add comments in LoadStore1
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 9 May 2021 19:14:28 +0000 (20:14 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 9 May 2021 19:14:28 +0000 (20:14 +0100)
src/soc/fu/ldst/loadstore.py
src/soc/simple/test/test_issuer_mmu.py

index a9dbaba365714eb9be7b9bd7a5ce25c8c5fec7ca..f3544b08f5615603f0071ed6fde3902daea42090 100644 (file)
@@ -187,6 +187,7 @@ class LoadStore1(PortInterfaceBase):
                 pass
             with m.Case(State.COMPLETE):
                 pass
+
         # microwatt: only if State.ACK_WAIZ
         with m.If(d_out.error):
             with m.If(d_out.cache_paradox):
@@ -242,6 +243,11 @@ class LoadStore1(PortInterfaceBase):
         with m.Else():
             m.d.sync += d_in.data.eq(0)
 
+        # this must move into the FSM, conditionally noticing that
+        # the "blip" comes from self.d_validblip.
+        # task 1: look up in dcache
+        # task 2: if dcache fails, look up in MMU.
+        # do **NOT** confuse the two.
         m.d.comb += d_in.load.eq(self.load)
         m.d.comb += d_in.byte_sel.eq(self.byte_sel)
         m.d.comb += d_in.addr.eq(self.addr)
index b24b73eb35c7a4397d7d572bfbfcc4968acfabed..4bf4d37a05792e5f04465a9801d7a2516d270457 100644 (file)
@@ -46,12 +46,12 @@ if __name__ == "__main__":
     #                          microwatt_mmu=True))
 
     # LD/ST tests should all still work
-    #suite.addTest(TestRunner(LDSTTestCase().test_data, svp64=svp64,
-    #                          microwatt_mmu=True))
+    suite.addTest(TestRunner(LDSTTestCase().test_data, svp64=svp64,
+                              microwatt_mmu=True))
 
     # LD/ST exception cases
-    suite.addTest(TestRunner(LDSTExceptionTestCase().test_data, svp64=svp64,
-                              microwatt_mmu=True))
+    #suite.addTest(TestRunner(LDSTExceptionTestCase().test_data, svp64=svp64,
+    #                          microwatt_mmu=True))
 
     runner = unittest.TextTestRunner()
     runner.run(suite)