pass
with m.Case(State.COMPLETE):
pass
+
# microwatt: only if State.ACK_WAIZ
with m.If(d_out.error):
with m.If(d_out.cache_paradox):
with m.Else():
m.d.sync += d_in.data.eq(0)
+ # this must move into the FSM, conditionally noticing that
+ # the "blip" comes from self.d_validblip.
+ # task 1: look up in dcache
+ # task 2: if dcache fails, look up in MMU.
+ # do **NOT** confuse the two.
m.d.comb += d_in.load.eq(self.load)
m.d.comb += d_in.byte_sel.eq(self.byte_sel)
m.d.comb += d_in.addr.eq(self.addr)
# microwatt_mmu=True))
# LD/ST tests should all still work
- #suite.addTest(TestRunner(LDSTTestCase().test_data, svp64=svp64,
- # microwatt_mmu=True))
+ suite.addTest(TestRunner(LDSTTestCase().test_data, svp64=svp64,
+ microwatt_mmu=True))
# LD/ST exception cases
- suite.addTest(TestRunner(LDSTExceptionTestCase().test_data, svp64=svp64,
- microwatt_mmu=True))
+ #suite.addTest(TestRunner(LDSTExceptionTestCase().test_data, svp64=svp64,
+ # microwatt_mmu=True))
runner = unittest.TextTestRunner()
runner.run(suite)