move part_sig_add to its own directory

diff --git a/Makefile2 b/Makefile2
deleted file mode 100755 (executable)
index 67b4c52..0000000
--- a/Makefile2
+++ /dev/null
@@ -1,26 +0,0 @@
-# -*- explicit-buffer-name: "Makefile<6502/cmos45>" -*-
-
-        LOGICAL_SYNTHESIS = Yosys
-       PHYSICAL_SYNTHESIS = Coriolis
-               DESIGN_KIT = sxlib
-
-#           YOSYS_FLATTEN = Yes
-            USE_CLOCKTREE = Yes
-                USE_DEBUG = No
-                 USE_KITE = No
-
-                 NETLISTS = $(shell cat nets2.txt)
-
-                VST_FLAGS = --vst-use-concat
-
- include ./mk/design-flow.mk
-
-
-blif:      part_sig_add.blif
-vst:       part_sig_add.vst
-layout:    part_sig_add_cts_r.ap
-gds:       part_sig_add_cts_r.gds
-
-lvx:       lvx-part_sig_add_cts_r
-druc:      druc-part_sig_add_cts_r
-view:      cgt-part_sig_add_cts_r

diff --git a/examples/part_sig_add.py b/examples/part_sig_add.py
deleted file mode 100644 (file)
index 532b216..0000000
--- a/examples/part_sig_add.py
+++ /dev/null
@@ -1,56 +0,0 @@
-from nmigen.cli import rtlil
-from ieee754.part.test.test_partsig import TestAddMod2
-import subprocess
-import os
-from nmigen import Signal
-
-def test():
-    width = 16
-    pmask = Signal(3)  # divide into 4-bits
-    module = TestAddMod2(width, pmask)
-    sim = create_ilang(module,
-                               [pmask,
-                                module.a.sig,
-                                module.b.sig,
-                                module.add_output,
-                                module.ls_output,
-                                module.sub_output,
-                                module.eq_output,
-                                module.gt_output,
-                                module.ge_output,
-                                module.ne_output,
-                                module.lt_output,
-                                module.le_output,
-                                module.mux_sel,
-                                module.mux_out,
-                                module.carry_in,
-                                module.add_carry_out,
-                                module.sub_carry_out,
-                                module.neg_output,
-                               ],
-                               "part_sig_add")
-                            
-def run_yosys(test_name):
-    liberty_file = os.getenv("HOME")+"/coriolis-2.x/src/alliance-check-toolkit/cells/nsxlib/nsxlib.lib"
-    print("test_name:",test_name)
-    cmd = [
-        "read_ilang part_sig_add.il",
-        "hierarchy -check -top part_sig_add",
-        "synth -top part_sig_add",
-        "dfflibmap -liberty "+liberty_file,
-        "abc -liberty "+liberty_file,
-        "clean",
-        "write_blif test.blif"
-    ]
-    cmd = "; ".join(cmd)
-    subprocess.call(["yosys","-p",cmd])
-
-def create_ilang(dut, ports, test_name):
-    vl = rtlil.convert(dut, name=test_name, ports=ports)
-    with open("%s.il" % test_name, "w") as f:
-        f.write(vl)
-    #run_yosys(test_name)
-
-
-if __name__ == "__main__":
-    test()

diff --git a/experiments2/Makefile b/experiments2/Makefile
new file mode 100755 (executable)
index 0000000..67b4c52
--- /dev/null
+++ b/experiments2/Makefile
@@ -0,0 +1,26 @@
+# -*- explicit-buffer-name: "Makefile<6502/cmos45>" -*-
+
+        LOGICAL_SYNTHESIS = Yosys
+       PHYSICAL_SYNTHESIS = Coriolis
+               DESIGN_KIT = sxlib
+
+#           YOSYS_FLATTEN = Yes
+            USE_CLOCKTREE = Yes
+                USE_DEBUG = No
+                 USE_KITE = No
+
+                 NETLISTS = $(shell cat nets2.txt)
+
+                VST_FLAGS = --vst-use-concat
+
+ include ./mk/design-flow.mk
+
+
+blif:      part_sig_add.blif
+vst:       part_sig_add.vst
+layout:    part_sig_add_cts_r.ap
+gds:       part_sig_add_cts_r.gds
+
+lvx:       lvx-part_sig_add_cts_r
+druc:      druc-part_sig_add_cts_r
+view:      cgt-part_sig_add_cts_r

diff --git a/experiments2/coriolis2/__init__.py b/experiments2/coriolis2/__init__.py
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/experiments2/coriolis2/katana.py b/experiments2/coriolis2/katana.py
new file mode 100644 (file)
index 0000000..442b2fc
--- /dev/null
+++ b/experiments2/coriolis2/katana.py
@@ -0,0 +1,12 @@
+
+from Hurricane import DebugSession
+
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12494_n543' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'dl(6)' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'n0_dl_7_0_6' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12509_n822' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12509_n734' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12509_n1386' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12494_n763' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12494_n800' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12491_n428_1' ) )

diff --git a/experiments2/coriolis2/settings.py b/experiments2/coriolis2/settings.py
new file mode 100644 (file)
index 0000000..95cc039
--- /dev/null
+++ b/experiments2/coriolis2/settings.py
@@ -0,0 +1,56 @@
+# -*- Mode:Python -*-
+
+import os
+import Cfg
+import CRL
+import Viewer
+#import node180.scn6m_deep_09
+import symbolic.cmos
+from   helpers       import l, u, n
+
+
+Cfg.Configuration.pushDefaultPriority( Cfg.Parameter.Priority.UserFile )
+
+
+Viewer.Graphics.setStyle( 'Alliance.Classic [black]' )
+ 
+Cfg.getParamBool      ( 'misc.catchCore'              ).setBool      ( False   )
+Cfg.getParamBool      ( 'misc.info'                   ).setBool      ( False   )
+Cfg.getParamBool      ( 'misc.paranoid'               ).setBool      ( False   )
+Cfg.getParamBool      ( 'misc.bug'                    ).setBool      ( False   )
+Cfg.getParamBool      ( 'misc.logMode'                ).setBool      ( True   )
+Cfg.getParamBool      ( 'misc.verboseLevel1'          ).setBool      ( True    )
+Cfg.getParamBool      ( 'misc.verboseLevel2'          ).setBool      ( True    )
+Cfg.getParamInt       ( 'misc.minTraceLevel'          ).setInt       ( 159     )
+Cfg.getParamInt       ( 'misc.maxTraceLevel'          ).setInt       ( 160     )
+Cfg.getParamEnumerate ( 'etesian.effort'              ).setInt       ( 2       )
+Cfg.getParamPercentage( 'etesian.spaceMargin'         ).setPercentage( 20.0    )
+Cfg.getParamPercentage( 'etesian.aspectRatio'         ).setPercentage( 100.0   )
+Cfg.getParamBool      ( 'etesian.uniformDensity'      ).setBool      ( True    )
+Cfg.getParamInt       ( 'anabatic.edgeLenght'         ).setInt       ( 24      )
+Cfg.getParamInt       ( 'anabatic.edgeWidth'          ).setInt       ( 8       )
+Cfg.getParamString    ( 'anabatic.topRoutingLayer'    ).setString    ( 'METAL5')
+Cfg.getParamInt       ( 'katana.eventsLimit'          ).setInt       ( 1000000 )
+Cfg.getParamInt       ( 'katana.hTracksReservedLocal' ).setInt       ( 7       )
+Cfg.getParamInt       ( 'katana.vTracksReservedLocal' ).setInt       ( 6       )
+#Cfg.getParamInt       ( 'clockTree.minimumSide'       ).setInt       ( l(1000) )
+
+Cfg.Configuration.popDefaultPriority()
+
+#cellsTop = os.path.abspath( os.getcwd()+'/../cells' )
+if os.environ.has_key('CELLS_TOP'):
+  cellsTop = os.environ['CELLS_TOP']
+else:
+  cellsTop = '../../../cells'
+
+af  = CRL.AllianceFramework.get()
+env = af.getEnvironment()
+env.addSYSTEM_LIBRARY( library=cellsTop+'/nsxlib', mode=CRL.Environment.Prepend )
+env.addSYSTEM_LIBRARY( library=cellsTop+'/mpxlib', mode=CRL.Environment.Prepend )
+env.setCLOCK( '^clk$|m_clock' )
+env.setPOWER( 'vdd' )
+env.setGROUND( 'vss' )
+
+
+print 'Successfully read user configuration'
+

diff --git a/experiments2/nets2.txt b/experiments2/nets2.txt
new file mode 100644 (file)
index 0000000..22ddba7
--- /dev/null
+++ b/experiments2/nets2.txt
@@ -0,0 +1,45 @@
+part_sig_add
+mux0
+mux1
+mux2
+gtc
+reorder
+gt1
+mux0$$2
+mux1$$3
+mux2$$4
+gtc$$1
+reorder$$5
+eq1
+mux0$$7
+mux1$$8
+mux2$$9
+gtc$$6
+reorder$$10
+ge1
+mux0$$12
+mux1$$13
+mux2$$14
+gtc$$11
+reorder$$15
+gt2
+mux0$$17
+mux1$$18
+mux2$$19
+gtc$$16
+reorder$$20
+eq2
+mux0$$22
+mux1$$23
+mux2$$24
+gtc$$21
+reorder$$25
+ge2
+ripple
+add1
+ripple$$26
+add2
+ripple$$27
+add3
+ls1
+pmux1

diff --git a/experiments2/part_sig_add.py b/experiments2/part_sig_add.py
new file mode 100644 (file)
index 0000000..532b216
--- /dev/null
+++ b/experiments2/part_sig_add.py
@@ -0,0 +1,56 @@
+from nmigen.cli import rtlil
+from ieee754.part.test.test_partsig import TestAddMod2
+import subprocess
+import os
+from nmigen import Signal
+
+def test():
+    width = 16
+    pmask = Signal(3)  # divide into 4-bits
+    module = TestAddMod2(width, pmask)
+    sim = create_ilang(module,
+                               [pmask,
+                                module.a.sig,
+                                module.b.sig,
+                                module.add_output,
+                                module.ls_output,
+                                module.sub_output,
+                                module.eq_output,
+                                module.gt_output,
+                                module.ge_output,
+                                module.ne_output,
+                                module.lt_output,
+                                module.le_output,
+                                module.mux_sel,
+                                module.mux_out,
+                                module.carry_in,
+                                module.add_carry_out,
+                                module.sub_carry_out,
+                                module.neg_output,
+                               ],
+                               "part_sig_add")
+                            
+def run_yosys(test_name):
+    liberty_file = os.getenv("HOME")+"/coriolis-2.x/src/alliance-check-toolkit/cells/nsxlib/nsxlib.lib"
+    print("test_name:",test_name)
+    cmd = [
+        "read_ilang part_sig_add.il",
+        "hierarchy -check -top part_sig_add",
+        "synth -top part_sig_add",
+        "dfflibmap -liberty "+liberty_file,
+        "abc -liberty "+liberty_file,
+        "clean",
+        "write_blif test.blif"
+    ]
+    cmd = "; ".join(cmd)
+    subprocess.call(["yosys","-p",cmd])
+
+def create_ilang(dut, ports, test_name):
+    vl = rtlil.convert(dut, name=test_name, ports=ports)
+    with open("%s.il" % test_name, "w") as f:
+        f.write(vl)
+    #run_yosys(test_name)
+
+
+if __name__ == "__main__":
+    test()

diff --git a/nets2.txt b/nets2.txt
deleted file mode 100644 (file)
index 22ddba7..0000000
--- a/nets2.txt
+++ /dev/null
@@ -1,45 +0,0 @@
-part_sig_add
-mux0
-mux1
-mux2
-gtc
-reorder
-gt1
-mux0$$2
-mux1$$3
-mux2$$4
-gtc$$1
-reorder$$5
-eq1
-mux0$$7
-mux1$$8
-mux2$$9
-gtc$$6
-reorder$$10
-ge1
-mux0$$12
-mux1$$13
-mux2$$14
-gtc$$11
-reorder$$15
-gt2
-mux0$$17
-mux1$$18
-mux2$$19
-gtc$$16
-reorder$$20
-eq2
-mux0$$22
-mux1$$23
-mux2$$24
-gtc$$21
-reorder$$25
-ge2
-ripple
-add1
-ripple$$26
-add2
-ripple$$27
-add3
-ls1
-pmux1