remove rdflags in pipe_data.py (redundant)

diff --git a/src/soc/fu/alu/pipe_data.py b/src/soc/fu/alu/pipe_data.py
index b9423944877d54a8bb4113f4dce8a44dc5e6e9a1..5b9766e295397fb74c94ecf4a086e6868605599c 100644 (file)
--- a/src/soc/fu/alu/pipe_data.py
+++ b/src/soc/fu/alu/pipe_data.py
@@ -68,7 +68,3 @@ class ALUOutputData(IntegerData):
 class ALUPipeSpec(CommonPipeSpec):
     regspec = (ALUInputData.regspec, ALUOutputData.regspec)
     opsubsetkls = CompALUOpSubset
-    def rdflags(self, e): # in order of regspec
-        reg1_ok = e.read_reg1.ok # RA
-        reg2_ok = e.read_reg2.ok # RB
-        return Cat(reg1_ok, reg2_ok, 1, 1) # RA RB CA SO

diff --git a/src/soc/fu/branch/pipe_data.py b/src/soc/fu/branch/pipe_data.py
index f8481db397841a7071a07e933348b3deadf7d83e..78c4f0f972807094f19159df3b8be80e4f65da6f 100644 (file)
--- a/src/soc/fu/branch/pipe_data.py
+++ b/src/soc/fu/branch/pipe_data.py
@@ -93,8 +93,3 @@ class BranchOutputData(IntegerData):
 class BranchPipeSpec(CommonPipeSpec):
     regspec = (BranchInputData.regspec, BranchOutputData.regspec)
     opsubsetkls = CompBROpSubset
-    def rdflags(self, e): # in order of regspec
-        cr1_en = e.read_cr1.ok # CR A
-        fast1_ok = e.read_fast1.ok # SPR1
-        fast2_ok = e.read_fast2.ok # SPR2
-        return Cat(fast1_ok, fast2_ok, cr1_en, 1) # SPR1 SPR2 CR CIA

diff --git a/src/soc/fu/compunits/compunits.py b/src/soc/fu/compunits/compunits.py
index 203055ad1cf3e3f1eabf0e80d93ad3157fe0c6c6..7eaecdb3a949498a70b7e52fa61c9c93a375a07b 100644 (file)
--- a/src/soc/fu/compunits/compunits.py
+++ b/src/soc/fu/compunits/compunits.py
@@ -40,6 +40,8 @@ see:
 
 """
 
+# imports
+
 from nmigen import Cat
 from nmigen.cli import rtlil
 from soc.experiment.compalu_multi import MultiCompUnit
@@ -91,10 +93,6 @@ class FunctionUnitBaseSingle(MultiCompUnit):
         alu = pipekls(pspec)                     # create actual NNNBasePipe
         super().__init__(regspec, alu, opsubset) # pass to MultiCompUnit
 
-    def rdflags(self, e):
-        print (dir(self.alu))
-        return self.alu.pspec.rdflags(e)
-
 
 ##############################################################
 # TODO: ReservationStations-based (FunctionUnitBaseConcurrent)

diff --git a/src/soc/fu/cr/pipe_data.py b/src/soc/fu/cr/pipe_data.py
index a7291c6c3d4e1d6cec184193fff7bf6f86b7be4d..24402270c9ed0472d4a38689a3a1c6d6a807851d 100644 (file)
--- a/src/soc/fu/cr/pipe_data.py
+++ b/src/soc/fu/cr/pipe_data.py
@@ -74,11 +74,3 @@ class CROutputData(IntegerData):
 class CRPipeSpec(CommonPipeSpec):
     regspec = (CRInputData.regspec, CROutputData.regspec)
     opsubsetkls = CompCROpSubset
-    def rdflags(self, e): # in order of regspec
-        reg1_ok = e.read_reg1.ok # RA/RC
-        reg2_ok = e.read_reg2.ok # RB
-        full_reg = e.read_cr_whole # full CR
-        cr1_en = e.read_cr1.ok # CR A
-        cr2_en = e.read_cr2.ok # CR B
-        cr3_en = e.read_cr3.ok # CR C
-        return Cat(reg1_ok, reg2_ok, full_reg, cr1_en, cr2_en, cr3_en)

diff --git a/src/soc/fu/logical/pipe_data.py b/src/soc/fu/logical/pipe_data.py
index 6512324d67e144954d5465aad268a2a0a7200e49..37e86d5aec1834aaf7ce5c78708b10619f424e8f 100644 (file)
--- a/src/soc/fu/logical/pipe_data.py
+++ b/src/soc/fu/logical/pipe_data.py
@@ -58,7 +58,3 @@ class LogicalOutputData(IntegerData):
 class LogicalPipeSpec(CommonPipeSpec):
     regspec = (LogicalInputData.regspec, LogicalOutputData.regspec)
     opsubsetkls = CompLogicalOpSubset
-    def rdflags(self, e): # in order of regspec
-        reg1_ok = e.read_reg1.ok # RA
-        reg2_ok = e.read_reg2.ok # RB
-        return Cat(reg1_ok, reg2_ok) # RA RB

diff --git a/src/soc/fu/shift_rot/pipe_data.py b/src/soc/fu/shift_rot/pipe_data.py
index 46d383a0300421a18b75f5c6d748f601d1c586af..044857526534a8382383b085feb5b8a62311beea 100644 (file)
--- a/src/soc/fu/shift_rot/pipe_data.py
+++ b/src/soc/fu/shift_rot/pipe_data.py
@@ -38,8 +38,3 @@ class ShiftRotInputData(IntegerData):
 class ShiftRotPipeSpec(CommonPipeSpec):
     regspec = (ShiftRotInputData.regspec, LogicalOutputData.regspec)
     opsubsetkls = CompSROpSubset
-    def rdflags(self, e): # in order of regspec input
-        reg1_ok = e.read_reg1.ok # RA
-        reg2_ok = e.read_reg2.ok # RB
-        reg3_ok = e.read_reg3.ok # RS
-        return Cat(reg1_ok, reg2_ok, reg3_ok, 1) # RA RB RC CA