This doesn't work yet.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
C_SOURCES = \
r600_buffer.c \
r600_state2.c \
+ evergreen_state.c \
r600_context.c \
r600_shader.c \
r600_draw.c \
--- /dev/null
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/* TODO:
+ * - fix mask for depth control & cull for query
+ */
+#include <stdio.h>
+#include <errno.h>
+#include <pipe/p_defines.h>
+#include <pipe/p_state.h>
+#include <pipe/p_context.h>
+#include <tgsi/tgsi_scan.h>
+#include <tgsi/tgsi_parse.h>
+#include <tgsi/tgsi_util.h>
+#include <util/u_blitter.h>
+#include <util/u_double_list.h>
+#include <util/u_transfer.h>
+#include <util/u_surface.h>
+#include <util/u_pack_color.h>
+#include <util/u_memory.h>
+#include <util/u_inlines.h>
+#include <pipebuffer/pb_buffer.h>
+#include "r600.h"
+#include "evergreend.h"
+struct radeon_state {
+ unsigned dummy;
+};
+#include "r600_resource.h"
+#include "r600_shader.h"
+#include "r600_pipe.h"
+#include "eg_state_inlines.h"
+
+static void evergreen_set_blend_color(struct pipe_context *ctx,
+ const struct pipe_blend_color *state)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
+
+ if (rstate == NULL)
+ return;
+
+ rstate->id = R600_PIPE_STATE_BLEND_COLOR;
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
+ free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
+ rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
+ r600_context_pipe_state_set(&rctx->ctx, rstate);
+}
+
+static void *evergreen_create_blend_state(struct pipe_context *ctx,
+ const struct pipe_blend_state *state)
+{
+ struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
+ struct r600_pipe_state *rstate;
+ u32 color_control, target_mask;
+
+ if (blend == NULL) {
+ return NULL;
+ }
+ rstate = &blend->rstate;
+
+ rstate->id = R600_PIPE_STATE_BLEND;
+
+ target_mask = 0;
+ color_control = S_028808_MODE(1);
+ if (state->logicop_enable) {
+ color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
+ } else {
+ color_control |= (0xcc << 16);
+ }
+ /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
+ if (state->independent_blend_enable) {
+ for (int i = 0; i < 8; i++) {
+ target_mask |= (state->rt[i].colormask << (4 * i));
+ }
+ } else {
+ for (int i = 0; i < 8; i++) {
+ target_mask |= (state->rt[0].colormask << (4 * i));
+ }
+ }
+ blend->cb_target_mask = target_mask;
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028808_CB_COLOR_CONTROL,
+ color_control, 0xFFFFFFFF, NULL);
+ return rstate;
+}
+
+static void evergreen_bind_blend_state(struct pipe_context *ctx, void *state)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
+ struct r600_pipe_state *rstate;
+
+ if (state == NULL)
+ return;
+ rstate = &blend->rstate;
+ rctx->states[rstate->id] = rstate;
+ rctx->cb_target_mask = blend->cb_target_mask;
+ r600_context_pipe_state_set(&rctx->ctx, rstate);
+}
+
+static void *evergreen_create_dsa_state(struct pipe_context *ctx,
+ const struct pipe_depth_stencil_alpha_state *state)
+{
+ struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
+ unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
+ unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
+
+ if (rstate == NULL) {
+ return NULL;
+ }
+
+ rstate->id = R600_PIPE_STATE_DSA;
+ /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
+ /* db_shader_control is 0xFFFFFFBE as Z_EXPORT_ENABLE (bit 0) will be
+ * set by fragment shader if it export Z and KILL_ENABLE (bit 6) will
+ * be set if shader use texkill instruction
+ */
+ db_shader_control = 0x210;
+ stencil_ref_mask = 0;
+ stencil_ref_mask_bf = 0;
+ db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
+ S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
+ S_028800_ZFUNC(state->depth.func);
+
+ /* stencil */
+ if (state->stencil[0].enabled) {
+ db_depth_control |= S_028800_STENCIL_ENABLE(1);
+ db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
+ db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
+ db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
+ db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
+
+
+ stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
+ S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
+ if (state->stencil[1].enabled) {
+ db_depth_control |= S_028800_BACKFACE_ENABLE(1);
+ db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
+ db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
+ db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
+ db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
+ stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
+ S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
+ }
+ }
+
+ /* alpha */
+ alpha_test_control = 0;
+ alpha_ref = 0;
+ if (state->alpha.enabled) {
+ alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
+ alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
+ alpha_ref = fui(state->alpha.ref_value);
+ }
+
+ /* misc */
+ db_render_control = 0;
+ db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
+ S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
+ S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
+ /* TODO db_render_override depends on query */
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028430_DB_STENCILREFMASK, stencil_ref_mask,
+ 0xFFFFFFFF & C_028430_STENCILREF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
+ 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBE, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028D0C_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028D10_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
+
+ return rstate;
+}
+
+static void *evergreen_create_rs_state(struct pipe_context *ctx,
+ const struct pipe_rasterizer_state *state)
+{
+ struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
+ struct r600_pipe_state *rstate;
+ float offset_units = 0, offset_scale = 0;
+ unsigned offset_db_fmt_cntl = 0;
+ unsigned tmp;
+ unsigned prov_vtx = 1;
+
+ if (rs == NULL) {
+ return NULL;
+ }
+
+ rstate = &rs->rstate;
+ rs->flatshade = state->flatshade;
+ rs->sprite_coord_enable = state->sprite_coord_enable;
+
+ rstate->id = R600_PIPE_STATE_RASTERIZER;
+ if (state->flatshade_first)
+ prov_vtx = 0;
+ tmp = 0x00000001;
+ if (state->sprite_coord_enable) {
+ tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
+ S_0286D4_PNT_SPRITE_OVRD_X(2) |
+ S_0286D4_PNT_SPRITE_OVRD_Y(3) |
+ S_0286D4_PNT_SPRITE_OVRD_Z(0) |
+ S_0286D4_PNT_SPRITE_OVRD_W(1);
+ if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
+ tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
+ }
+ }
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
+
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028814_PA_SU_SC_MODE_CNTL,
+ S_028814_PROVOKING_VTX_LAST(prov_vtx) |
+ S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
+ S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
+ S_028814_FACE(!state->front_ccw) |
+ S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
+ S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
+ S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02881C_PA_CL_VS_OUT_CNTL,
+ S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
+ S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
+ /* point size 12.4 fixed point */
+ tmp = (unsigned)(state->point_size * 8.0);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A08_PA_SU_LINE_CNTL, 0x00000008, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, fui(offset_scale), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, fui(offset_scale), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units), 0xFFFFFFFF, NULL);
+ return rstate;
+}
+
+static void evergreen_bind_rs_state(struct pipe_context *ctx, void *state)
+{
+ struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+
+ if (state == NULL)
+ return;
+
+ if (rctx->flatshade != rs->flatshade) {
+// rctx->ps_rebuild = TRUE;
+ }
+ if (rctx->sprite_coord_enable != rs->sprite_coord_enable) {
+// rctx->ps_rebuild = TRUE;
+ }
+ rctx->flatshade = rs->flatshade;
+ rctx->sprite_coord_enable = rs->sprite_coord_enable;
+
+ rctx->states[rs->rstate.id] = &rs->rstate;
+ r600_context_pipe_state_set(&rctx->ctx, &rs->rstate);
+}
+
+static void evergreen_delete_rs_state(struct pipe_context *ctx, void *state)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
+
+ if (rctx->states[rs->rstate.id] == &rs->rstate) {
+ rctx->states[rs->rstate.id] = NULL;
+ }
+ free(rs);
+}
+
+static void *evergreen_create_sampler_state(struct pipe_context *ctx,
+ const struct pipe_sampler_state *state)
+{
+ struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
+ union util_color uc;
+
+ if (rstate == NULL) {
+ return NULL;
+ }
+
+ rstate->id = R600_PIPE_STATE_SAMPLER;
+ util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_SAMPLER, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
+ S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
+ S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
+ S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
+ S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
+ S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
+ S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
+ S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
+ S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
+ /* FIXME LOD it depends on texture base level ... */
+ r600_pipe_state_add_reg(rstate, R600_GROUP_SAMPLER, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
+ S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
+ S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)),
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_SAMPLER, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
+ S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)) |
+ S_03C008_TYPE(1),
+ 0xFFFFFFFF, NULL);
+
+ if (uc.ui) {
+ /* TODO border color */
+ }
+ return rstate;
+}
+
+static void *evergreen_create_vertex_elements(struct pipe_context *ctx,
+ unsigned count,
+ const struct pipe_vertex_element *elements)
+{
+ struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
+
+ assert(count < 32);
+ v->count = count;
+ v->refcount = 1;
+ memcpy(v->elements, elements, count * sizeof(struct pipe_vertex_element));
+ return v;
+}
+
+static void evergreen_sampler_view_destroy(struct pipe_context *ctx,
+ struct pipe_sampler_view *state)
+{
+ struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
+
+ pipe_resource_reference(&state->texture, NULL);
+ FREE(resource);
+}
+
+static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
+ struct pipe_resource *texture,
+ const struct pipe_sampler_view *state)
+{
+ struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
+ struct r600_pipe_state *rstate;
+ const struct util_format_description *desc;
+ struct r600_resource_texture *tmp;
+ struct r600_resource *rbuffer;
+ unsigned format;
+ uint32_t word4 = 0, yuv_format = 0, pitch = 0;
+ unsigned char swizzle[4];
+ struct radeon_ws_bo *bo[2];
+
+ if (resource == NULL)
+ return NULL;
+ rstate = &resource->state;
+
+ /* initialize base object */
+ resource->base = *state;
+ resource->base.texture = NULL;
+ pipe_reference(NULL, &texture->reference);
+ resource->base.texture = texture;
+ resource->base.reference.count = 1;
+ resource->base.context = ctx;
+
+ swizzle[0] = state->swizzle_r;
+ swizzle[1] = state->swizzle_g;
+ swizzle[2] = state->swizzle_b;
+ swizzle[3] = state->swizzle_a;
+ format = r600_translate_texformat(texture->format,
+ swizzle,
+ &word4, &yuv_format);
+ if (format == ~0) {
+ format = 0;
+ }
+ desc = util_format_description(texture->format);
+ if (desc == NULL) {
+ R600_ERR("unknow format %d\n", texture->format);
+ }
+ tmp = (struct r600_resource_texture*)texture;
+ rbuffer = &tmp->resource;
+ bo[0] = rbuffer->bo;
+ bo[1] = rbuffer->bo;
+ /* FIXME depth texture decompression */
+ if (tmp->depth) {
+#if 0
+ r = evergreen_texture_from_depth(ctx, tmp, view->first_level);
+ if (r) {
+ return;
+ }
+ bo[0] = radeon_ws_bo_incref(rscreen->rw, tmp->uncompressed);
+ bo[1] = radeon_ws_bo_incref(rscreen->rw, tmp->uncompressed);
+#endif
+ }
+ pitch = align(tmp->pitch[0] / tmp->bpt, 8);
+
+ /* FIXME properly handle first level != 0 */
+ r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_030000_RESOURCE0_WORD0,
+ S_030000_DIM(r600_tex_dim(texture->target)) |
+ S_030000_PITCH((pitch / 8) - 1) |
+ S_030000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_030004_RESOURCE0_WORD1,
+ S_030004_TEX_HEIGHT(texture->height0 - 1) |
+ S_030004_TEX_DEPTH(texture->depth0 - 1),
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_030008_RESOURCE0_WORD2,
+ tmp->offset[0] >> 8, 0xFFFFFFFF, bo[0]);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_03000C_RESOURCE0_WORD3,
+ tmp->offset[1] >> 8, 0xFFFFFFFF, bo[1]);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_030010_RESOURCE0_WORD4,
+ word4 | S_030010_NUM_FORMAT_ALL(V_030010_SQ_NUM_FORMAT_NORM) |
+ S_030010_SRF_MODE_ALL(V_030010_SFR_MODE_NO_ZERO) |
+ S_030010_REQUEST_SIZE(1) |
+ S_030010_BASE_LEVEL(state->first_level), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_030014_RESOURCE0_WORD5,
+ S_030014_LAST_LEVEL(state->last_level) |
+ S_030014_BASE_ARRAY(0) |
+ S_030014_LAST_ARRAY(0), 0xffffffff, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_030018_RESOURCE0_WORD6, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_03001C_RESOURCE0_WORD7,
+ S_03001C_DATA_FORMAT(format) |
+ S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
+
+ return &resource->base;
+}
+
+static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
+ struct pipe_sampler_view **views)
+{
+ /* TODO */
+ assert(1);
+}
+
+static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
+ struct pipe_sampler_view **views)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
+
+ for (int i = 0; i < count; i++) {
+ if (resource[i]) {
+ r600_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state, i);
+ }
+ }
+}
+
+static void evergreen_bind_state(struct pipe_context *ctx, void *state)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
+
+ if (state == NULL)
+ return;
+ rctx->states[rstate->id] = rstate;
+ r600_context_pipe_state_set(&rctx->ctx, rstate);
+}
+
+static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
+
+ for (int i = 0; i < count; i++) {
+ r600_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
+ }
+}
+
+static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
+
+ /* TODO implement */
+ for (int i = 0; i < count; i++) {
+ r600_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
+ }
+}
+
+static void evergreen_delete_state(struct pipe_context *ctx, void *state)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
+
+ if (rctx->states[rstate->id] == rstate) {
+ rctx->states[rstate->id] = NULL;
+ }
+ for (int i = 0; i < rstate->nregs; i++) {
+ radeon_ws_bo_reference(rctx->radeon, &rstate->regs[i].bo, NULL);
+ }
+ free(rstate);
+}
+
+static void evergreen_delete_vertex_element(struct pipe_context *ctx, void *state)
+{
+ struct r600_vertex_element *v = (struct r600_vertex_element*)state;
+
+ if (v == NULL)
+ return;
+ if (--v->refcount)
+ return;
+ free(v);
+}
+
+static void evergreen_set_clip_state(struct pipe_context *ctx,
+ const struct pipe_clip_state *state)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
+
+ if (rstate == NULL)
+ return;
+
+ rctx->clip = *state;
+ rstate->id = R600_PIPE_STATE_CLIP;
+ for (int i = 0; i < state->nr; i++) {
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_0285BC_PA_CL_UCP0_X + i * 4,
+ fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_0285C0_PA_CL_UCP0_Y + i * 4,
+ fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_0285C4_PA_CL_UCP0_Z + i * 4,
+ fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_0285C8_PA_CL_UCP0_W + i * 4,
+ fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
+ }
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028810_PA_CL_CLIP_CNTL,
+ S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
+ S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
+ S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
+
+ free(rctx->states[R600_PIPE_STATE_CLIP]);
+ rctx->states[R600_PIPE_STATE_CLIP] = rstate;
+ r600_context_pipe_state_set(&rctx->ctx, rstate);
+}
+
+static void evergreen_bind_vertex_elements(struct pipe_context *ctx, void *state)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_vertex_element *v = (struct r600_vertex_element*)state;
+
+ evergreen_delete_vertex_element(ctx, rctx->vertex_elements);
+ rctx->vertex_elements = v;
+ if (v) {
+ v->refcount++;
+// rctx->vs_rebuild = TRUE;
+ }
+}
+
+static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
+ const struct pipe_poly_stipple *state)
+{
+}
+
+static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
+{
+}
+
+static void evergreen_set_scissor_state(struct pipe_context *ctx,
+ const struct pipe_scissor_state *state)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
+ u32 tl, br;
+
+ if (rstate == NULL)
+ return;
+
+ rstate->id = R600_PIPE_STATE_SCISSOR;
+ tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
+ br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028210_PA_SC_CLIPRECT_0_TL, tl,
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028214_PA_SC_CLIPRECT_0_BR, br,
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028218_PA_SC_CLIPRECT_1_TL, tl,
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_02821C_PA_SC_CLIPRECT_1_BR, br,
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028220_PA_SC_CLIPRECT_2_TL, tl,
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028224_PA_SC_CLIPRECT_2_BR, br,
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028228_PA_SC_CLIPRECT_3_TL, tl,
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_02822C_PA_SC_CLIPRECT_3_BR, br,
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_02820C_PA_SC_CLIPRECT_RULE, 0x0000FFFF,
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
+ 0xFFFFFFFF, NULL);
+
+ free(rctx->states[R600_PIPE_STATE_SCISSOR]);
+ rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
+ r600_context_pipe_state_set(&rctx->ctx, rstate);
+}
+
+static void evergreen_set_stencil_ref(struct pipe_context *ctx,
+ const struct pipe_stencil_ref *state)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
+ u32 tmp;
+
+ if (rstate == NULL)
+ return;
+
+ rctx->stencil_ref = *state;
+ rstate->id = R600_PIPE_STATE_STENCIL_REF;
+ tmp = S_028430_STENCILREF(state->ref_value[0]);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028430_DB_STENCILREFMASK, tmp,
+ ~C_028430_STENCILREF, NULL);
+ tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028434_DB_STENCILREFMASK_BF, tmp,
+ ~C_028434_STENCILREF_BF, NULL);
+
+ free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
+ rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
+ r600_context_pipe_state_set(&rctx->ctx, rstate);
+}
+
+static void evergreen_set_viewport_state(struct pipe_context *ctx,
+ const struct pipe_viewport_state *state)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
+
+ if (rstate == NULL)
+ return;
+
+ rctx->viewport = *state;
+ rstate->id = R600_PIPE_STATE_VIEWPORT;
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
+
+ free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
+ rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
+ r600_context_pipe_state_set(&rctx->ctx, rstate);
+}
+
+static void evergreen_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
+ const struct pipe_framebuffer_state *state, int cb)
+{
+ struct r600_resource_texture *rtex;
+ struct r600_resource *rbuffer;
+ unsigned level = state->cbufs[cb]->level;
+ unsigned pitch, slice;
+ unsigned color_info;
+ unsigned format, swap, ntype;
+ const struct util_format_description *desc;
+ struct radeon_ws_bo *bo[3];
+
+ rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
+ rbuffer = &rtex->resource;
+ bo[0] = rbuffer->bo;
+ bo[1] = rbuffer->bo;
+ bo[2] = rbuffer->bo;
+
+ pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
+ slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
+ ntype = 0;
+ desc = util_format_description(rtex->resource.base.b.format);
+ if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
+ ntype = V_028C70_NUMBER_SRGB;
+
+ format = r600_translate_colorformat(rtex->resource.base.b.format);
+ swap = r600_translate_colorswap(rtex->resource.base.b.format);
+ color_info = S_028C70_FORMAT(format) |
+ S_028C70_COMP_SWAP(swap) |
+ S_028C70_BLEND_CLAMP(1) |
+ S_028C70_SOURCE_FORMAT(1) |
+ S_028C70_NUMBER_TYPE(ntype);
+
+ /* FIXME handle enabling of CB beyond BASE8 which has different offset */
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028C60_CB_COLOR0_BASE + cb * 0x3C,
+ state->cbufs[cb]->offset >> 8, 0xFFFFFFFF, bo[0]);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028C70_CB_COLOR0_INFO + cb * 0x3C,
+ color_info, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
+ S_028C64_PITCH_TILE_MAX(pitch),
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
+ S_028C68_SLICE_TILE_MAX(slice),
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
+ 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
+ S_028C74_NON_DISP_TILING_ORDER(1),
+ 0xFFFFFFFF, NULL);
+}
+
+static void evergreen_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
+ const struct pipe_framebuffer_state *state)
+{
+ struct r600_resource_texture *rtex;
+ struct r600_resource *rbuffer;
+ unsigned level;
+ unsigned pitch, slice, format;
+
+ if (state->zsbuf == NULL)
+ return;
+
+ rtex = (struct r600_resource_texture*)state->zsbuf->texture;
+ rtex->tiled = 1;
+ rtex->array_mode = 2;
+ rtex->tile_type = 1;
+ rtex->depth = 1;
+ rbuffer = &rtex->resource;
+
+ level = state->zsbuf->level;
+ pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
+ slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
+ format = r600_translate_dbformat(state->zsbuf->texture->format);
+
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028048_DB_Z_READ_BASE,
+ state->zsbuf->offset >> 8, 0xFFFFFFFF, rbuffer->bo);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028050_DB_Z_WRITE_BASE,
+ state->zsbuf->offset >> 8, 0xFFFFFFFF, rbuffer->bo);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028008_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028040_DB_Z_INFO,
+ S_028040_ARRAY_MODE(rtex->array_mode) | S_028040_FORMAT(format),
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028058_DB_DEPTH_SIZE,
+ S_028058_PITCH_TILE_MAX(pitch),
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02805C_DB_DEPTH_SLICE,
+ S_02805C_SLICE_TILE_MAX(slice),
+ 0xFFFFFFFF, NULL);
+}
+
+static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
+ const struct pipe_framebuffer_state *state)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
+ u32 shader_mask, tl, br, target_mask;
+
+ if (rstate == NULL)
+ return;
+
+ /* unreference old buffer and reference new one */
+ rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
+ for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
+ pipe_surface_reference(&rctx->framebuffer.cbufs[i], NULL);
+ }
+ for (int i = 0; i < state->nr_cbufs; i++) {
+ pipe_surface_reference(&rctx->framebuffer.cbufs[i], state->cbufs[i]);
+ }
+ pipe_surface_reference(&rctx->framebuffer.zsbuf, state->zsbuf);
+ rctx->framebuffer = *state;
+
+ /* build states */
+ for (int i = 0; i < state->nr_cbufs; i++) {
+ evergreen_cb(rctx, rstate, state, i);
+ }
+ if (state->zsbuf) {
+ evergreen_db(rctx, rstate, state);
+ }
+
+ target_mask = 0x00000000;
+ target_mask = 0xFFFFFFFF;
+ shader_mask = 0;
+ for (int i = 0; i < state->nr_cbufs; i++) {
+ target_mask ^= 0xf << (i * 4);
+ shader_mask |= 0xf << (i * 4);
+ }
+ tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
+ br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
+
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
+ 0xFFFFFFFF, NULL);
+
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028238_CB_TARGET_MASK,
+ 0x00000000, target_mask, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02823C_CB_SHADER_MASK,
+ shader_mask, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C04_PA_SC_AA_CONFIG,
+ 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
+ 0x00000000, 0xFFFFFFFF, NULL);
+
+ free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
+ rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
+ r600_context_pipe_state_set(&rctx->ctx, rstate);
+}
+
+static void evergreen_set_index_buffer(struct pipe_context *ctx,
+ const struct pipe_index_buffer *ib)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+
+ if (ib) {
+ pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
+ memcpy(&rctx->index_buffer, ib, sizeof(rctx->index_buffer));
+ } else {
+ pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
+ memset(&rctx->index_buffer, 0, sizeof(rctx->index_buffer));
+ }
+
+ /* TODO make this more like a state */
+}
+
+static void evergreen_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
+ const struct pipe_vertex_buffer *buffers)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+
+ for (int i = 0; i < rctx->nvertex_buffer; i++) {
+ pipe_resource_reference(&rctx->vertex_buffer[i].buffer, NULL);
+ }
+ memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count);
+ for (int i = 0; i < count; i++) {
+ rctx->vertex_buffer[i].buffer = NULL;
+ pipe_resource_reference(&rctx->vertex_buffer[i].buffer, buffers[i].buffer);
+ }
+ rctx->nvertex_buffer = count;
+}
+
+static void evergreen_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
+ struct pipe_resource *buffer)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_resource *rbuffer = (struct r600_resource*)buffer;
+
+ switch (shader) {
+ case PIPE_SHADER_VERTEX:
+ rctx->vs_const_buffer.nregs = 0;
+ r600_pipe_state_add_reg(&rctx->vs_const_buffer, R600_GROUP_ALU_CONST,
+ R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
+ ALIGN_DIVUP(buffer->width0 >> 4, 16),
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(&rctx->vs_const_buffer, R600_GROUP_ALU_CONST,
+ R_028980_ALU_CONST_CACHE_VS_0,
+ 0, 0xFFFFFFFF, rbuffer->bo);
+ r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_const_buffer);
+ break;
+ case PIPE_SHADER_FRAGMENT:
+ rctx->ps_const_buffer.nregs = 0;
+ r600_pipe_state_add_reg(&rctx->ps_const_buffer, R600_GROUP_ALU_CONST,
+ R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
+ ALIGN_DIVUP(buffer->width0 >> 4, 16),
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(&rctx->ps_const_buffer, R600_GROUP_ALU_CONST,
+ R_028940_ALU_CONST_CACHE_PS_0,
+ 0, 0xFFFFFFFF, rbuffer->bo);
+ r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_const_buffer);
+ break;
+ default:
+ R600_ERR("unsupported %d\n", shader);
+ return;
+ }
+}
+
+static void *evergreen_create_shader_state(struct pipe_context *ctx,
+ const struct pipe_shader_state *state)
+{
+ struct r600_pipe_shader *shader = CALLOC_STRUCT(r600_pipe_shader);
+ int r;
+
+ r = r600_pipe_shader_create2(ctx, shader, state->tokens);
+ if (r) {
+ return NULL;
+ }
+ return shader;
+}
+
+static void evergreen_bind_ps_shader(struct pipe_context *ctx, void *state)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+
+ /* TODO delete old shader */
+ rctx->ps_shader = (struct r600_pipe_shader *)state;
+}
+
+static void evergreen_bind_vs_shader(struct pipe_context *ctx, void *state)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+
+ /* TODO delete old shader */
+ rctx->vs_shader = (struct r600_pipe_shader *)state;
+}
+
+static void evergreen_delete_ps_shader(struct pipe_context *ctx, void *state)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
+
+ if (rctx->ps_shader == shader) {
+ rctx->ps_shader = NULL;
+ }
+ /* TODO proper delete */
+ free(shader);
+}
+
+static void evergreen_delete_vs_shader(struct pipe_context *ctx, void *state)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
+
+ if (rctx->vs_shader == shader) {
+ rctx->vs_shader = NULL;
+ }
+ /* TODO proper delete */
+ free(shader);
+}
+
+void evergreen_init_state_functions2(struct r600_pipe_context *rctx)
+{
+ rctx->context.create_blend_state = evergreen_create_blend_state;
+ rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
+ rctx->context.create_fs_state = evergreen_create_shader_state;
+ rctx->context.create_rasterizer_state = evergreen_create_rs_state;
+ rctx->context.create_sampler_state = evergreen_create_sampler_state;
+ rctx->context.create_sampler_view = evergreen_create_sampler_view;
+ rctx->context.create_vertex_elements_state = evergreen_create_vertex_elements;
+ rctx->context.create_vs_state = evergreen_create_shader_state;
+ rctx->context.bind_blend_state = evergreen_bind_blend_state;
+ rctx->context.bind_depth_stencil_alpha_state = evergreen_bind_state;
+ rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
+ rctx->context.bind_fs_state = evergreen_bind_ps_shader;
+ rctx->context.bind_rasterizer_state = evergreen_bind_rs_state;
+ rctx->context.bind_vertex_elements_state = evergreen_bind_vertex_elements;
+ rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
+ rctx->context.bind_vs_state = evergreen_bind_vs_shader;
+ rctx->context.delete_blend_state = evergreen_delete_state;
+ rctx->context.delete_depth_stencil_alpha_state = evergreen_delete_state;
+ rctx->context.delete_fs_state = evergreen_delete_ps_shader;
+ rctx->context.delete_rasterizer_state = evergreen_delete_rs_state;
+ rctx->context.delete_sampler_state = evergreen_delete_state;
+ rctx->context.delete_vertex_elements_state = evergreen_delete_vertex_element;
+ rctx->context.delete_vs_state = evergreen_delete_vs_shader;
+ rctx->context.set_blend_color = evergreen_set_blend_color;
+ rctx->context.set_clip_state = evergreen_set_clip_state;
+ rctx->context.set_constant_buffer = evergreen_set_constant_buffer;
+ rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
+ rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
+ rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
+ rctx->context.set_sample_mask = evergreen_set_sample_mask;
+ rctx->context.set_scissor_state = evergreen_set_scissor_state;
+ rctx->context.set_stencil_ref = evergreen_set_stencil_ref;
+ rctx->context.set_vertex_buffers = evergreen_set_vertex_buffers;
+ rctx->context.set_index_buffer = evergreen_set_index_buffer;
+ rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
+ rctx->context.set_viewport_state = evergreen_set_viewport_state;
+ rctx->context.sampler_view_destroy = evergreen_sampler_view_destroy;
+}
+
+void evergreen_init_config2(struct r600_pipe_context *rctx)
+{
+ struct r600_pipe_state *rstate = &rctx->config;
+ int ps_prio;
+ int vs_prio;
+ int gs_prio;
+ int es_prio;
+ int hs_prio, cs_prio, ls_prio;
+ int num_ps_gprs;
+ int num_vs_gprs;
+ int num_gs_gprs;
+ int num_es_gprs;
+ int num_hs_gprs;
+ int num_ls_gprs;
+ int num_temp_gprs;
+ int num_ps_threads;
+ int num_vs_threads;
+ int num_gs_threads;
+ int num_es_threads;
+ int num_hs_threads;
+ int num_ls_threads;
+ int num_ps_stack_entries;
+ int num_vs_stack_entries;
+ int num_gs_stack_entries;
+ int num_es_stack_entries;
+ int num_hs_stack_entries;
+ int num_ls_stack_entries;
+ enum radeon_family family;
+ unsigned tmp;
+
+ family = r600_get_family(rctx->radeon);
+ ps_prio = 0;
+ vs_prio = 1;
+ gs_prio = 2;
+ es_prio = 3;
+ hs_prio = 0;
+ ls_prio = 0;
+ cs_prio = 0;
+
+ switch (family) {
+ case CHIP_CEDAR:
+ default:
+ num_ps_gprs = 93;
+ num_vs_gprs = 46;
+ num_temp_gprs = 4;
+ num_gs_gprs = 31;
+ num_es_gprs = 31;
+ num_hs_gprs = 23;
+ num_ls_gprs = 23;
+ num_ps_threads = 96;
+ num_vs_threads = 16;
+ num_gs_threads = 16;
+ num_es_threads = 16;
+ num_hs_threads = 16;
+ num_ls_threads = 16;
+ num_ps_stack_entries = 42;
+ num_vs_stack_entries = 42;
+ num_gs_stack_entries = 42;
+ num_es_stack_entries = 42;
+ num_hs_stack_entries = 42;
+ num_ls_stack_entries = 42;
+ break;
+ case CHIP_REDWOOD:
+ num_ps_gprs = 93;
+ num_vs_gprs = 46;
+ num_temp_gprs = 4;
+ num_gs_gprs = 31;
+ num_es_gprs = 31;
+ num_hs_gprs = 23;
+ num_ls_gprs = 23;
+ num_ps_threads = 128;
+ num_vs_threads = 20;
+ num_gs_threads = 20;
+ num_es_threads = 20;
+ num_hs_threads = 20;
+ num_ls_threads = 20;
+ num_ps_stack_entries = 42;
+ num_vs_stack_entries = 42;
+ num_gs_stack_entries = 42;
+ num_es_stack_entries = 42;
+ num_hs_stack_entries = 42;
+ num_ls_stack_entries = 42;
+ break;
+ case CHIP_JUNIPER:
+ num_ps_gprs = 93;
+ num_vs_gprs = 46;
+ num_temp_gprs = 4;
+ num_gs_gprs = 31;
+ num_es_gprs = 31;
+ num_hs_gprs = 23;
+ num_ls_gprs = 23;
+ num_ps_threads = 128;
+ num_vs_threads = 20;
+ num_gs_threads = 20;
+ num_es_threads = 20;
+ num_hs_threads = 20;
+ num_ls_threads = 20;
+ num_ps_stack_entries = 85;
+ num_vs_stack_entries = 85;
+ num_gs_stack_entries = 85;
+ num_es_stack_entries = 85;
+ num_hs_stack_entries = 85;
+ num_ls_stack_entries = 85;
+ break;
+ case CHIP_CYPRESS:
+ case CHIP_HEMLOCK:
+ num_ps_gprs = 93;
+ num_vs_gprs = 46;
+ num_temp_gprs = 4;
+ num_gs_gprs = 31;
+ num_es_gprs = 31;
+ num_hs_gprs = 23;
+ num_ls_gprs = 23;
+ num_ps_threads = 128;
+ num_vs_threads = 20;
+ num_gs_threads = 20;
+ num_es_threads = 20;
+ num_hs_threads = 20;
+ num_ls_threads = 20;
+ num_ps_stack_entries = 85;
+ num_vs_stack_entries = 85;
+ num_gs_stack_entries = 85;
+ num_es_stack_entries = 85;
+ num_hs_stack_entries = 85;
+ num_ls_stack_entries = 85;
+ break;
+ }
+
+ tmp = 0x00000000;
+ switch (family) {
+ case CHIP_CEDAR:
+ break;
+ default:
+ tmp |= S_008C00_VC_ENABLE(1);
+ break;
+ }
+ tmp |= S_008C00_EXPORT_SRC_C(1);
+ tmp |= S_008C00_CS_PRIO(cs_prio);
+ tmp |= S_008C00_LS_PRIO(ls_prio);
+ tmp |= S_008C00_HS_PRIO(hs_prio);
+ tmp |= S_008C00_PS_PRIO(ps_prio);
+ tmp |= S_008C00_VS_PRIO(vs_prio);
+ tmp |= S_008C00_GS_PRIO(gs_prio);
+ tmp |= S_008C00_ES_PRIO(es_prio);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
+
+ tmp = 0;
+ tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
+ tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
+ tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
+
+ tmp = 0;
+ tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
+ tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
+
+ tmp = 0;
+ tmp |= S_008C0C_NUM_HS_GPRS(num_hs_gprs);
+ tmp |= S_008C0C_NUM_LS_GPRS(num_ls_gprs);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C0C_SQ_GPR_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
+
+ tmp = 0;
+ tmp |= S_008C18_NUM_PS_THREADS(num_ps_threads);
+ tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
+ tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
+ tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
+
+ tmp = 0;
+ tmp |= S_008C1C_NUM_HS_THREADS(num_hs_threads);
+ tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
+
+ tmp = 0;
+ tmp |= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
+ tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C20_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
+
+ tmp = 0;
+ tmp |= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
+ tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C24_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
+
+ tmp = 0;
+ tmp |= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
+ tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C28_SQ_STACK_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
+
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_009100_SPI_CONFIG_CNTL, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4), 0xFFFFFFFF, NULL);
+
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028350_SX_MISC, 0x0, 0xFFFFFFFF, NULL);
+
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028A48_PA_SC_MODE_CNTL_0, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL);
+
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028900_SQ_ESGS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028904_SQ_GSVS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
+
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_02891C_SQ_GS_VERT_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0x0, 0xFFFFFFFF, NULL);
+
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028AB4_VGT_REUSE_OFF, 0x00000001, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL);
+ r600_context_pipe_state_set(&rctx->ctx, rstate);
+}
+
+int r600_conv_pipe_prim(unsigned pprim, unsigned *prim);
+void evergreen_draw(struct pipe_context *ctx, const struct pipe_draw_info *info)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_pipe_state *rstate;
+ struct r600_resource *rbuffer;
+ unsigned i, j, offset, format, prim;
+ u32 vgt_dma_index_type, vgt_draw_initiator, mask;
+ struct pipe_vertex_buffer *vertex_buffer;
+ struct r600_draw rdraw;
+ struct r600_pipe_state vgt;
+ struct r600_drawl draw;
+
+ assert(info->index_bias == 0);
+
+ draw.mode = info->mode;
+ draw.start = info->start;
+ draw.count = info->count;
+ if (info->indexed && rctx->index_buffer.buffer) {
+ draw.index_size = rctx->index_buffer.index_size;
+ draw.index_buffer = rctx->index_buffer.buffer;
+ assert(rctx->index_buffer.offset %
+ rctx->index_buffer.index_size == 0);
+ draw.start += rctx->index_buffer.offset /
+ rctx->index_buffer.index_size;
+ } else {
+ draw.index_size = 0;
+ draw.index_buffer = NULL;
+ }
+ switch (draw.index_size) {
+ case 2:
+ vgt_draw_initiator = 0;
+ vgt_dma_index_type = 0;
+ break;
+ case 4:
+ vgt_draw_initiator = 0;
+ vgt_dma_index_type = 1;
+ break;
+ case 0:
+ vgt_draw_initiator = 2;
+ vgt_dma_index_type = 0;
+ break;
+ default:
+ R600_ERR("unsupported index size %d\n", draw.index_size);
+ return;
+ }
+ if (r600_conv_pipe_prim(draw.mode, &prim))
+ return;
+
+ /* rebuild vertex shader if input format changed */
+ if (r600_pipe_shader_update2(&rctx->context, rctx->vs_shader))
+ return;
+ if (r600_pipe_shader_update2(&rctx->context, rctx->ps_shader))
+ return;
+
+ for (i = 0 ; i < rctx->vertex_elements->count; i++) {
+ rstate = &rctx->vs_resource[i];
+ j = rctx->vertex_elements->elements[i].vertex_buffer_index;
+ vertex_buffer = &rctx->vertex_buffer[j];
+ rbuffer = (struct r600_resource*)vertex_buffer->buffer;
+ offset = rctx->vertex_elements->elements[i].src_offset + vertex_buffer->buffer_offset;
+ format = r600_translate_colorformat(rctx->vertex_elements->elements[i].src_format);
+ rstate->id = R600_PIPE_STATE_RESOURCE;
+ rstate->nregs = 0;
+
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_RESOURCE, R_030000_RESOURCE0_WORD0, offset, 0xFFFFFFFF, rbuffer->bo);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_RESOURCE, R_030004_RESOURCE0_WORD1, rbuffer->size - offset - 1, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_RESOURCE,
+ R_030008_RESOURCE0_WORD2,
+ S_030008_STRIDE(vertex_buffer->stride) |
+ S_030008_DATA_FORMAT(format),
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_RESOURCE,
+ R_03000C_RESOURCE0_WORD3,
+ S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
+ S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
+ S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
+ S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W),
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_RESOURCE, R_030010_RESOURCE0_WORD4, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_RESOURCE, R_030014_RESOURCE0_WORD5, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_RESOURCE, R_030018_RESOURCE0_WORD6, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, EVERGREEN_GROUP_RESOURCE, R_03001C_RESOURCE0_WORD7, 0xC0000000, 0xFFFFFFFF, NULL);
+ evergreen_vs_resource_set(&rctx->ctx, rstate, i);
+ }
+
+ mask = 0;
+ for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
+ mask |= (0xF << (i * 4));
+ }
+
+ vgt.id = R600_PIPE_STATE_VGT;
+ vgt.nregs = 0;
+ r600_pipe_state_add_reg(&vgt, EVERGREEN_GROUP_CONFIG, R_008958_VGT_PRIMITIVE_TYPE, prim, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(&vgt, EVERGREEN_GROUP_CONTEXT, R_028408_VGT_INDX_OFFSET, draw.start, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(&vgt, EVERGREEN_GROUP_CONTEXT, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL);
+ r600_context_pipe_state_set(&rctx->ctx, &vgt);
+
+ rdraw.vgt_num_indices = draw.count;
+ rdraw.vgt_num_instances = 1;
+ rdraw.vgt_index_type = vgt_dma_index_type;
+ rdraw.vgt_draw_initiator = vgt_draw_initiator;
+ rdraw.indices = NULL;
+ if (draw.index_buffer) {
+ rbuffer = (struct r600_resource*)draw.index_buffer;
+ rdraw.indices = rbuffer->bo;
+ rdraw.indices_bo_offset = 0;
+ }
+ evergreen_context_draw(&rctx->ctx, &rdraw);
+}
+
+void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_pipe_state *rstate = &shader->rstate;
+ struct r600_shader *rshader = &shader->shader;
+ unsigned i, tmp, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z;
+ boolean have_pos = FALSE, have_face = FALSE;
+
+ /* clear previous register */
+ rstate->nregs = 0;
+
+ for (i = 0; i < rshader->ninput; i++) {
+ tmp = S_028644_SEMANTIC(i);
+ tmp |= S_028644_SEL_CENTROID(1);
+ if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
+ have_pos = TRUE;
+ if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
+ rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
+ rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
+ tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
+ }
+ if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
+ have_face = TRUE;
+ if (rctx->sprite_coord_enable & (1 << i)) {
+ tmp |= S_028644_PT_SPRITE_TEX(1);
+ }
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp, 0xFFFFFFFF, NULL);
+ }
+
+ exports_ps = 0;
+ num_cout = 0;
+ for (i = 0; i < rshader->noutput; i++) {
+ if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
+ exports_ps |= 1;
+ else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
+ num_cout++;
+ }
+ }
+ exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
+ if (!exports_ps) {
+ /* always at least export 1 component per pixel */
+ exports_ps = 2;
+ }
+
+ spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
+ S_0286CC_PERSP_GRADIENT_ENA(1);
+ spi_input_z = 0;
+ if (have_pos) {
+ spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1);
+ spi_input_z |= 1;
+ }
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286CC_SPI_PS_IN_CONTROL_0,
+ spi_ps_in_control_0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286D0_SPI_PS_IN_CONTROL_1,
+ S_0286D0_FRONT_FACE_ENA(have_face), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028840_SQ_PGM_START_PS,
+ 0x00000000, 0xFFFFFFFF, shader->bo);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028844_SQ_PGM_RESOURCES_PS,
+ S_028844_NUM_GPRS(rshader->bc.ngpr) |
+ S_028844_PRIME_CACHE_ON_DRAW(1) |
+ S_028844_STACK_SIZE(rshader->bc.nstack),
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_02884C_SQ_PGM_EXPORTS_PS,
+ exports_ps, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_0286E0_SPI_BARYC_CNTL,
+ S_0286E0_PERSP_CENTROID_ENA(1) |
+ S_0286E0_LINEAR_CENTROID_ENA(1),
+ 0xFFFFFFFF, NULL);
+}
+
+void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
+{
+ struct r600_pipe_state *rstate = &shader->rstate;
+ struct r600_shader *rshader = &shader->shader;
+ unsigned spi_vs_out_id[10];
+ unsigned i, tmp;
+
+ /* clear previous register */
+ rstate->nregs = 0;
+
+ /* so far never got proper semantic id from tgsi */
+ for (i = 0; i < 10; i++) {
+ spi_vs_out_id[i] = 0;
+ }
+ for (i = 0; i < 32; i++) {
+ tmp = i << ((i & 3) * 8);
+ spi_vs_out_id[i / 4] |= tmp;
+ }
+ for (i = 0; i < 10; i++) {
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_02861C_SPI_VS_OUT_ID_0 + i * 4,
+ spi_vs_out_id[i], 0xFFFFFFFF, NULL);
+ }
+
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_0286C4_SPI_VS_OUT_CONFIG,
+ S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028860_SQ_PGM_RESOURCES_VS,
+ S_028860_NUM_GPRS(rshader->bc.ngpr) |
+ S_028860_STACK_SIZE(rshader->bc.nstack),
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_0288A8_SQ_PGM_RESOURCES_FS,
+ 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_02885C_SQ_PGM_START_VS,
+ 0x00000000, 0xFFFFFFFF, shader->bo);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_0288A4_SQ_PGM_START_FS,
+ 0x00000000, 0xFFFFFFFF, shader->bo);
+}
#ifndef EVERGREEND_H
#define EVERGREEND_H
+/* evergreen values */
+#define EVERGREEN_CONFIG_REG_OFFSET 0X00008000
+#define EVERGREEN_CONFIG_REG_END 0X0000AC00
+#define EVERGREEN_CONTEXT_REG_OFFSET 0X00028000
+#define EVERGREEN_CONTEXT_REG_END 0X00029000
+#define EVERGREEN_RESOURCE_OFFSET 0x00030000
+#define EVERGREEN_RESOURCE_END 0x00030400
+#define EVERGREEN_LOOP_CONST_OFFSET 0x0003A200
+#define EVERGREEN_LOOP_CONST_END 0x0003A26C
+#define EVERGREEN_BOOL_CONST_OFFSET 0x0003A500
+#define EVERGREEN_BOOL_CONST_END 0x0003A506
+#define EVERGREEN_SAMPLER_OFFSET 0X0003C000
+#define EVERGREEN_SAMPLER_END 0X0003CFF0
+
+#define EVENT_TYPE_ZPASS_DONE 0x15
+#define EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT 0x16
+
#define R600_TEXEL_PITCH_ALIGNMENT_MASK 0x7
#define PKT3_NOP 0x10
#define SQ_TEX_INST_SAMPLE 0x10
#define SQ_TEX_INST_SAMPLE_L 0x11
#define SQ_TEX_INST_SAMPLE_C 0x18
+
+#define R_008A14_PA_CL_ENHANCE 0x00008A14
+#define R_008C0C_SQ_THREAD_RESOURCE_MGMT 0x00008C0C
+#define R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x00008D8C
+#define R_028000_DB_RENDER_CONTROL 0x00028000
+#define R_028008_DB_DEPTH_VIEW 0x00028008
+#define R_02800C_DB_RENDER_OVERRIDE 0x0002800C
+#define R_028010_DB_RENDER_OVERRIDE2 0x00028010
+#define R_028014_DB_HTILE_DATA_BASE 0x00028014
+#define R_028028_DB_STENCIL_CLEAR 0x00028028
+#define R_02802C_DB_DEPTH_CLEAR 0x0002802C
+#define R_028048_DB_Z_READ_BASE 0x00028048
+#define R_02804C_DB_STENCIL_READ_BASE 0x0002804C
+#define R_028050_DB_Z_WRITE_BASE 0x00028050
+#define R_028054_DB_STENCIL_WRITE_BASE 0x00028054
+#define R_028140_ALU_CONST_BUFFER_SIZE_PS_0 0x00028140
+#define R_028180_ALU_CONST_BUFFER_SIZE_VS_0 0x00028180
+#define R_028200_PA_SC_WINDOW_OFFSET 0x00028200
+#define R_02820C_PA_SC_CLIPRECT_RULE 0x0002820C
+#define R_028210_PA_SC_CLIPRECT_0_TL 0x00028210
+#define R_028214_PA_SC_CLIPRECT_0_BR 0x00028214
+#define R_028218_PA_SC_CLIPRECT_1_TL 0x00028218
+#define R_02821C_PA_SC_CLIPRECT_1_BR 0x0002821C
+#define R_028220_PA_SC_CLIPRECT_2_TL 0x00028220
+#define R_028224_PA_SC_CLIPRECT_2_BR 0x00028224
+#define R_028228_PA_SC_CLIPRECT_3_TL 0x00028228
+#define R_02822C_PA_SC_CLIPRECT_3_BR 0x0002822C
+#define R_028230_PA_SC_EDGERULE 0x00028230
+#define R_028234_PA_SU_HARDWARE_SCREEN_OFFSET 0x00028234
+#define R_028238_CB_TARGET_MASK 0x00028238
+#define R_02823C_CB_SHADER_MASK 0x0002823C
+#define R_028250_PA_SC_VPORT_SCISSOR_0_TL 0x00028250
+#define R_028254_PA_SC_VPORT_SCISSOR_0_BR 0x00028254
+#define R_028350_SX_MISC 0x00028350
+#define R_028380_SQ_VTX_SEMANTIC_0 0x00028380
+#define R_028384_SQ_VTX_SEMANTIC_1 0x00028384
+#define R_028388_SQ_VTX_SEMANTIC_2 0x00028388
+#define R_02838C_SQ_VTX_SEMANTIC_3 0x0002838C
+#define R_028390_SQ_VTX_SEMANTIC_4 0x00028390
+#define R_028394_SQ_VTX_SEMANTIC_5 0x00028394
+#define R_028398_SQ_VTX_SEMANTIC_6 0x00028398
+#define R_02839C_SQ_VTX_SEMANTIC_7 0x0002839C
+#define R_0283A0_SQ_VTX_SEMANTIC_8 0x000283A0
+#define R_0283A4_SQ_VTX_SEMANTIC_9 0x000283A4
+#define R_0283A8_SQ_VTX_SEMANTIC_10 0x000283A8
+#define R_0283AC_SQ_VTX_SEMANTIC_11 0x000283AC
+#define R_0283B0_SQ_VTX_SEMANTIC_12 0x000283B0
+#define R_0283B4_SQ_VTX_SEMANTIC_13 0x000283B4
+#define R_0283B8_SQ_VTX_SEMANTIC_14 0x000283B8
+#define R_0283BC_SQ_VTX_SEMANTIC_15 0x000283BC
+#define R_0283C0_SQ_VTX_SEMANTIC_16 0x000283C0
+#define R_0283C4_SQ_VTX_SEMANTIC_17 0x000283C4
+#define R_0283C8_SQ_VTX_SEMANTIC_18 0x000283C8
+#define R_0283CC_SQ_VTX_SEMANTIC_19 0x000283CC
+#define R_0283D0_SQ_VTX_SEMANTIC_20 0x000283D0
+#define R_0283D4_SQ_VTX_SEMANTIC_21 0x000283D4
+#define R_0283D8_SQ_VTX_SEMANTIC_22 0x000283D8
+#define R_0283DC_SQ_VTX_SEMANTIC_23 0x000283DC
+#define R_0283E0_SQ_VTX_SEMANTIC_24 0x000283E0
+#define R_0283E4_SQ_VTX_SEMANTIC_25 0x000283E4
+#define R_0283E8_SQ_VTX_SEMANTIC_26 0x000283E8
+#define R_0283EC_SQ_VTX_SEMANTIC_27 0x000283EC
+#define R_0283F0_SQ_VTX_SEMANTIC_28 0x000283F0
+#define R_0283F4_SQ_VTX_SEMANTIC_29 0x000283F4
+#define R_0283F8_SQ_VTX_SEMANTIC_30 0x000283F8
+#define R_0283FC_SQ_VTX_SEMANTIC_31 0x000283FC
+#define R_0282D0_PA_SC_VPORT_ZMIN_0 0x000282D0
+#define R_0282D4_PA_SC_VPORT_ZMAX_0 0x000282D4
+#define R_028400_VGT_MAX_VTX_INDX 0x00028400
+#define R_028404_VGT_MIN_VTX_INDX 0x00028404
+#define R_028408_VGT_INDX_OFFSET 0x00028408
+#define R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX 0x0002840C
+#define R_028414_CB_BLEND_RED 0x00028414
+#define R_028418_CB_BLEND_GREEN 0x00028418
+#define R_02841C_CB_BLEND_BLUE 0x0002841C
+#define R_028420_CB_BLEND_ALPHA 0x00028420
+#define R_028438_SX_ALPHA_REF 0x00028438
+#define R_02843C_PA_CL_VPORT_XSCALE_0 0x0002843C
+#define R_028440_PA_CL_VPORT_XOFFSET_0 0x00028440
+#define R_028444_PA_CL_VPORT_YSCALE_0 0x00028444
+#define R_028448_PA_CL_VPORT_YOFFSET_0 0x00028448
+#define R_02844C_PA_CL_VPORT_ZSCALE_0 0x0002844C
+#define R_028450_PA_CL_VPORT_ZOFFSET_0 0x00028450
+#define R_0285BC_PA_CL_UCP0_X 0x000285BC
+#define R_0285C0_PA_CL_UCP0_Y 0x000285C0
+#define R_0285C4_PA_CL_UCP0_Z 0x000285C4
+#define R_0285C8_PA_CL_UCP0_W 0x000285C8
+#define R_0285CC_PA_CL_UCP1_X 0x000285CC
+#define R_0285D0_PA_CL_UCP1_Y 0x000285D0
+#define R_0285D4_PA_CL_UCP1_Z 0x000285D4
+#define R_0285D8_PA_CL_UCP1_W 0x000285D8
+#define R_0285DC_PA_CL_UCP2_X 0x000285DC
+#define R_0285E0_PA_CL_UCP2_Y 0x000285E0
+#define R_0285E4_PA_CL_UCP2_Z 0x000285E4
+#define R_0285E8_PA_CL_UCP2_W 0x000285E8
+#define R_0285EC_PA_CL_UCP3_X 0x000285EC
+#define R_0285F0_PA_CL_UCP3_Y 0x000285F0
+#define R_0285F4_PA_CL_UCP3_Z 0x000285F4
+#define R_0285F8_PA_CL_UCP3_W 0x000285F8
+#define R_0285FC_PA_CL_UCP4_X 0x000285FC
+#define R_028600_PA_CL_UCP4_Y 0x00028600
+#define R_028604_PA_CL_UCP4_Z 0x00028604
+#define R_028608_PA_CL_UCP4_W 0x00028608
+#define R_02860C_PA_CL_UCP5_X 0x0002860C
+#define R_028610_PA_CL_UCP5_Y 0x00028610
+#define R_028614_PA_CL_UCP5_Z 0x00028614
+#define R_028618_PA_CL_UCP5_W 0x00028618
+#define R_02861C_SPI_VS_OUT_ID_0 0x0002861C
+#define R_028620_SPI_VS_OUT_ID_1 0x00028620
+#define R_028624_SPI_VS_OUT_ID_2 0x00028624
+#define R_028628_SPI_VS_OUT_ID_3 0x00028628
+#define R_02862C_SPI_VS_OUT_ID_4 0x0002862C
+#define R_028630_SPI_VS_OUT_ID_5 0x00028630
+#define R_028634_SPI_VS_OUT_ID_6 0x00028634
+#define R_028638_SPI_VS_OUT_ID_7 0x00028638
+#define R_02863C_SPI_VS_OUT_ID_8 0x0002863C
+#define R_028640_SPI_VS_OUT_ID_9 0x00028640
+#define R_028648_SPI_PS_INPUT_CNTL_1 0x00028648
+#define R_02864C_SPI_PS_INPUT_CNTL_2 0x0002864C
+#define R_028650_SPI_PS_INPUT_CNTL_3 0x00028650
+#define R_028654_SPI_PS_INPUT_CNTL_4 0x00028654
+#define R_028658_SPI_PS_INPUT_CNTL_5 0x00028658
+#define R_02865C_SPI_PS_INPUT_CNTL_6 0x0002865C
+#define R_028660_SPI_PS_INPUT_CNTL_7 0x00028660
+#define R_028664_SPI_PS_INPUT_CNTL_8 0x00028664
+#define R_028668_SPI_PS_INPUT_CNTL_9 0x00028668
+#define R_02866C_SPI_PS_INPUT_CNTL_10 0x0002866C
+#define R_028670_SPI_PS_INPUT_CNTL_11 0x00028670
+#define R_028674_SPI_PS_INPUT_CNTL_12 0x00028674
+#define R_028678_SPI_PS_INPUT_CNTL_13 0x00028678
+#define R_02867C_SPI_PS_INPUT_CNTL_14 0x0002867C
+#define R_028680_SPI_PS_INPUT_CNTL_15 0x00028680
+#define R_028684_SPI_PS_INPUT_CNTL_16 0x00028684
+#define R_028688_SPI_PS_INPUT_CNTL_17 0x00028688
+#define R_02868C_SPI_PS_INPUT_CNTL_18 0x0002868C
+#define R_028690_SPI_PS_INPUT_CNTL_19 0x00028690
+#define R_028694_SPI_PS_INPUT_CNTL_20 0x00028694
+#define R_028698_SPI_PS_INPUT_CNTL_21 0x00028698
+#define R_02869C_SPI_PS_INPUT_CNTL_22 0x0002869C
+#define R_0286A0_SPI_PS_INPUT_CNTL_23 0x000286A0
+#define R_0286A4_SPI_PS_INPUT_CNTL_24 0x000286A4
+#define R_0286A8_SPI_PS_INPUT_CNTL_25 0x000286A8
+#define R_0286AC_SPI_PS_INPUT_CNTL_26 0x000286AC
+#define R_0286B0_SPI_PS_INPUT_CNTL_27 0x000286B0
+#define R_0286B4_SPI_PS_INPUT_CNTL_28 0x000286B4
+#define R_0286B8_SPI_PS_INPUT_CNTL_29 0x000286B8
+#define R_0286BC_SPI_PS_INPUT_CNTL_30 0x000286BC
+#define R_0286C0_SPI_PS_INPUT_CNTL_31 0x000286C0
+#define R_0286C8_SPI_THREAD_GROUPING 0x000286C8
+#define R_0286D8_SPI_INPUT_Z 0x000286D8
+#define R_0286DC_SPI_FOG_CNTL 0x000286DC
+#define R_0286E4_SPI_PS_IN_CONTROL_2 0x000286E4
+#define R_0286E8_SPI_COMPUTE_INPUT_CNTL 0x000286E8
+#define R_028780_CB_BLEND0_CONTROL 0x00028780
+#define R_028784_CB_BLEND1_CONTROL 0x00028784
+#define R_028788_CB_BLEND2_CONTROL 0x00028788
+#define R_02878C_CB_BLEND3_CONTROL 0x0002878C
+#define R_028790_CB_BLEND4_CONTROL 0x00028790
+#define R_028794_CB_BLEND5_CONTROL 0x00028794
+#define R_028798_CB_BLEND6_CONTROL 0x00028798
+#define R_02879C_CB_BLEND7_CONTROL 0x0002879C
+#define R_028818_PA_CL_VTE_CNTL 0x00028818
+#define R_028820_PA_CL_NANINF_CNTL 0x00028820
+#define R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1 0x00028838
+#define R_028840_SQ_PGM_START_PS 0x00028840
+#define R_02884C_SQ_PGM_EXPORTS_PS 0x0002884C
+#define S_02884C_EXPORT_COLORS(x) (((x) & 0xF) << 1)
+#define G_02884C_EXPORT_COLORS(x) (((x) >> 1) & 0xF)
+#define C_02884C_EXPORT_COLORS 0xFFFFFFE1
+#define S_02884C_EXPORT_Z(x) (((x) & 0x1) << 0)
+#define G_02884C_EXPORT_Z(x) (((x) >> 0) & 0x1)
+#define C_02884C_EXPORT_Z 0xFFFFFFFE
+#define R_02885C_SQ_PGM_START_VS 0x0002885C
+#define R_0288A4_SQ_PGM_START_FS 0x000288A4
+#define R_0288A8_SQ_PGM_RESOURCES_FS 0x000288A8
+#define R_0288EC_SQ_LDS_ALLOC_PS 0x000288EC
+#define R_028900_SQ_ESGS_RING_ITEMSIZE 0x00028900
+#define R_028904_SQ_GSVS_RING_ITEMSIZE 0x00028904
+#define R_028908_SQ_ESTMP_RING_ITEMSIZE 0x00028908
+#define R_02890C_SQ_GSTMP_RING_ITEMSIZE 0x0002890C
+#define R_028910_SQ_VSTMP_RING_ITEMSIZE 0x00028910
+#define R_028914_SQ_PSTMP_RING_ITEMSIZE 0x00028914
+#define R_02891C_SQ_GS_VERT_ITEMSIZE 0x0002891C
+#define R_028920_SQ_GS_VERT_ITEMSIZE_1 0x00028920
+#define R_028924_SQ_GS_VERT_ITEMSIZE_2 0x00028924
+#define R_028928_SQ_GS_VERT_ITEMSIZE_3 0x00028928
+#define R_028940_ALU_CONST_CACHE_PS_0 0x00028940
+#define R_028980_ALU_CONST_CACHE_VS_0 0x00028980
+#define R_028A04_PA_SU_POINT_MINMAX 0x00028A04
+#define R_028A08_PA_SU_LINE_CNTL 0x00028A08
+#define R_028A10_VGT_OUTPUT_PATH_CNTL 0x00028A10
+#define R_028A14_VGT_HOS_CNTL 0x00028A14
+#define R_028A18_VGT_HOS_MAX_TESS_LEVEL 0x00028A18
+#define R_028A1C_VGT_HOS_MIN_TESS_LEVEL 0x00028A1C
+#define R_028A20_VGT_HOS_REUSE_DEPTH 0x00028A20
+#define R_028A24_VGT_GROUP_PRIM_TYPE 0x00028A24
+#define R_028A28_VGT_GROUP_FIRST_DECR 0x00028A28
+#define R_028A2C_VGT_GROUP_DECR 0x00028A2C
+#define R_028A30_VGT_GROUP_VECT_0_CNTL 0x00028A30
+#define R_028A34_VGT_GROUP_VECT_1_CNTL 0x00028A34
+#define R_028A38_VGT_GROUP_VECT_0_FMT_CNTL 0x00028A38
+#define R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL 0x00028A3C
+#define R_028A48_PA_SC_MODE_CNTL_0 0x00028A48
+#define R_028A4C_PA_SC_MODE_CNTL_1 0x00028A4C
+#define R_028AB4_VGT_REUSE_OFF 0x00028AB4
+#define R_028AB8_VGT_VTX_CNT_EN 0x00028AB8
+#define R_028ABC_DB_HTILE_SURFACE 0x00028ABC
+#define R_028AC0_DB_SRESULTS_COMPARE_STATE0 0x00028AC0
+#define R_028AC4_DB_SRESULTS_COMPARE_STATE1 0x00028AC4
+#define R_028AC8_DB_PRELOAD_CONTROL 0x00028AC8
+#define R_028B54_VGT_SHADER_STAGES_EN 0x00028B54
+#define R_028B70_DB_ALPHA_TO_MASK 0x00028B70
+#define R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL 0x00028B78
+#define R_028B7C_PA_SU_POLY_OFFSET_CLAMP 0x00028B7C
+#define R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE 0x00028B80
+#define R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET 0x00028B84
+#define R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE 0x00028B88
+#define R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET 0x00028B8C
+#define R_028B94_VGT_STRMOUT_CONFIG 0x00028B94
+#define R_028B98_VGT_STRMOUT_BUFFER_CONFIG 0x00028B98
+#define R_028C00_PA_SC_LINE_CNTL 0x00028C00
+#define R_028C04_PA_SC_AA_CONFIG 0x00028C04
+#define R_028C08_PA_SU_VTX_CNTL 0x00028C08
+#define R_028C0C_PA_CL_GB_VERT_CLIP_ADJ 0x00028C0C
+#define R_028C10_PA_CL_GB_VERT_DISC_ADJ 0x00028C10
+#define R_028C14_PA_CL_GB_HORZ_CLIP_ADJ 0x00028C14
+#define R_028C18_PA_CL_GB_HORZ_DISC_ADJ 0x00028C18
+#define R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX 0x00028C1C
+#define R_028C3C_PA_SC_AA_MASK 0x00028C3C
+#define R_028C60_CB_COLOR0_BASE 0x00028C60
+#define R_028C6C_CB_COLOR0_VIEW 0x00028C6C
+#define R_028C9C_CB_COLOR1_BASE 0x00028C9C
+#define R_028CA0_CB_COLOR1_PITCH 0x00028CA0
+#define R_028CA4_CB_COLOR1_SLICE 0x00028CA4
+#define R_028CA8_CB_COLOR1_VIEW 0x00028CA8
+#define R_028CAC_CB_COLOR1_INFO 0x00028CAC
+#define R_028CB0_CB_COLOR1_ATTRIB 0x00028CB0
+#define R_028CB8_CB_COLOR1_DIM 0x00028CB8
+#define R_028CD8_CB_COLOR2_BASE 0x00028CD8
+#define R_028CDC_CB_COLOR2_PITCH 0x00028CDC
+#define R_028CE0_CB_COLOR2_SLICE 0x00028CE0
+#define R_028CE4_CB_COLOR2_VIEW 0x00028CE4
+#define R_028CE8_CB_COLOR2_INFO 0x00028CE8
+#define R_028CEC_CB_COLOR2_ATTRIB 0x00028CEC
+#define R_028CF0_CB_COLOR2_DIM 0x00028CF0
+#define R_028D14_CB_COLOR3_BASE 0x00028D14
+#define R_028D18_CB_COLOR3_PITCH 0x00028D18
+#define R_028D1C_CB_COLOR3_SLICE 0x00028D1C
+#define R_028D20_CB_COLOR3_VIEW 0x00028D20
+#define R_028D24_CB_COLOR3_INFO 0x00028D24
+#define R_028D28_CB_COLOR3_ATTRIB 0x00028D28
+#define R_028D2C_CB_COLOR3_DIM 0x00028D2C
+#define R_028D50_CB_COLOR4_BASE 0x00028D50
+#define R_028D54_CB_COLOR4_PITCH 0x00028D54
+#define R_028D58_CB_COLOR4_SLICE 0x00028D58
+#define R_028D5C_CB_COLOR4_VIEW 0x00028D5C
+#define R_028D60_CB_COLOR4_INFO 0x00028D60
+#define R_028D64_CB_COLOR4_ATTRIB 0x00028D64
+#define R_028D68_CB_COLOR4_DIM 0x00028D68
+#define R_028D8C_CB_COLOR5_BASE 0x00028D8C
+#define R_028D90_CB_COLOR5_PITCH 0x00028D90
+#define R_028D94_CB_COLOR5_SLICE 0x00028D94
+#define R_028D98_CB_COLOR5_VIEW 0x00028D98
+#define R_028D9C_CB_COLOR5_INFO 0x00028D9C
+#define R_028DA0_CB_COLOR5_ATTRIB 0x00028DA0
+#define R_028DA4_CB_COLOR5_DIM 0x00028DA4
+#define R_028DC8_CB_COLOR6_BASE 0x00028DC8
+#define R_028DCC_CB_COLOR6_PITCH 0x00028DCC
+#define R_028DD0_CB_COLOR6_SLICE 0x00028DD0
+#define R_028DD4_CB_COLOR6_VIEW 0x00028DD4
+#define R_028DD8_CB_COLOR6_INFO 0x00028DD8
+#define R_028DDC_CB_COLOR6_ATTRIB 0x00028DDC
+#define R_028DE0_CB_COLOR6_DIM 0x00028DE0
+#define R_028E04_CB_COLOR7_BASE 0x00028E04
+#define R_028E08_CB_COLOR7_PITCH 0x00028E08
+#define R_028E0C_CB_COLOR7_SLICE 0x00028E0C
+#define R_028E10_CB_COLOR7_VIEW 0x00028E10
+#define R_028E14_CB_COLOR7_INFO 0x00028E14
+#define R_028E18_CB_COLOR7_ATTRIB 0x00028E18
+#define R_028E1C_CB_COLOR7_DIM 0x00028E1C
+#define R_028E40_CB_COLOR8_BASE 0x00028E40
+#define R_028E44_CB_COLOR8_PITCH 0x00028E44
+#define R_028E48_CB_COLOR8_SLICE 0x00028E48
+#define R_028E4C_CB_COLOR8_VIEW 0x00028E4C
+#define R_028E50_CB_COLOR8_INFO 0x00028E50
+#define R_028E54_CB_COLOR8_ATTRIB 0x00028E54
+#define R_028E58_CB_COLOR8_DIM 0x00028E58
+#define R_028E5C_CB_COLOR9_BASE 0x00028E5C
+#define R_028E60_CB_COLOR9_PITCH 0x00028E60
+#define R_028E64_CB_COLOR9_SLICE 0x00028E64
+#define R_028E68_CB_COLOR9_VIEW 0x00028E68
+#define R_028E6C_CB_COLOR9_INFO 0x00028E6C
+#define R_028E70_CB_COLOR9_ATTRIB 0x00028E70
+#define R_028E74_CB_COLOR9_DIM 0x00028E74
+#define R_028E78_CB_COLOR10_BASE 0x00028E78
+#define R_028E7C_CB_COLOR10_PITCH 0x00028E7C
+#define R_028E80_CB_COLOR10_SLICE 0x00028E80
+#define R_028E84_CB_COLOR10_VIEW 0x00028E84
+#define R_028E88_CB_COLOR10_INFO 0x00028E88
+#define R_028E8C_CB_COLOR10_ATTRIB 0x00028E8C
+#define R_028E90_CB_COLOR10_DIM 0x00028E90
+#define R_028E94_CB_COLOR11_BASE 0x00028E94
+#define R_028E98_CB_COLOR11_PITCH 0x00028E98
+#define R_028E9C_CB_COLOR11_SLICE 0x00028E9C
+#define R_028EA0_CB_COLOR11_VIEW 0x00028EA0
+#define R_028EA4_CB_COLOR11_INFO 0x00028EA4
+#define R_028EA8_CB_COLOR11_ATTRIB 0x00028EA8
+#define R_028EAC_CB_COLOR11_DIM 0x00028EAC
+#define R_030000_RESOURCE0_WORD0 0x00030000
+#define R_030004_RESOURCE0_WORD1 0x00030004
+#define R_030008_RESOURCE0_WORD2 0x00030008
+#define R_03000C_RESOURCE0_WORD3 0x0003000C
+#define R_030010_RESOURCE0_WORD4 0x00030010
+#define R_030014_RESOURCE0_WORD5 0x00030014
+#define R_030018_RESOURCE0_WORD6 0x00030018
+#define R_03001C_RESOURCE0_WORD7 0x0003001C
+#define R_0085F0_CP_COHER_CNTL 0x0085F0
+#define S_0085F0_DEST_BASE_0_ENA(x) (((x) & 0x1) << 0)
+#define G_0085F0_DEST_BASE_0_ENA(x) (((x) >> 0) & 0x1)
+#define C_0085F0_DEST_BASE_0_ENA 0xFFFFFFFE
+#define S_0085F0_DEST_BASE_1_ENA(x) (((x) & 0x1) << 1)
+#define G_0085F0_DEST_BASE_1_ENA(x) (((x) >> 1) & 0x1)
+#define C_0085F0_DEST_BASE_1_ENA 0xFFFFFFFD
+#define S_0085F0_SO0_DEST_BASE_ENA(x) (((x) & 0x1) << 2)
+#define G_0085F0_SO0_DEST_BASE_ENA(x) (((x) >> 2) & 0x1)
+#define C_0085F0_SO0_DEST_BASE_ENA 0xFFFFFFFB
+#define S_0085F0_SO1_DEST_BASE_ENA(x) (((x) & 0x1) << 3)
+#define G_0085F0_SO1_DEST_BASE_ENA(x) (((x) >> 3) & 0x1)
+#define C_0085F0_SO1_DEST_BASE_ENA 0xFFFFFFF7
+#define S_0085F0_SO2_DEST_BASE_ENA(x) (((x) & 0x1) << 4)
+#define G_0085F0_SO2_DEST_BASE_ENA(x) (((x) >> 4) & 0x1)
+#define C_0085F0_SO2_DEST_BASE_ENA 0xFFFFFFEF
+#define S_0085F0_SO3_DEST_BASE_ENA(x) (((x) & 0x1) << 5)
+#define G_0085F0_SO3_DEST_BASE_ENA(x) (((x) >> 5) & 0x1)
+#define C_0085F0_SO3_DEST_BASE_ENA 0xFFFFFFDF
+#define S_0085F0_CB0_DEST_BASE_ENA(x) (((x) & 0x1) << 6)
+#define G_0085F0_CB0_DEST_BASE_ENA(x) (((x) >> 6) & 0x1)
+#define C_0085F0_CB0_DEST_BASE_ENA 0xFFFFFFBF
+#define S_0085F0_CB1_DEST_BASE_ENA(x) (((x) & 0x1) << 7)
+#define G_0085F0_CB1_DEST_BASE_ENA(x) (((x) >> 7) & 0x1)
+#define C_0085F0_CB1_DEST_BASE_ENA 0xFFFFFF7F
+#define S_0085F0_CB2_DEST_BASE_ENA(x) (((x) & 0x1) << 8)
+#define G_0085F0_CB2_DEST_BASE_ENA(x) (((x) >> 8) & 0x1)
+#define C_0085F0_CB2_DEST_BASE_ENA 0xFFFFFEFF
+#define S_0085F0_CB3_DEST_BASE_ENA(x) (((x) & 0x1) << 9)
+#define G_0085F0_CB3_DEST_BASE_ENA(x) (((x) >> 9) & 0x1)
+#define C_0085F0_CB3_DEST_BASE_ENA 0xFFFFFDFF
+#define S_0085F0_CB4_DEST_BASE_ENA(x) (((x) & 0x1) << 10)
+#define G_0085F0_CB4_DEST_BASE_ENA(x) (((x) >> 10) & 0x1)
+#define C_0085F0_CB4_DEST_BASE_ENA 0xFFFFFBFF
+#define S_0085F0_CB5_DEST_BASE_ENA(x) (((x) & 0x1) << 11)
+#define G_0085F0_CB5_DEST_BASE_ENA(x) (((x) >> 11) & 0x1)
+#define C_0085F0_CB5_DEST_BASE_ENA 0xFFFFF7FF
+#define S_0085F0_CB6_DEST_BASE_ENA(x) (((x) & 0x1) << 12)
+#define G_0085F0_CB6_DEST_BASE_ENA(x) (((x) >> 12) & 0x1)
+#define C_0085F0_CB6_DEST_BASE_ENA 0xFFFFEFFF
+#define S_0085F0_CB7_DEST_BASE_ENA(x) (((x) & 0x1) << 13)
+#define G_0085F0_CB7_DEST_BASE_ENA(x) (((x) >> 13) & 0x1)
+#define C_0085F0_CB7_DEST_BASE_ENA 0xFFFFDFFF
+#define S_0085F0_DB_DEST_BASE_ENA(x) (((x) & 0x1) << 14)
+#define G_0085F0_DB_DEST_BASE_ENA(x) (((x) >> 14) & 0x1)
+#define C_0085F0_DB_DEST_BASE_ENA 0xFFFFBFFF
+#define S_0085F0_CR_DEST_BASE_ENA(x) (((x) & 0x1) << 15)
+#define G_0085F0_CR_DEST_BASE_ENA(x) (((x) >> 15) & 0x1)
+#define C_0085F0_CR_DEST_BASE_ENA 0xFFFF7FFF
+#define S_0085F0_TC_ACTION_ENA(x) (((x) & 0x1) << 23)
+#define G_0085F0_TC_ACTION_ENA(x) (((x) >> 23) & 0x1)
+#define C_0085F0_TC_ACTION_ENA 0xFF7FFFFF
+#define S_0085F0_VC_ACTION_ENA(x) (((x) & 0x1) << 24)
+#define G_0085F0_VC_ACTION_ENA(x) (((x) >> 24) & 0x1)
+#define C_0085F0_VC_ACTION_ENA 0xFEFFFFFF
+#define S_0085F0_CB_ACTION_ENA(x) (((x) & 0x1) << 25)
+#define G_0085F0_CB_ACTION_ENA(x) (((x) >> 25) & 0x1)
+#define C_0085F0_CB_ACTION_ENA 0xFDFFFFFF
+#define S_0085F0_DB_ACTION_ENA(x) (((x) & 0x1) << 26)
+#define G_0085F0_DB_ACTION_ENA(x) (((x) >> 26) & 0x1)
+#define C_0085F0_DB_ACTION_ENA 0xFBFFFFFF
+#define S_0085F0_SH_ACTION_ENA(x) (((x) & 0x1) << 27)
+#define G_0085F0_SH_ACTION_ENA(x) (((x) >> 27) & 0x1)
+#define C_0085F0_SH_ACTION_ENA 0xF7FFFFFF
+#define S_0085F0_SMX_ACTION_ENA(x) (((x) & 0x1) << 28)
+#define G_0085F0_SMX_ACTION_ENA(x) (((x) >> 28) & 0x1)
+#define C_0085F0_SMX_ACTION_ENA 0xEFFFFFFF
+#define S_0085F0_CR0_ACTION_ENA(x) (((x) & 0x1) << 29)
+#define G_0085F0_CR0_ACTION_ENA(x) (((x) >> 29) & 0x1)
+#define C_0085F0_CR0_ACTION_ENA 0xDFFFFFFF
+#define S_0085F0_CR1_ACTION_ENA(x) (((x) & 0x1) << 30)
+#define G_0085F0_CR1_ACTION_ENA(x) (((x) >> 30) & 0x1)
+#define C_0085F0_CR1_ACTION_ENA 0xBFFFFFFF
+#define S_0085F0_CR2_ACTION_ENA(x) (((x) & 0x1) << 31)
+#define G_0085F0_CR2_ACTION_ENA(x) (((x) >> 31) & 0x1)
+#define C_0085F0_CR2_ACTION_ENA 0x7FFFFFFF
+
#endif
R600_NGROUPS
};
+enum evergreen_group_id {
+ EVERGREEN_GROUP_CONFIG = 0,
+ EVERGREEN_GROUP_CONTEXT,
+ EVERGREEN_GROUP_RESOURCE,
+ EVERGREEN_GROUP_SAMPLER,
+ EVERGREEN_GROUP_CTL_CONST,
+ EVERGREEN_GROUP_LOOP_CONST,
+ EVERGREEN_GROUP_BOOL_CONST,
+ EVERGREEN_NGROUPS
+};
+
struct r600_pipe_reg {
unsigned group_id;
u32 offset;
void r600_query_begin(struct r600_context *ctx, struct r600_query *query);
void r600_query_end(struct r600_context *ctx, struct r600_query *query);
+int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon);
+void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *draw);
+void evergreen_ps_resource_set(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
+void evergreen_vs_resource_set(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
+
#endif
--- /dev/null
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Jerome Glisse
+ */
+#ifndef R600_PIPE_H
+#define R600_PIPE_H
+
+enum r600_pipe_state_id {
+ R600_PIPE_STATE_BLEND = 0,
+ R600_PIPE_STATE_BLEND_COLOR,
+ R600_PIPE_STATE_CONFIG,
+ R600_PIPE_STATE_CLIP,
+ R600_PIPE_STATE_SCISSOR,
+ R600_PIPE_STATE_VIEWPORT,
+ R600_PIPE_STATE_RASTERIZER,
+ R600_PIPE_STATE_VGT,
+ R600_PIPE_STATE_FRAMEBUFFER,
+ R600_PIPE_STATE_DSA,
+ R600_PIPE_STATE_STENCIL_REF,
+ R600_PIPE_STATE_PS_SHADER,
+ R600_PIPE_STATE_VS_SHADER,
+ R600_PIPE_STATE_CONSTANT,
+ R600_PIPE_STATE_SAMPLER,
+ R600_PIPE_STATE_RESOURCE,
+ R600_PIPE_NSTATES
+};
+
+struct r600_screen {
+ struct pipe_screen screen;
+ struct radeon *radeon;
+};
+
+struct r600_pipe_sampler_view {
+ struct pipe_sampler_view base;
+ struct r600_pipe_state state;
+};
+
+struct r600_pipe_rasterizer {
+ struct r600_pipe_state rstate;
+ bool flatshade;
+ unsigned sprite_coord_enable;
+};
+
+struct r600_pipe_blend {
+ struct r600_pipe_state rstate;
+ unsigned cb_target_mask;
+};
+
+struct r600_pipe_shader {
+ struct r600_shader shader;
+ struct r600_pipe_state rstate;
+ struct radeon_ws_bo *bo;
+};
+
+struct r600_vertex_element
+{
+ unsigned count;
+ unsigned refcount;
+ struct pipe_vertex_element elements[32];
+};
+
+struct r600_pipe_context {
+ struct pipe_context context;
+ struct r600_screen *screen;
+ struct radeon *radeon;
+ struct blitter_context *blitter;
+ struct r600_pipe_state *states[R600_PIPE_NSTATES];
+ struct r600_context ctx;
+ struct r600_vertex_element *vertex_elements;
+ struct pipe_framebuffer_state framebuffer;
+ struct pipe_index_buffer index_buffer;
+ struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS];
+ unsigned nvertex_buffer;
+ unsigned cb_target_mask;
+ /* for saving when using blitter */
+ struct pipe_stencil_ref stencil_ref;
+ struct pipe_viewport_state viewport;
+ struct pipe_clip_state clip;
+ unsigned vs_nconst;
+ unsigned ps_nconst;
+ struct r600_pipe_state vs_const[256];
+ struct r600_pipe_state ps_const[256];
+ struct r600_pipe_state vs_resource[160];
+ struct r600_pipe_state ps_resource[160];
+ struct r600_pipe_state config;
+ struct r600_pipe_shader *ps_shader;
+ struct r600_pipe_shader *vs_shader;
+ struct r600_pipe_state vs_const_buffer;
+ struct r600_pipe_state ps_const_buffer;
+ /* shader information */
+ unsigned sprite_coord_enable;
+ bool flatshade;
+};
+
+struct r600_drawl {
+ struct pipe_context *ctx;
+ unsigned mode;
+ unsigned start;
+ unsigned count;
+ unsigned index_size;
+ struct pipe_resource *index_buffer;
+};
+
+uint32_t r600_translate_texformat(enum pipe_format format,
+ const unsigned char *swizzle_view,
+ uint32_t *word4_p, uint32_t *yuv_format_p);
+
+/* r600_state2.c */
+int r600_pipe_shader_update2(struct pipe_context *ctx, struct r600_pipe_shader *shader);
+int r600_pipe_shader_create2(struct pipe_context *ctx, struct r600_pipe_shader *shader, const struct tgsi_token *tokens);
+
+/* evergreen_state.c */
+void evergreen_init_state_functions2(struct r600_pipe_context *rctx);
+void evergreen_init_config2(struct r600_pipe_context *rctx);
+void evergreen_draw(struct pipe_context *ctx, const struct pipe_draw_info *info);
+void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
+void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
+
+static INLINE u32 S_FIXED(float value, u32 frac_bits)
+{
+ return value * (1 << frac_bits);
+}
+#define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
+
+#endif
};
#include "r600_resource.h"
#include "r600_shader.h"
-
-
-uint32_t r600_translate_texformat(enum pipe_format format,
- const unsigned char *swizzle_view,
- uint32_t *word4_p, uint32_t *yuv_format_p);
-
+#include "r600_pipe.h"
#include "r600_state_inlines.h"
-enum r600_pipe_state_id {
- R600_PIPE_STATE_BLEND = 0,
- R600_PIPE_STATE_BLEND_COLOR,
- R600_PIPE_STATE_CONFIG,
- R600_PIPE_STATE_CLIP,
- R600_PIPE_STATE_SCISSOR,
- R600_PIPE_STATE_VIEWPORT,
- R600_PIPE_STATE_RASTERIZER,
- R600_PIPE_STATE_VGT,
- R600_PIPE_STATE_FRAMEBUFFER,
- R600_PIPE_STATE_DSA,
- R600_PIPE_STATE_STENCIL_REF,
- R600_PIPE_STATE_PS_SHADER,
- R600_PIPE_STATE_VS_SHADER,
- R600_PIPE_STATE_CONSTANT,
- R600_PIPE_STATE_SAMPLER,
- R600_PIPE_STATE_RESOURCE,
- R600_PIPE_NSTATES
-};
-
-struct r600_screen {
- struct pipe_screen screen;
- struct radeon *radeon;
-};
-
-struct r600_pipe_sampler_view {
- struct pipe_sampler_view base;
- struct r600_pipe_state state;
-};
-
-struct r600_pipe_rasterizer {
- struct r600_pipe_state rstate;
- bool flatshade;
- unsigned sprite_coord_enable;
-};
-
-struct r600_pipe_blend {
- struct r600_pipe_state rstate;
- unsigned cb_target_mask;
-};
-
-struct r600_pipe_shader {
- struct r600_shader shader;
- struct r600_pipe_state rstate;
- struct radeon_ws_bo *bo;
-};
-
-struct r600_vertex_element
-{
- unsigned count;
- unsigned refcount;
- struct pipe_vertex_element elements[32];
-};
-
-struct r600_pipe_context {
- struct pipe_context context;
- struct r600_screen *screen;
- struct radeon *radeon;
- struct blitter_context *blitter;
- struct r600_pipe_state *states[R600_PIPE_NSTATES];
- struct r600_context ctx;
- struct r600_vertex_element *vertex_elements;
- struct pipe_framebuffer_state framebuffer;
- struct pipe_index_buffer index_buffer;
- struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS];
- unsigned nvertex_buffer;
- unsigned cb_target_mask;
- /* for saving when using blitter */
- struct pipe_stencil_ref stencil_ref;
- struct pipe_viewport_state viewport;
- struct pipe_clip_state clip;
- unsigned vs_nconst;
- unsigned ps_nconst;
- struct r600_pipe_state vs_const[256];
- struct r600_pipe_state ps_const[256];
- struct r600_pipe_state vs_resource[160];
- struct r600_pipe_state ps_resource[160];
- struct r600_pipe_state config;
- struct r600_pipe_shader *ps_shader;
- struct r600_pipe_shader *vs_shader;
- /* shader information */
- unsigned sprite_coord_enable;
- bool flatshade;
-};
-
-static INLINE u32 S_FIXED(float value, u32 frac_bits)
-{
- return value * (1 << frac_bits);
-}
-
/* r600_shader.c */
static void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
{
- struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
struct r600_pipe_state *rstate = &shader->rstate;
struct r600_shader *rshader = &shader->shader;
unsigned spi_vs_out_id[10];
rshader->flat_shade = rctx->flatshade;
switch (rshader->processor_type) {
case TGSI_PROCESSOR_VERTEX:
- r600_pipe_shader_vs(ctx, shader);
+ if (rshader->family >= CHIP_CEDAR) {
+ evergreen_pipe_shader_vs(ctx, shader);
+ } else {
+ r600_pipe_shader_vs(ctx, shader);
+ }
break;
case TGSI_PROCESSOR_FRAGMENT:
- r600_pipe_shader_ps(ctx, shader);
+ if (rshader->family >= CHIP_CEDAR) {
+ evergreen_pipe_shader_ps(ctx, shader);
+ } else {
+ r600_pipe_shader_ps(ctx, shader);
+ }
break;
default:
return -EINVAL;
return r600_bc_build(&shader->bc);
}
-static int r600_pipe_shader_update2(struct pipe_context *ctx, struct r600_pipe_shader *shader)
+int r600_pipe_shader_update2(struct pipe_context *ctx, struct r600_pipe_shader *shader)
{
struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
int r;
}
int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader);
-static int r600_pipe_shader_create2(struct pipe_context *ctx, struct r600_pipe_shader *shader, const struct tgsi_token *tokens)
+int r600_pipe_shader_create2(struct pipe_context *ctx, struct r600_pipe_shader *shader, const struct tgsi_token *tokens)
{
struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
int r;
FREE(rscreen);
}
-struct r600_drawl {
- struct pipe_context *ctx;
- unsigned mode;
- unsigned start;
- unsigned count;
- unsigned index_size;
- struct pipe_resource *index_buffer;
-};
-
int r600_conv_pipe_prim(unsigned pprim, unsigned *prim);
static void r600_draw_common(struct r600_drawl *draw)
{
rctx->context.screen = screen;
rctx->context.priv = priv;
rctx->context.destroy = r600_destroy_context;
- rctx->context.draw_vbo = r600_draw_vbo2;
rctx->context.flush = r600_flush2;
/* Easy accessing of screen/winsys. */
r600_init_blit_functions2(rctx);
r600_init_query_functions2(rctx);
- r600_init_state_functions2(rctx);
r600_init_context_resource_functions2(rctx);
rctx->blitter = util_blitter_create(&rctx->context);
return NULL;
}
- if (r600_context_init(&rctx->ctx, rctx->radeon)) {
+ switch (r600_get_family(rctx->radeon)) {
+ case CHIP_R600:
+ case CHIP_RV610:
+ case CHIP_RV630:
+ case CHIP_RV670:
+ case CHIP_RV620:
+ case CHIP_RV635:
+ case CHIP_RS780:
+ case CHIP_RS880:
+ case CHIP_RV770:
+ case CHIP_RV730:
+ case CHIP_RV710:
+ case CHIP_RV740:
+ rctx->context.draw_vbo = r600_draw_vbo2;
+ r600_init_state_functions2(rctx);
+ if (r600_context_init(&rctx->ctx, rctx->radeon)) {
+ r600_destroy_context(&rctx->context);
+ return NULL;
+ }
+ r600_init_config2(rctx);
+ break;
+ case CHIP_CEDAR:
+ case CHIP_REDWOOD:
+ case CHIP_JUNIPER:
+ case CHIP_CYPRESS:
+ case CHIP_HEMLOCK:
+ rctx->context.draw_vbo = evergreen_draw;
+ evergreen_init_state_functions2(rctx);
+ if (evergreen_context_init(&rctx->ctx, rctx->radeon)) {
+ r600_destroy_context(&rctx->context);
+ return NULL;
+ }
+ evergreen_init_config2(rctx);
+ break;
+ default:
+ R600_ERR("unsupported family %d\n", r600_get_family(rctx->radeon));
r600_destroy_context(&rctx->context);
return NULL;
}
- r600_init_config2(rctx);
-
return &rctx->context;
}
bof.c \
r600_state.c \
r600_state2.c \
+ evergreen_state.c \
r600.c \
radeon_ctx.c \
radeon_draw.c \
--- /dev/null
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Jerome Glisse
+ */
+#include <errno.h>
+#include <stdint.h>
+#include <string.h>
+#include <stdlib.h>
+#include <assert.h>
+#include "xf86drm.h"
+#include "r600.h"
+#include "evergreend.h"
+#include "r600_priv.h"
+#include "radeon_drm.h"
+#include "bof.h"
+#include "pipe/p_compiler.h"
+#include "util/u_inlines.h"
+#include <pipebuffer/pb_bufmgr.h>
+
+struct radeon_bo {
+ struct pipe_reference reference;
+ unsigned handle;
+ unsigned size;
+ unsigned alignment;
+ unsigned map_count;
+ void *data;
+};
+struct radeon_ws_bo {
+ struct pipe_reference reference;
+ struct pb_buffer *pb;
+};
+struct radeon_bo *radeon_bo_pb_get_bo(struct pb_buffer *_buf);
+
+struct radeon_bo *r600_context_reg_bo(struct r600_context *ctx, unsigned group_id, unsigned offset);
+void r600_context_group_emit_dirty(struct r600_context *ctx, struct r600_group *group, unsigned opcode);
+void r600_context_bo_reloc(struct r600_context *ctx, u32 *pm4, struct radeon_bo *bo);
+int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg);
+int r600_group_init(struct r600_group *group, unsigned start_offset, unsigned end_offset);
+
+#define GROUP_FORCE_NEW_BLOCK 0
+static const struct r600_reg evergreen_reg_list[] = {
+ {0, 0, R_008958_VGT_PRIMITIVE_TYPE},
+ {0, 0, R_008A14_PA_CL_ENHANCE},
+ {0, 0, R_008C00_SQ_CONFIG},
+ {0, 0, R_008C04_SQ_GPR_RESOURCE_MGMT_1},
+ {0, 0, R_008C08_SQ_GPR_RESOURCE_MGMT_2},
+ {0, 0, R_008C0C_SQ_THREAD_RESOURCE_MGMT},
+ {0, 0, R_008C18_SQ_THREAD_RESOURCE_MGMT_1},
+ {0, 0, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2},
+ {0, 0, R_008C20_SQ_STACK_RESOURCE_MGMT_1},
+ {0, 0, R_008C24_SQ_STACK_RESOURCE_MGMT_2},
+ {0, 0, R_008C28_SQ_STACK_RESOURCE_MGMT_3},
+ {0, 0, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ},
+ {0, 0, R_009100_SPI_CONFIG_CNTL},
+ {0, 0, R_00913C_SPI_CONFIG_CNTL_1},
+ {0, 0, R_028000_DB_RENDER_CONTROL},
+ {0, 0, R_028008_DB_DEPTH_VIEW},
+ {0, 0, R_02800C_DB_RENDER_OVERRIDE},
+ {0, 0, R_028010_DB_RENDER_OVERRIDE2},
+ {1, 0, R_028014_DB_HTILE_DATA_BASE},
+ {0, 0, R_028028_DB_STENCIL_CLEAR},
+ {0, 0, R_02802C_DB_DEPTH_CLEAR},
+ {0, 0, R_028030_PA_SC_SCREEN_SCISSOR_TL},
+ {0, 0, R_028034_PA_SC_SCREEN_SCISSOR_BR},
+ {1, 0, R_028040_DB_Z_INFO},
+ {0, 0, R_028044_DB_STENCIL_INFO},
+ {1, 0, R_028048_DB_Z_READ_BASE},
+ {1, 0, R_02804C_DB_STENCIL_READ_BASE},
+ {1, 0, R_028050_DB_Z_WRITE_BASE},
+ {1, 0, R_028054_DB_STENCIL_WRITE_BASE},
+ {0, 0, R_028058_DB_DEPTH_SIZE},
+ {0, 0, R_02805C_DB_DEPTH_SLICE},
+ {0, 0, R_028140_ALU_CONST_BUFFER_SIZE_PS_0},
+ {0, 0, R_028180_ALU_CONST_BUFFER_SIZE_VS_0},
+ {0, 0, R_028200_PA_SC_WINDOW_OFFSET},
+ {0, 0, R_028204_PA_SC_WINDOW_SCISSOR_TL},
+ {0, 0, R_028208_PA_SC_WINDOW_SCISSOR_BR},
+ {0, 0, R_02820C_PA_SC_CLIPRECT_RULE},
+ {0, 0, R_028210_PA_SC_CLIPRECT_0_TL},
+ {0, 0, R_028214_PA_SC_CLIPRECT_0_BR},
+ {0, 0, R_028218_PA_SC_CLIPRECT_1_TL},
+ {0, 0, R_02821C_PA_SC_CLIPRECT_1_BR},
+ {0, 0, R_028220_PA_SC_CLIPRECT_2_TL},
+ {0, 0, R_028224_PA_SC_CLIPRECT_2_BR},
+ {0, 0, R_028228_PA_SC_CLIPRECT_3_TL},
+ {0, 0, R_02822C_PA_SC_CLIPRECT_3_BR},
+ {0, 0, R_028230_PA_SC_EDGERULE},
+ {0, 0, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET},
+ {0, 0, R_028238_CB_TARGET_MASK},
+ {0, 0, R_02823C_CB_SHADER_MASK},
+ {0, 0, R_028240_PA_SC_GENERIC_SCISSOR_TL},
+ {0, 0, R_028244_PA_SC_GENERIC_SCISSOR_BR},
+ {0, 0, R_028250_PA_SC_VPORT_SCISSOR_0_TL},
+ {0, 0, R_028254_PA_SC_VPORT_SCISSOR_0_BR},
+ {0, 0, R_028350_SX_MISC},
+ {0, 0, R_028380_SQ_VTX_SEMANTIC_0},
+ {0, 0, R_028384_SQ_VTX_SEMANTIC_1},
+ {0, 0, R_028388_SQ_VTX_SEMANTIC_2},
+ {0, 0, R_02838C_SQ_VTX_SEMANTIC_3},
+ {0, 0, R_028390_SQ_VTX_SEMANTIC_4},
+ {0, 0, R_028394_SQ_VTX_SEMANTIC_5},
+ {0, 0, R_028398_SQ_VTX_SEMANTIC_6},
+ {0, 0, R_02839C_SQ_VTX_SEMANTIC_7},
+ {0, 0, R_0283A0_SQ_VTX_SEMANTIC_8},
+ {0, 0, R_0283A4_SQ_VTX_SEMANTIC_9},
+ {0, 0, R_0283A8_SQ_VTX_SEMANTIC_10},
+ {0, 0, R_0283AC_SQ_VTX_SEMANTIC_11},
+ {0, 0, R_0283B0_SQ_VTX_SEMANTIC_12},
+ {0, 0, R_0283B4_SQ_VTX_SEMANTIC_13},
+ {0, 0, R_0283B8_SQ_VTX_SEMANTIC_14},
+ {0, 0, R_0283BC_SQ_VTX_SEMANTIC_15},
+ {0, 0, R_0283C0_SQ_VTX_SEMANTIC_16},
+ {0, 0, R_0283C4_SQ_VTX_SEMANTIC_17},
+ {0, 0, R_0283C8_SQ_VTX_SEMANTIC_18},
+ {0, 0, R_0283CC_SQ_VTX_SEMANTIC_19},
+ {0, 0, R_0283D0_SQ_VTX_SEMANTIC_20},
+ {0, 0, R_0283D4_SQ_VTX_SEMANTIC_21},
+ {0, 0, R_0283D8_SQ_VTX_SEMANTIC_22},
+ {0, 0, R_0283DC_SQ_VTX_SEMANTIC_23},
+ {0, 0, R_0283E0_SQ_VTX_SEMANTIC_24},
+ {0, 0, R_0283E4_SQ_VTX_SEMANTIC_25},
+ {0, 0, R_0283E8_SQ_VTX_SEMANTIC_26},
+ {0, 0, R_0283EC_SQ_VTX_SEMANTIC_27},
+ {0, 0, R_0283F0_SQ_VTX_SEMANTIC_28},
+ {0, 0, R_0283F4_SQ_VTX_SEMANTIC_29},
+ {0, 0, R_0283F8_SQ_VTX_SEMANTIC_30},
+ {0, 0, R_0283FC_SQ_VTX_SEMANTIC_31},
+ {0, 0, R_0282D0_PA_SC_VPORT_ZMIN_0},
+ {0, 0, R_0282D4_PA_SC_VPORT_ZMAX_0},
+ {0, 0, R_028400_VGT_MAX_VTX_INDX},
+ {0, 0, R_028404_VGT_MIN_VTX_INDX},
+ {0, 0, R_028408_VGT_INDX_OFFSET},
+ {0, 0, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX},
+ {0, 0, R_028410_SX_ALPHA_TEST_CONTROL},
+ {0, 0, R_028414_CB_BLEND_RED},
+ {0, 0, R_028418_CB_BLEND_GREEN},
+ {0, 0, R_02841C_CB_BLEND_BLUE},
+ {0, 0, R_028420_CB_BLEND_ALPHA},
+ {0, 0, R_028430_DB_STENCILREFMASK},
+ {0, 0, R_028434_DB_STENCILREFMASK_BF},
+ {0, 0, R_028438_SX_ALPHA_REF},
+ {0, 0, R_02843C_PA_CL_VPORT_XSCALE_0},
+ {0, 0, R_028440_PA_CL_VPORT_XOFFSET_0},
+ {0, 0, R_028444_PA_CL_VPORT_YSCALE_0},
+ {0, 0, R_028448_PA_CL_VPORT_YOFFSET_0},
+ {0, 0, R_02844C_PA_CL_VPORT_ZSCALE_0},
+ {0, 0, R_028450_PA_CL_VPORT_ZOFFSET_0},
+ {0, 0, R_0285BC_PA_CL_UCP0_X},
+ {0, 0, R_0285C0_PA_CL_UCP0_Y},
+ {0, 0, R_0285C4_PA_CL_UCP0_Z},
+ {0, 0, R_0285C8_PA_CL_UCP0_W},
+ {0, 0, R_0285CC_PA_CL_UCP1_X},
+ {0, 0, R_0285D0_PA_CL_UCP1_Y},
+ {0, 0, R_0285D4_PA_CL_UCP1_Z},
+ {0, 0, R_0285D8_PA_CL_UCP1_W},
+ {0, 0, R_0285DC_PA_CL_UCP2_X},
+ {0, 0, R_0285E0_PA_CL_UCP2_Y},
+ {0, 0, R_0285E4_PA_CL_UCP2_Z},
+ {0, 0, R_0285E8_PA_CL_UCP2_W},
+ {0, 0, R_0285EC_PA_CL_UCP3_X},
+ {0, 0, R_0285F0_PA_CL_UCP3_Y},
+ {0, 0, R_0285F4_PA_CL_UCP3_Z},
+ {0, 0, R_0285F8_PA_CL_UCP3_W},
+ {0, 0, R_0285FC_PA_CL_UCP4_X},
+ {0, 0, R_028600_PA_CL_UCP4_Y},
+ {0, 0, R_028604_PA_CL_UCP4_Z},
+ {0, 0, R_028608_PA_CL_UCP4_W},
+ {0, 0, R_02860C_PA_CL_UCP5_X},
+ {0, 0, R_028610_PA_CL_UCP5_Y},
+ {0, 0, R_028614_PA_CL_UCP5_Z},
+ {0, 0, R_028618_PA_CL_UCP5_W},
+ {0, 0, R_02861C_SPI_VS_OUT_ID_0},
+ {0, 0, R_028620_SPI_VS_OUT_ID_1},
+ {0, 0, R_028624_SPI_VS_OUT_ID_2},
+ {0, 0, R_028628_SPI_VS_OUT_ID_3},
+ {0, 0, R_02862C_SPI_VS_OUT_ID_4},
+ {0, 0, R_028630_SPI_VS_OUT_ID_5},
+ {0, 0, R_028634_SPI_VS_OUT_ID_6},
+ {0, 0, R_028638_SPI_VS_OUT_ID_7},
+ {0, 0, R_02863C_SPI_VS_OUT_ID_8},
+ {0, 0, R_028640_SPI_VS_OUT_ID_9},
+ {0, 0, R_028644_SPI_PS_INPUT_CNTL_0},
+ {0, 0, R_028648_SPI_PS_INPUT_CNTL_1},
+ {0, 0, R_02864C_SPI_PS_INPUT_CNTL_2},
+ {0, 0, R_028650_SPI_PS_INPUT_CNTL_3},
+ {0, 0, R_028654_SPI_PS_INPUT_CNTL_4},
+ {0, 0, R_028658_SPI_PS_INPUT_CNTL_5},
+ {0, 0, R_02865C_SPI_PS_INPUT_CNTL_6},
+ {0, 0, R_028660_SPI_PS_INPUT_CNTL_7},
+ {0, 0, R_028664_SPI_PS_INPUT_CNTL_8},
+ {0, 0, R_028668_SPI_PS_INPUT_CNTL_9},
+ {0, 0, R_02866C_SPI_PS_INPUT_CNTL_10},
+ {0, 0, R_028670_SPI_PS_INPUT_CNTL_11},
+ {0, 0, R_028674_SPI_PS_INPUT_CNTL_12},
+ {0, 0, R_028678_SPI_PS_INPUT_CNTL_13},
+ {0, 0, R_02867C_SPI_PS_INPUT_CNTL_14},
+ {0, 0, R_028680_SPI_PS_INPUT_CNTL_15},
+ {0, 0, R_028684_SPI_PS_INPUT_CNTL_16},
+ {0, 0, R_028688_SPI_PS_INPUT_CNTL_17},
+ {0, 0, R_02868C_SPI_PS_INPUT_CNTL_18},
+ {0, 0, R_028690_SPI_PS_INPUT_CNTL_19},
+ {0, 0, R_028694_SPI_PS_INPUT_CNTL_20},
+ {0, 0, R_028698_SPI_PS_INPUT_CNTL_21},
+ {0, 0, R_02869C_SPI_PS_INPUT_CNTL_22},
+ {0, 0, R_0286A0_SPI_PS_INPUT_CNTL_23},
+ {0, 0, R_0286A4_SPI_PS_INPUT_CNTL_24},
+ {0, 0, R_0286A8_SPI_PS_INPUT_CNTL_25},
+ {0, 0, R_0286AC_SPI_PS_INPUT_CNTL_26},
+ {0, 0, R_0286B0_SPI_PS_INPUT_CNTL_27},
+ {0, 0, R_0286B4_SPI_PS_INPUT_CNTL_28},
+ {0, 0, R_0286B8_SPI_PS_INPUT_CNTL_29},
+ {0, 0, R_0286BC_SPI_PS_INPUT_CNTL_30},
+ {0, 0, R_0286C0_SPI_PS_INPUT_CNTL_31},
+ {0, 0, R_0286C4_SPI_VS_OUT_CONFIG},
+ {0, 0, R_0286C8_SPI_THREAD_GROUPING},
+ {0, 0, R_0286CC_SPI_PS_IN_CONTROL_0},
+ {0, 0, R_0286D0_SPI_PS_IN_CONTROL_1},
+ {0, 0, R_0286D4_SPI_INTERP_CONTROL_0},
+ {0, 0, R_0286D8_SPI_INPUT_Z},
+ {0, 0, R_0286DC_SPI_FOG_CNTL},
+ {0, 0, R_0286E0_SPI_BARYC_CNTL},
+ {0, 0, R_0286E4_SPI_PS_IN_CONTROL_2},
+ {0, 0, R_0286E8_SPI_COMPUTE_INPUT_CNTL},
+ {0, 0, R_028780_CB_BLEND0_CONTROL},
+ {0, 0, R_028784_CB_BLEND1_CONTROL},
+ {0, 0, R_028788_CB_BLEND2_CONTROL},
+ {0, 0, R_02878C_CB_BLEND3_CONTROL},
+ {0, 0, R_028790_CB_BLEND4_CONTROL},
+ {0, 0, R_028794_CB_BLEND5_CONTROL},
+ {0, 0, R_028798_CB_BLEND6_CONTROL},
+ {0, 0, R_02879C_CB_BLEND7_CONTROL},
+ {0, 0, R_028800_DB_DEPTH_CONTROL},
+ {0, 0, R_02880C_DB_SHADER_CONTROL},
+ {0, 0, R_028808_CB_COLOR_CONTROL},
+ {0, 0, R_028810_PA_CL_CLIP_CNTL},
+ {0, 0, R_028814_PA_SU_SC_MODE_CNTL},
+ {0, 0, R_028818_PA_CL_VTE_CNTL},
+ {0, 0, R_02881C_PA_CL_VS_OUT_CNTL},
+ {0, 0, R_028820_PA_CL_NANINF_CNTL},
+ {0, 0, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1},
+ {1, 0, R_028840_SQ_PGM_START_PS},
+ {0, 0, R_028844_SQ_PGM_RESOURCES_PS},
+ {0, 0, R_028848_SQ_PGM_RESOURCES_2_PS},
+ {0, 0, R_02884C_SQ_PGM_EXPORTS_PS},
+ {1, 0, R_02885C_SQ_PGM_START_VS},
+ {0, 0, R_028860_SQ_PGM_RESOURCES_VS},
+ {0, 0, R_028864_SQ_PGM_RESOURCES_2_VS},
+ {1, 0, R_0288A4_SQ_PGM_START_FS},
+ {0, 0, R_0288A8_SQ_PGM_RESOURCES_FS},
+ {0, 0, R_0288EC_SQ_LDS_ALLOC_PS},
+ {0, 0, R_028900_SQ_ESGS_RING_ITEMSIZE},
+ {0, 0, R_028904_SQ_GSVS_RING_ITEMSIZE},
+ {0, 0, R_028908_SQ_ESTMP_RING_ITEMSIZE},
+ {0, 0, R_02890C_SQ_GSTMP_RING_ITEMSIZE},
+ {0, 0, R_028910_SQ_VSTMP_RING_ITEMSIZE},
+ {0, 0, R_028914_SQ_PSTMP_RING_ITEMSIZE},
+ {0, 0, R_02891C_SQ_GS_VERT_ITEMSIZE},
+ {0, 0, R_028920_SQ_GS_VERT_ITEMSIZE_1},
+ {0, 0, R_028924_SQ_GS_VERT_ITEMSIZE_2},
+ {0, 0, R_028928_SQ_GS_VERT_ITEMSIZE_3},
+ {1, 0, R_028940_ALU_CONST_CACHE_PS_0},
+ {1, 0, R_028980_ALU_CONST_CACHE_VS_0},
+ {0, 0, R_028A00_PA_SU_POINT_SIZE},
+ {0, 0, R_028A04_PA_SU_POINT_MINMAX},
+ {0, 0, R_028A08_PA_SU_LINE_CNTL},
+ {0, 0, R_028A10_VGT_OUTPUT_PATH_CNTL},
+ {0, 0, R_028A14_VGT_HOS_CNTL},
+ {0, 0, R_028A18_VGT_HOS_MAX_TESS_LEVEL},
+ {0, 0, R_028A1C_VGT_HOS_MIN_TESS_LEVEL},
+ {0, 0, R_028A20_VGT_HOS_REUSE_DEPTH},
+ {0, 0, R_028A24_VGT_GROUP_PRIM_TYPE},
+ {0, 0, R_028A28_VGT_GROUP_FIRST_DECR},
+ {0, 0, R_028A2C_VGT_GROUP_DECR},
+ {0, 0, R_028A30_VGT_GROUP_VECT_0_CNTL},
+ {0, 0, R_028A34_VGT_GROUP_VECT_1_CNTL},
+ {0, 0, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL},
+ {0, 0, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL},
+ {0, 0, R_028A40_VGT_GS_MODE},
+ {0, 0, R_028A48_PA_SC_MODE_CNTL_0},
+ {0, 0, R_028A4C_PA_SC_MODE_CNTL_1},
+ {0, 0, R_028AB4_VGT_REUSE_OFF},
+ {0, 0, R_028AB8_VGT_VTX_CNT_EN},
+ {0, 0, R_028ABC_DB_HTILE_SURFACE},
+ {0, 0, R_028AC0_DB_SRESULTS_COMPARE_STATE0},
+ {0, 0, R_028AC4_DB_SRESULTS_COMPARE_STATE1},
+ {0, 0, R_028AC8_DB_PRELOAD_CONTROL},
+ {0, 0, R_028B54_VGT_SHADER_STAGES_EN},
+ {0, 0, R_028B70_DB_ALPHA_TO_MASK},
+ {0, 0, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL},
+ {0, 0, R_028B7C_PA_SU_POLY_OFFSET_CLAMP},
+ {0, 0, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE},
+ {0, 0, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET},
+ {0, 0, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE},
+ {0, 0, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET},
+ {0, 0, R_028B94_VGT_STRMOUT_CONFIG},
+ {0, 0, R_028B98_VGT_STRMOUT_BUFFER_CONFIG},
+ {0, 0, R_028C00_PA_SC_LINE_CNTL},
+ {0, 0, R_028C04_PA_SC_AA_CONFIG},
+ {0, 0, R_028C08_PA_SU_VTX_CNTL},
+ {0, 0, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ},
+ {0, 0, R_028C10_PA_CL_GB_VERT_DISC_ADJ},
+ {0, 0, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ},
+ {0, 0, R_028C18_PA_CL_GB_HORZ_DISC_ADJ},
+ {0, 0, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX},
+ {0, 0, R_028C3C_PA_SC_AA_MASK},
+ {0, 0, GROUP_FORCE_NEW_BLOCK},
+ {1, 0, R_028C60_CB_COLOR0_BASE},
+ {0, 0, R_028C64_CB_COLOR0_PITCH},
+ {0, 0, R_028C68_CB_COLOR0_SLICE},
+ {0, 0, R_028C6C_CB_COLOR0_VIEW},
+ {1, 0, R_028C70_CB_COLOR0_INFO},
+ {0, 0, R_028C74_CB_COLOR0_ATTRIB},
+ {0, 0, R_028C78_CB_COLOR0_DIM},
+ {0, 0, GROUP_FORCE_NEW_BLOCK},
+ {1, 0, R_028C9C_CB_COLOR1_BASE},
+ {0, 0, R_028CA0_CB_COLOR1_PITCH},
+ {0, 0, R_028CA4_CB_COLOR1_SLICE},
+ {0, 0, R_028CA8_CB_COLOR1_VIEW},
+ {1, 0, R_028CAC_CB_COLOR1_INFO},
+ {0, 0, R_028CB0_CB_COLOR1_ATTRIB},
+ {0, 0, R_028CB8_CB_COLOR1_DIM},
+ {0, 0, GROUP_FORCE_NEW_BLOCK},
+ {1, 0, R_028CD8_CB_COLOR2_BASE},
+ {0, 0, R_028CDC_CB_COLOR2_PITCH},
+ {0, 0, R_028CE0_CB_COLOR2_SLICE},
+ {0, 0, R_028CE4_CB_COLOR2_VIEW},
+ {1, 0, R_028CE8_CB_COLOR2_INFO},
+ {0, 0, R_028CEC_CB_COLOR2_ATTRIB},
+ {0, 0, R_028CF0_CB_COLOR2_DIM},
+ {0, 0, GROUP_FORCE_NEW_BLOCK},
+ {1, 0, R_028D14_CB_COLOR3_BASE},
+ {0, 0, R_028D18_CB_COLOR3_PITCH},
+ {0, 0, R_028D1C_CB_COLOR3_SLICE},
+ {0, 0, R_028D20_CB_COLOR3_VIEW},
+ {1, 0, R_028D24_CB_COLOR3_INFO},
+ {0, 0, R_028D28_CB_COLOR3_ATTRIB},
+ {0, 0, R_028D2C_CB_COLOR3_DIM},
+ {0, 0, GROUP_FORCE_NEW_BLOCK},
+ {1, 0, R_028D50_CB_COLOR4_BASE},
+ {0, 0, R_028D54_CB_COLOR4_PITCH},
+ {0, 0, R_028D58_CB_COLOR4_SLICE},
+ {0, 0, R_028D5C_CB_COLOR4_VIEW},
+ {1, 0, R_028D60_CB_COLOR4_INFO},
+ {0, 0, R_028D64_CB_COLOR4_ATTRIB},
+ {0, 0, R_028D68_CB_COLOR4_DIM},
+ {0, 0, GROUP_FORCE_NEW_BLOCK},
+ {1, 0, R_028D8C_CB_COLOR5_BASE},
+ {0, 0, R_028D90_CB_COLOR5_PITCH},
+ {0, 0, R_028D94_CB_COLOR5_SLICE},
+ {0, 0, R_028D98_CB_COLOR5_VIEW},
+ {1, 0, R_028D9C_CB_COLOR5_INFO},
+ {0, 0, R_028DA0_CB_COLOR5_ATTRIB},
+ {0, 0, R_028DA4_CB_COLOR5_DIM},
+ {0, 0, GROUP_FORCE_NEW_BLOCK},
+ {1, 0, R_028DC8_CB_COLOR6_BASE},
+ {0, 0, R_028DCC_CB_COLOR6_PITCH},
+ {0, 0, R_028DD0_CB_COLOR6_SLICE},
+ {0, 0, R_028DD4_CB_COLOR6_VIEW},
+ {1, 0, R_028DD8_CB_COLOR6_INFO},
+ {0, 0, R_028DDC_CB_COLOR6_ATTRIB},
+ {0, 0, R_028DE0_CB_COLOR6_DIM},
+ {0, 0, GROUP_FORCE_NEW_BLOCK},
+ {1, 0, R_028E04_CB_COLOR7_BASE},
+ {0, 0, R_028E08_CB_COLOR7_PITCH},
+ {0, 0, R_028E0C_CB_COLOR7_SLICE},
+ {0, 0, R_028E10_CB_COLOR7_VIEW},
+ {1, 0, R_028E14_CB_COLOR7_INFO},
+ {0, 0, R_028E18_CB_COLOR7_ATTRIB},
+ {0, 0, R_028E1C_CB_COLOR7_DIM},
+ {0, 0, GROUP_FORCE_NEW_BLOCK},
+ {1, 0, R_028E40_CB_COLOR8_BASE},
+ {0, 0, R_028E44_CB_COLOR8_PITCH},
+ {0, 0, R_028E48_CB_COLOR8_SLICE},
+ {0, 0, R_028E4C_CB_COLOR8_VIEW},
+ {1, 0, R_028E50_CB_COLOR8_INFO},
+ {0, 0, R_028E54_CB_COLOR8_ATTRIB},
+ {0, 0, R_028E58_CB_COLOR8_DIM},
+ {0, 0, GROUP_FORCE_NEW_BLOCK},
+ {1, 0, R_028E5C_CB_COLOR9_BASE},
+ {0, 0, R_028E60_CB_COLOR9_PITCH},
+ {0, 0, R_028E64_CB_COLOR9_SLICE},
+ {0, 0, R_028E68_CB_COLOR9_VIEW},
+ {1, 0, R_028E6C_CB_COLOR9_INFO},
+ {0, 0, R_028E70_CB_COLOR9_ATTRIB},
+ {0, 0, R_028E74_CB_COLOR9_DIM},
+ {0, 0, GROUP_FORCE_NEW_BLOCK},
+ {1, 0, R_028E78_CB_COLOR10_BASE},
+ {0, 0, R_028E7C_CB_COLOR10_PITCH},
+ {0, 0, R_028E80_CB_COLOR10_SLICE},
+ {0, 0, R_028E84_CB_COLOR10_VIEW},
+ {1, 0, R_028E88_CB_COLOR10_INFO},
+ {0, 0, R_028E8C_CB_COLOR10_ATTRIB},
+ {0, 0, R_028E90_CB_COLOR10_DIM},
+ {0, 0, GROUP_FORCE_NEW_BLOCK},
+ {1, 0, R_028E94_CB_COLOR11_BASE},
+ {0, 0, R_028E98_CB_COLOR11_PITCH},
+ {0, 0, R_028E9C_CB_COLOR11_SLICE},
+ {0, 0, R_028EA0_CB_COLOR11_VIEW},
+ {1, 0, R_028EA4_CB_COLOR11_INFO},
+ {0, 0, R_028EA8_CB_COLOR11_ATTRIB},
+ {0, 0, R_028EAC_CB_COLOR11_DIM},
+};
+
+/* SHADER RESOURCE R600/R700 */
+static int evergreen_state_resource_init(struct r600_context *ctx, u32 offset)
+{
+ struct r600_reg r600_shader_resource[] = {
+ {0, 0, R_030000_RESOURCE0_WORD0},
+ {0, 0, R_030004_RESOURCE0_WORD1},
+ {1, 0, R_030008_RESOURCE0_WORD2},
+ {1, 0, R_03000C_RESOURCE0_WORD3},
+ {0, 0, R_030010_RESOURCE0_WORD4},
+ {0, 0, R_030014_RESOURCE0_WORD5},
+ {0, 0, R_030018_RESOURCE0_WORD6},
+ {0, 0, R_03001C_RESOURCE0_WORD7},
+ };
+ unsigned nreg = sizeof(r600_shader_resource)/sizeof(struct r600_reg);
+
+ for (int i = 0; i < nreg; i++) {
+ r600_shader_resource[i].offset += offset;
+ }
+ return r600_context_add_block(ctx, r600_shader_resource, nreg);
+}
+
+/* SHADER SAMPLER R600/R700 */
+static int r600_state_sampler_init(struct r600_context *ctx, u32 offset)
+{
+ struct r600_reg r600_shader_sampler[] = {
+ {0, 0, R_03C000_SQ_TEX_SAMPLER_WORD0_0},
+ {0, 0, R_03C004_SQ_TEX_SAMPLER_WORD1_0},
+ {0, 0, R_03C008_SQ_TEX_SAMPLER_WORD2_0},
+ };
+ unsigned nreg = sizeof(r600_shader_sampler)/sizeof(struct r600_reg);
+
+ for (int i = 0; i < nreg; i++) {
+ r600_shader_sampler[i].offset += offset;
+ }
+ return r600_context_add_block(ctx, r600_shader_sampler, nreg);
+}
+
+int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon)
+{
+ int r;
+
+ memset(ctx, 0, sizeof(struct r600_context));
+ ctx->radeon = radeon;
+ LIST_INITHEAD(&ctx->query_list);
+ /* initialize groups */
+ r = r600_group_init(&ctx->groups[EVERGREEN_GROUP_CONFIG], EVERGREEN_CONFIG_REG_OFFSET, EVERGREEN_CONFIG_REG_END);
+ if (r) {
+ goto out_err;
+ }
+ r = r600_group_init(&ctx->groups[EVERGREEN_GROUP_LOOP_CONST], EVERGREEN_LOOP_CONST_OFFSET, EVERGREEN_LOOP_CONST_END);
+ if (r) {
+ goto out_err;
+ }
+ r = r600_group_init(&ctx->groups[EVERGREEN_GROUP_BOOL_CONST], EVERGREEN_BOOL_CONST_OFFSET, EVERGREEN_BOOL_CONST_END);
+ if (r) {
+ goto out_err;
+ }
+ r = r600_group_init(&ctx->groups[EVERGREEN_GROUP_SAMPLER], EVERGREEN_SAMPLER_OFFSET, EVERGREEN_SAMPLER_END);
+ if (r) {
+ goto out_err;
+ }
+ r = r600_group_init(&ctx->groups[EVERGREEN_GROUP_RESOURCE], EVERGREEN_RESOURCE_OFFSET, EVERGREEN_RESOURCE_END);
+ if (r) {
+ goto out_err;
+ }
+ r = r600_group_init(&ctx->groups[EVERGREEN_GROUP_CONTEXT], EVERGREEN_CONTEXT_REG_OFFSET, EVERGREEN_CONTEXT_REG_END);
+ if (r) {
+ goto out_err;
+ }
+ ctx->ngroups = EVERGREEN_NGROUPS;
+
+ /* add blocks */
+ r = r600_context_add_block(ctx, evergreen_reg_list, sizeof(evergreen_reg_list)/sizeof(struct r600_reg));
+ if (r)
+ goto out_err;
+
+ /* PS SAMPLER */
+ for (int j = 0, offset = 0; j < 18; j++, offset += 0xC) {
+ r = r600_state_sampler_init(ctx, offset);
+ if (r)
+ goto out_err;
+ }
+ /* VS SAMPLER */
+ for (int j = 0, offset = 0xD8; j < 18; j++, offset += 0xC) {
+ r = r600_state_sampler_init(ctx, offset);
+ if (r)
+ goto out_err;
+ }
+ /* PS RESOURCE */
+ for (int j = 0, offset = 0; j < 176; j++, offset += 0x1C) {
+ r = evergreen_state_resource_init(ctx, offset);
+ if (r)
+ goto out_err;
+ }
+ /* VS RESOURCE */
+ for (int j = 0, offset = 0x1600; j < 176; j++, offset += 0x1C) {
+ r = evergreen_state_resource_init(ctx, offset);
+ if (r)
+ goto out_err;
+ }
+
+ /* allocate cs variables */
+ ctx->nreloc = RADEON_CTX_MAX_PM4;
+ ctx->reloc = calloc(ctx->nreloc, sizeof(struct r600_reloc));
+ if (ctx->reloc == NULL) {
+ r = -ENOMEM;
+ goto out_err;
+ }
+ ctx->bo = calloc(ctx->nreloc, sizeof(void *));
+ if (ctx->bo == NULL) {
+ r = -ENOMEM;
+ goto out_err;
+ }
+ ctx->pm4_ndwords = RADEON_CTX_MAX_PM4;
+ ctx->pm4 = calloc(ctx->pm4_ndwords, 4);
+ if (ctx->pm4 == NULL) {
+ r = -ENOMEM;
+ goto out_err;
+ }
+ return 0;
+out_err:
+ r600_context_fini(ctx);
+ return r;
+}
+
+void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *draw)
+{
+ struct radeon_bo *cb[12];
+ unsigned ndwords = 9;
+
+ if (draw->indices) {
+ ndwords = 13;
+ /* make sure there is enough relocation space before scheduling draw */
+ if (ctx->creloc >= (ctx->nreloc - 1)) {
+ r600_context_flush(ctx);
+ }
+ }
+
+ /* find number of color buffer */
+ cb[0] = r600_context_reg_bo(ctx, EVERGREEN_GROUP_CONTEXT, R_028C60_CB_COLOR0_BASE);
+ cb[1] = r600_context_reg_bo(ctx, EVERGREEN_GROUP_CONTEXT, R_028C9C_CB_COLOR1_BASE);
+ cb[2] = r600_context_reg_bo(ctx, EVERGREEN_GROUP_CONTEXT, R_028CD8_CB_COLOR2_BASE);
+ cb[3] = r600_context_reg_bo(ctx, EVERGREEN_GROUP_CONTEXT, R_028D14_CB_COLOR3_BASE);
+ cb[4] = r600_context_reg_bo(ctx, EVERGREEN_GROUP_CONTEXT, R_028D50_CB_COLOR4_BASE);
+ cb[5] = r600_context_reg_bo(ctx, EVERGREEN_GROUP_CONTEXT, R_028D8C_CB_COLOR5_BASE);
+ cb[6] = r600_context_reg_bo(ctx, EVERGREEN_GROUP_CONTEXT, R_028DC8_CB_COLOR6_BASE);
+ cb[7] = r600_context_reg_bo(ctx, EVERGREEN_GROUP_CONTEXT, R_028E04_CB_COLOR7_BASE);
+ cb[8] = r600_context_reg_bo(ctx, EVERGREEN_GROUP_CONTEXT, R_028E40_CB_COLOR8_BASE);
+ cb[9] = r600_context_reg_bo(ctx, EVERGREEN_GROUP_CONTEXT, R_028E5C_CB_COLOR9_BASE);
+ cb[10] = r600_context_reg_bo(ctx, EVERGREEN_GROUP_CONTEXT, R_028E78_CB_COLOR10_BASE);
+ cb[11] = r600_context_reg_bo(ctx, EVERGREEN_GROUP_CONTEXT, R_028E94_CB_COLOR11_BASE);
+ for (int i = 0; i < 12; i++) {
+ if (cb[i]) {
+ ndwords += 7;
+ }
+ }
+
+ if ((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) {
+ /* need to flush */
+ r600_context_flush(ctx);
+ }
+ /* at that point everythings is flushed and ctx->pm4_cdwords = 0 */
+ if ((ctx->pm4_dirty_cdwords + ndwords) > ctx->pm4_ndwords) {
+ R600_ERR("context is too big to be scheduled\n");
+ return;
+ }
+
+ /* enough room to copy packet */
+ r600_context_group_emit_dirty(ctx, &ctx->groups[EVERGREEN_GROUP_CONFIG], PKT3_SET_CONFIG_REG);
+ r600_context_group_emit_dirty(ctx, &ctx->groups[EVERGREEN_GROUP_CONTEXT], PKT3_SET_CONTEXT_REG);
+ r600_context_group_emit_dirty(ctx, &ctx->groups[EVERGREEN_GROUP_RESOURCE], PKT3_SET_RESOURCE);
+ r600_context_group_emit_dirty(ctx, &ctx->groups[EVERGREEN_GROUP_SAMPLER], PKT3_SET_SAMPLER);
+
+ /* draw packet */
+ ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_INDEX_TYPE, 0);
+ ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_index_type;
+ ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NUM_INSTANCES, 0);
+ ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_instances;
+ if (draw->indices) {
+ ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_DRAW_INDEX, 3);
+ ctx->pm4[ctx->pm4_cdwords++] = draw->indices_bo_offset;
+ ctx->pm4[ctx->pm4_cdwords++] = 0;
+ ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_indices;
+ ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_draw_initiator;
+ ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0);
+ ctx->pm4[ctx->pm4_cdwords++] = 0;
+ r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], radeon_bo_pb_get_bo(draw->indices->pb));
+ } else {
+ ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1);
+ ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_indices;
+ ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_draw_initiator;
+ }
+ ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0);
+ ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT;
+
+ /* flush color buffer */
+ for (int i = 0; i < 8; i++) {
+ if (cb[i]) {
+ ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3);
+ ctx->pm4[ctx->pm4_cdwords++] = (S_0085F0_CB0_DEST_BASE_ENA(1) << i) |
+ S_0085F0_CB_ACTION_ENA(1);
+ ctx->pm4[ctx->pm4_cdwords++] = (cb[i]->size + 255) >> 8;
+ ctx->pm4[ctx->pm4_cdwords++] = 0x00000000;
+ ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A;
+ ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0);
+ ctx->pm4[ctx->pm4_cdwords++] = 0;
+ r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], cb[i]);
+ }
+ }
+
+ /* all dirty state have been scheduled in current cs */
+ ctx->pm4_dirty_cdwords = 0;
+}
+
+static inline void evergreen_resource_set(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
+{
+ struct r600_group_block *block;
+ unsigned id;
+
+ offset -= ctx->groups[EVERGREEN_GROUP_RESOURCE].start_offset;
+ id = ctx->groups[EVERGREEN_GROUP_RESOURCE].offset_block_id[offset >> 2];
+ block = &ctx->groups[EVERGREEN_GROUP_RESOURCE].blocks[id];
+ block->pm4[0] = state->regs[0].value;
+ block->pm4[1] = state->regs[1].value;
+ block->pm4[2] = state->regs[2].value;
+ block->pm4[3] = state->regs[3].value;
+ block->pm4[4] = state->regs[4].value;
+ block->pm4[5] = state->regs[5].value;
+ block->pm4[6] = state->regs[6].value;
+ block->pm4[7] = state->regs[7].value;
+ radeon_ws_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL);
+ radeon_ws_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL);
+ if (state->regs[0].bo) {
+ /* VERTEX RESOURCE, we preted there is 2 bo to relocate so
+ * we have single case btw VERTEX & TEXTURE resource
+ */
+ radeon_ws_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[0].bo);
+ radeon_ws_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[0].bo);
+ } else {
+ /* TEXTURE RESOURCE */
+ radeon_ws_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[2].bo);
+ radeon_ws_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[3].bo);
+ }
+ block->status |= R600_BLOCK_STATUS_ENABLED;
+ block->status |= R600_BLOCK_STATUS_DIRTY;
+ ctx->pm4_dirty_cdwords += 2 + block->pm4_ndwords;
+}
+
+void evergreen_ps_resource_set(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
+{
+ unsigned offset = R_030000_RESOURCE0_WORD0 + 0x20 * rid;
+
+ evergreen_resource_set(ctx, state, offset);
+}
+
+void evergreen_vs_resource_set(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
+{
+ unsigned offset = R_030000_RESOURCE0_WORD0 + 0x1600 + 0x20 * rid;
+
+ evergreen_resource_set(ctx, state, offset);
+}
#include "util/u_inlines.h"
#include <pipebuffer/pb_bufmgr.h>
+#define GROUP_FORCE_NEW_BLOCK 0
struct radeon_ws_bo {
struct pipe_reference reference;
struct pb_buffer *pb;
return -1;
}
-static int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg)
+int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg)
{
struct r600_group_block *block, *tmp;
struct r600_group *group;
for (unsigned i = 0, n = 0; i < nreg; i += n) {
u32 j, r;
- /* find number of consecutive registers */
- for (j = i + 1, r = reg[i].offset + 4, n = 1; j < (nreg - i); j++, n++, r+=4) {
- if (r != reg[j].offset) {
- break;
+
+ /* register that need relocation are in their own group */
+ n = 1;
+ if (!reg[i].need_bo) {
+ /* find number of consecutive registers */
+ for (j = i + 1, r = reg[i].offset + 4, n = 1; j < (nreg - i); j++, n++, r+=4) {
+ if (reg[i].need_bo || r != reg[j].offset) {
+ break;
+ }
}
}
+ /* ignore new block balise */
+ if (reg[i].offset == GROUP_FORCE_NEW_BLOCK)
+ continue;
+
/* find into which group this block is */
group_id = r600_group_id_register_offset(reg[i].offset);
assert(group_id >= 0);
return 0;
}
-static int r600_group_init(struct r600_group *group, unsigned start_offset, unsigned end_offset)
+int r600_group_init(struct r600_group *group, unsigned start_offset, unsigned end_offset)
{
group->start_offset = start_offset;
group->end_offset = end_offset;
return r;
}
-static void r600_context_bo_reloc(struct r600_context *ctx, u32 *pm4, struct radeon_bo *bo)
+void r600_context_bo_reloc(struct r600_context *ctx, u32 *pm4, struct radeon_bo *bo)
{
int i, reloc_id;
block->pm4[4] = state->regs[4].value;
block->pm4[5] = state->regs[5].value;
block->pm4[6] = state->regs[6].value;
- radeon_ws_bo_reference(ctx->radeon, &block->reloc[1].bo, block->reloc[1].bo);
- radeon_ws_bo_reference(ctx->radeon , &block->reloc[2].bo, block->reloc[2].bo);
+ radeon_ws_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL);
+ radeon_ws_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL);
if (state->regs[0].bo) {
/* VERTEX RESOURCE, we preted there is 2 bo to relocate so
* we have single case btw VERTEX & TEXTURE resource
}
}
-static inline void r600_context_group_emit_dirty(struct r600_context *ctx, struct r600_group *group, unsigned opcode)
+void r600_context_group_emit_dirty(struct r600_context *ctx, struct r600_group *group, unsigned opcode)
{
struct radeon_bo *bo;
int id;
}
}
-static struct radeon_bo *r600_context_reg_bo(struct r600_context *ctx, unsigned group_id, unsigned offset)
+struct radeon_bo *r600_context_reg_bo(struct r600_context *ctx, unsigned group_id, unsigned offset)
{
struct r600_group_block *block;
unsigned id;
projects / mesa.git / commitdiff