comment out reset signal for iverilog simulation

diff --git a/src/simsoctb.v b/src/simsoctb.v
index 64fb39a1bf02f772acb8846c487cba04a4e78d16..da3b2e0008ba2d3b80559bcbf794f5856da558ad 100644 (file)
--- a/src/simsoctb.v
+++ b/src/simsoctb.v
@@ -90,7 +90,7 @@ module simsoctb;
   //defparam ram_chip.
   
   top simsoctop (
-    .ddr3_0__rst__io(dram_rst),
+     //FIXME .ddr3_0__rst__io(dram_rst),
     .ddr3_0__dq__io(dram_dq),
     .ddr3_0__dqs__p(dram_dqs),
     .ddr3_0__clk__p(dram_ck),