fetch instructions from bare wishbone fetch unit

diff --git a/src/soc/bus/test/test_minerva.py b/src/soc/bus/test/test_minerva.py
index 01c00b25f4dae6604377c5be602b480c63fe923d..c2bc0d4f1f95c5e30414f6d3f949340af93377e3 100644 (file)
--- a/src/soc/bus/test/test_minerva.py
+++ b/src/soc/bus/test/test_minerva.py
@@ -1,6 +1,7 @@
 from nmigen_soc.wishbone.sram import SRAM
 from nmigen import Memory, Signal, Module
 from soc.minerva.units.loadstore import BareLoadStoreUnit, CachedLoadStoreUnit
+from soc.minerva.units.fetch import BareFetchUnit, CachedFetchUnit
 
 
 class TestSRAMBareLoadStoreUnit(BareLoadStoreUnit):
@@ -31,3 +32,36 @@ class TestSRAMBareLoadStoreUnit(BareLoadStoreUnit):
         comb += sram.bus.adr.eq(dbus.adr)
 
         return m
+
+
+class TestSRAMBareFetchUnit(BareFetchUnit):
+    def __init__(self, addr_wid=64, data_wid=64):
+        super().__init__(addr_wid, data_wid)
+        # small 16-entry Memory
+        self.mem = Memory(width=self.data_wid, depth=32)
+
+    def _get_memory(self):
+        return self.mem
+
+    def elaborate(self, platform):
+        m = super().elaborate(platform)
+        comb = m.d.comb
+        m.submodules.sram = sram = SRAM(memory=self.mem, read_only=True,
+                                        features={'cti', 'bte', 'err'})
+        ibus = self.ibus
+
+        # directly connect the wishbone bus of FetchUnitInterface to SRAM
+        # note: SRAM is a target (slave), ibus is initiator (master)
+        fanouts = ['dat_w', 'sel', 'cyc', 'stb', 'we', 'cti', 'bte']
+        fanins = ['dat_r', 'ack', 'err']
+        for fanout in fanouts:
+            print ("fanout", fanout, getattr(sram.bus, fanout).shape(),
+                                     getattr(ibus, fanout).shape())
+            comb += getattr(sram.bus, fanout).eq(getattr(ibus, fanout))
+            comb += getattr(sram.bus, fanout).eq(getattr(ibus, fanout))
+        for fanin in fanins:
+            comb += getattr(ibus, fanin).eq(getattr(sram.bus, fanin))
+        # connect address
+        comb += sram.bus.adr.eq(ibus.adr)
+
+        return m

diff --git a/src/soc/config/ifetch.py b/src/soc/config/ifetch.py
index 0aea4565772fc177cbb807511220489e13cf5bf1..f558d7792c5b9ff9432f9f4c6c358da47f5e0e26 100644 (file)
--- a/src/soc/config/ifetch.py
+++ b/src/soc/config/ifetch.py
@@ -7,13 +7,13 @@ as well as larger ones and so on, without needing large amounts
 of unnecessarily-duplicated code
 """
 from soc.experiment.imem import TestMemFetchUnit
-#from soc.bus.test.test_minerva import TestSRAMBareFetchUnit
+from soc.bus.test.test_minerva import TestSRAMBareFetchUnit
 
 
 class ConfigFetchUnit:
     def __init__(self, pspec):
         fudict = {'testmem': TestMemFetchUnit,
-                   #'test_bare_wb': TestSRAMBareFetchUnit,
+                   'test_bare_wb': TestSRAMBareFetchUnit,
                    #'test_cache_wb': TestCacheFetchUnit
                   }
         fukls = fudict[pspec.imem_ifacetype]

diff --git a/src/soc/config/test/test_fetch.py b/src/soc/config/test/test_fetch.py
index e772eb8c6163871e09b801a4cbd9e55fa5dcab37..00154dfde5ed2b49e9a32b56db5b02edcc9e05eb 100644 (file)
--- a/src/soc/config/test/test_fetch.py
+++ b/src/soc/config/test/test_fetch.py
@@ -13,6 +13,7 @@ from soc.config.test.test_loadstore import TestMemPspec
 def read_from_addr(dut, addr):
     yield dut.a_pc_i.eq(addr)
     yield dut.a_valid_i.eq(1)
+    yield dut.f_valid_i.eq(1)
     yield dut.a_stall_i.eq(1)
     yield
     yield dut.a_stall_i.eq(0)
@@ -20,8 +21,12 @@ def read_from_addr(dut, addr):
     yield Settle()
     while (yield dut.f_busy_o):
         yield
-    assert (yield dut.a_valid_i)
-    return (yield dut.f_instr_o)
+    res = (yield dut.f_instr_o)
+
+    yield dut.a_valid_i.eq(0)
+    yield dut.f_valid_i.eq(0)
+    yield
+    return res
 
 
 def tst_lsmemtype(ifacetype):
@@ -40,13 +45,14 @@ def tst_lsmemtype(ifacetype):
     sim = Simulator(m)
     sim.add_clock(1e-6)
 
-    mem = dut.mem.mem
+    mem = dut._get_memory()
 
     def process():
 
         values = [random.randint(0, (1<<32)-1) for x in range(16)]
         for addr, val in enumerate(values):
             yield mem._array[addr].eq(val)
+        yield Settle()
 
         for addr, val in enumerate(values):
             x = yield from read_from_addr(dut, addr << 2)
@@ -58,5 +64,5 @@ def tst_lsmemtype(ifacetype):
         sim.run()
 
 if __name__ == '__main__':
-    #tst_lsmemtype('test_bare_wb')
+    tst_lsmemtype('test_bare_wb')
     tst_lsmemtype('testmem')

diff --git a/src/soc/experiment/imem.py b/src/soc/experiment/imem.py
index 17c5b1ebcb751fc9acdbf567eb3b3110441d3104..068a040869dfdaf1b3ded7c1180de9adebb69b48 100644 (file)
--- a/src/soc/experiment/imem.py
+++ b/src/soc/experiment/imem.py
@@ -12,6 +12,9 @@ class TestMemFetchUnit(FetchUnitInterface, Elaboratable):
         # limit TestMemory to 2^6 entries of regwid size
         self.mem = TestMemory(self.data_wid, 6, readonly=True)
 
+    def _get_memory(self):
+        return self.mem.mem
+
     def elaborate(self, platform):
         m = Module()
         regwid, addrwid = self.data_wid, self.addr_wid

diff --git a/src/soc/minerva/units/fetch.py b/src/soc/minerva/units/fetch.py
index 023f8909511a1a6d5b655fe20a693d20de25b9df..246f3dda15c80760564075b1b75b4cefe8b7f583 100644 (file)
--- a/src/soc/minerva/units/fetch.py
+++ b/src/soc/minerva/units/fetch.py
@@ -112,7 +112,7 @@ class CachedFetchUnit(FetchUnitInterface, Elaboratable):
         m.d.comb += iba.bus.connect(self.ibus)
 
         icache_port = iba.port(priority=0)
-        cti = Mux(icache.bus_last, Cycle.END, Cycle.INCREMENT
+        cti = Mux(icache.bus_last, Cycle.END, Cycle.INCREMENT)
         m.d.comb += [
             icache_port.cyc.eq(icache.bus_re),
             icache_port.stb.eq(icache.bus_re),

diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py
index 48c802ec5fb24c26362d10a70f45cd0fa36fb561..14a23a8cc51fbdcba758c402937b6a8f6eceb9ca 100644 (file)
--- a/src/soc/simple/test/test_issuer.py
+++ b/src/soc/simple/test/test_issuer.py
@@ -66,8 +66,9 @@ class TestRunner(FHDLTestCase):
         go_insn_i = Signal()
         pc_i = Signal(32)
 
-        m.submodules.issuer = issuer = TestIssuer(ifacetype="test_bare_wb")
-        imem = issuer.imem.mem.mem
+        m.submodules.issuer = issuer = TestIssuer(ifacetype="test_bare_wb",
+                                                  imemtype="test_bare_wb")
+        imem = issuer.imem._get_memory()
         core = issuer.core
         pdecode2 = core.pdecode2
         l0 = core.l0