Only add assert statement if DEBUG generic is true.

Default value is false.

diff --git a/rtl/vhdl/c4m_jtag_pkg.vhdl b/rtl/vhdl/c4m_jtag_pkg.vhdl
index d25f2ae7b814f6a7bca2a4bf3dc8b3beb7b5fd01..0fc07490762d753276457d4e660450671f5ef681 100644 (file)
--- a/rtl/vhdl/c4m_jtag_pkg.vhdl
+++ b/rtl/vhdl/c4m_jtag_pkg.vhdl
@@ -148,6 +148,8 @@ package c4m_jtag is
 
   component c4m_jtag_tap_controller is
     generic (
+      DEBUG:            boolean := false;
+
       IR_WIDTH:         integer := 2;
       IOS:              integer := 1;
 

diff --git a/rtl/vhdl/c4m_jtag_tap_controller.vhdl b/rtl/vhdl/c4m_jtag_tap_controller.vhdl
index 35c7f52eda54308b74ce84756222f451bbbfb103..217982e80ec237e074eb2bf90c08fa9d48f9e47f 100644 (file)
--- a/rtl/vhdl/c4m_jtag_tap_controller.vhdl
+++ b/rtl/vhdl/c4m_jtag_tap_controller.vhdl
@@ -8,6 +8,8 @@ use work.c4m_jtag.ALL;
 
 entity c4m_jtag_tap_controller is
   generic (
+    DEBUG:              boolean := false;
+
     IR_WIDTH:           integer := 2;
     IOS:                integer := 1;
 
@@ -57,7 +59,6 @@ architecture rtl of c4m_jtag_tap_controller is
   signal ID_TDO_EN:     std_logic;
   signal IO_TDO:        std_logic;
   signal IO_TDO_EN:     std_logic;
-  signal EN:            std_logic_vector(2 downto 0) := "000";
 begin
   IR <= S_IR;
 
@@ -140,10 +141,14 @@ begin
          IO_TDO when IO_TDO_EN = '1' else
          '0';
 
-  EN <= IR_TDO_EN & ID_TDO_EN & IO_TDO_EN;
-  assert EN = "000" or EN = "100" or EN = "010" or EN = "001"
-    report "TDO conflict in c4m_jtag_tap_controller"
-    severity ERROR;
+  CHECK_EN: if DEBUG generate
+    signal EN:  std_logic_vector(2 downto 0) := "000";
+  begin
+    EN <= IR_TDO_EN & ID_TDO_EN & IO_TDO_EN;
+    assert EN = "000" or EN = "100" or EN = "010" or EN = "001"
+      report "TDO conflict in c4m_jtag_tap_controller"
+      severity ERROR;
+  end generate CHECK_EN;
 end rtl;