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[riscv-tests.git]
/
debug
/
targets
/
SiFive
/
2018-09-13
Tim Newsome
Assert if HiFive1 program is too large.
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commitdiff
2018-04-27
Megan Wachs
Merge pull request #125 from riscv/debug-delete-sim
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commitdiff
2018-04-19
Megan Wachs
Delete E300Sim.py
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commitdiff
2018-04-02
Tim Newsome
Use `gdb_report_register_access_error enable`
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commitdiff
2018-03-01
Tim Newsome
Ensure an error when reading a non-existent CSR.
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commitdiff
2018-02-07
Tim Newsome
Link scripts shouldn't be executable.
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commitdiff
2017-09-12
Tim Newsome
Merge pull request #69 from riscv/multicore
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commitdiff
2017-08-28
Tim Newsome
Make pylint happy.
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commitdiff
2017-08-28
Tim Newsome
WIP multicore testing.
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commitdiff
2017-08-28
Tim Newsome
Make the debug tests aware of multicore.
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commitdiff
2017-08-10
Tim Newsome
Give these sim targets a chance of passing.
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commitdiff
2017-06-27
Tim Newsome
Merge pull request #55 from riscv/debug
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commitdiff
2017-06-27
Tim Newsome
Merge pull request #56 from riscv/config
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commitdiff
2017-06-26
Tim Newsome
Move target definition into individual files.
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