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add sv.stwu/pi example in test_sv_load_store_postinc
[openpower-isa.git]
/
openpower
/
isa
/
svfixedarith.mdwn
2022-09-29
Jacob Lifshay
rename madded->maddedu for consistency with PowerISA...
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2022-09-29
Jacob Lifshay
rename divrem2du->divmod2du for consistency with PowerI...
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2022-09-29
Jacob Lifshay
add bigint tests and fix madded pseudocode
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2022-09-29
Jacob Lifshay
fill out dsld/dsrd pseudocode
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2022-09-29
Jacob Lifshay
clean up bigint instruction naming
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2022-09-28
Luke Kenneth Casso...
new revision of dsld
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2022-09-28
Luke Kenneth Casso...
add double-sld pseudocode, first draft
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2022-05-03
Luke Kenneth Casso...
code-comments on madded and divmod2du should say RS...
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2022-05-03
Luke Kenneth Casso...
properly fix pagereader.py to parse markdown with inden...
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2022-05-03
Jacob Lifshay
fix syntax error
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2022-04-29
Luke Kenneth Casso...
higher bits need to be checked for overflow not lower
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2022-04-29
Luke Kenneth Casso...
invert RC and RA, making divmod2du more like divdu
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2022-04-27
Luke Kenneth Casso...
accidentally added svfixedarith.mdwn to wiki rather...
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