use widths.get(dw/sw) and test empty/non-empty after.
[openpower-isa.git] / openpower / isa /
2022-09-18 Luke Kenneth Casso... add new svstep mode setting up pack/unpack
2022-09-15 Luke Kenneth Casso... fix sprset mtspr/mfspr pseudocode with wrong definition of
2022-09-12 Jacob Lifshayadd pseudocode for all fptrans ops
2022-09-12 Jacob Lifshayadd fptrans helpers, switching existing uses to new...
2022-09-12 Luke Kenneth Casso... split out setvl from sv.setvl test in test_pysvp64dis.py
2022-09-08 Luke Kenneth Casso... rename svshape and svoffset fields
2022-09-08 Dmitry Selyutinsvshape2: rename fields
2022-09-06 Luke Kenneth Casso... add first functional confirmed unit test for parallel...
2022-09-06 Luke Kenneth Casso... REMAP parallel-reduce:
2022-09-06 Luke Kenneth Casso... add dummy fixedsync.mdwn pseudocode for lwarx/stbcx...
2022-09-04 Dmitry SelyutinRevert "target_addr in b and bc pseudo-code has no...
2022-09-04 Dmitry SelyutinRevert "svbranch.mdwn: replace target_addr with BD"
2022-09-03 Luke Kenneth Casso... Revert "add inv option to svshape2 (only 1 bit)"
2022-09-03 Luke Kenneth Casso... add inv option to svshape2 (only 1 bit)
2022-09-02 Luke Kenneth Casso... add first svshape2 pseudocode, based on svindex
2022-09-02 Luke Kenneth Casso... add svshape2 (stub pseudocode) fields, Form, and CSV...
2022-09-01 Luke Kenneth Casso... ghostmansd found that extswsli is incorrectly declared
2022-09-01 Dmitry Selyutinsvbranch.mdwn: replace target_addr with BD
2022-09-01 Jacob Lifshaymove fsins/fcoss to fptrans.mdwn -- they are transcende...
2022-08-31 Luke Kenneth Casso... target_addr in b and bc pseudo-code has no corresponding
2022-08-30 Dmitry Selyutinbcd.mdwn: fix cbcdtd operands
2022-08-30 Dmitry Selyutinbcd.mdwn: fix cdtbcd operands
2022-08-30 Dmitry Selyutinfixedlogical.mdwn: fix bpermd operands
2022-08-30 Luke Kenneth Casso... remove space from arguments in popcnt, should not have...
2022-08-30 Luke Kenneth Casso... correct the bitmanip pseudocode to remove spaces from...
2022-08-26 Luke Kenneth Casso... initialise overflow to zero in setvl, unconditionally.
2022-08-26 Luke Kenneth Casso... sigh, update setvl tests, to spec, and ISACaller
2022-08-26 Luke Kenneth Casso... add setvl unit tests for overflow condition.
2022-08-26 Luke Kenneth Casso... put back overflow in setvl, TODO actually set an overfl...
2022-08-26 Luke Kenneth Casso... okaaaay, long story. using GPR(_RT) <- something will...
2022-08-26 Luke Kenneth Casso... Revert "fix setvl. not setting CR0 properly"
2022-08-26 Jacob Lifshayfix setvl. not setting CR0 properly
2022-08-12 Luke Kenneth Casso... remive svfixedload.mdwn. requires scalar fixed load...
2022-08-12 Luke Kenneth Casso... remove use of sv ld shifted, replace with els, deprecat...
2022-07-27 Jacob Lifshayadd another test and fix broken fishmv pseudocode
2022-07-27 Konstantinos Marga... Add fishmv instruction (bug #887)
2022-07-26 Luke Kenneth Casso... use DOUBLE helper function in fmvis
2022-07-26 Konstantinos Marga... fix form and pseudo-code for fmvis, tests in 64-bit...
2022-07-26 Luke Kenneth Casso... whitespace cleanup
2022-07-26 Konstantinos Marga... fix fmvis decoder, it's now a 2-operand instruction
2022-07-26 Konstantinos Marga... Add fmvis instruction + tests, bug #887
2022-07-11 Luke Kenneth Casso... add mm=1 svindex test, setting single targetted SVSHAPE
2022-07-11 Luke Kenneth Casso... compute 2nd svindex dimension using unsignee compare
2022-07-10 Luke Kenneth Casso... add yx svindex test, needed to compute size of 2nd dim
2022-07-10 Luke Kenneth Casso... fix svindex pseudocode, set large 2nd dim on nonskip
2022-07-10 Luke Kenneth Casso... fix svindex unit test, experiment setting dimensions
2022-07-10 Luke Kenneth Casso... fix svindex pseudocode
2022-07-09 Luke Kenneth Casso... add storing of shape in requested SVSHAPE in svindex...
2022-07-06 Luke Kenneth Casso... add first stub of svindex pseudocode
2022-07-02 Luke Kenneth Casso... add setvl CTR tests, fix CTR mode
2022-07-02 Luke Kenneth Casso... fix setvl CTR mode
2022-07-02 Luke Kenneth Casso... setvl has new CTR mode, making room in encoding needed
2022-06-26 Luke Kenneth Casso... rename SVRM *field* to SVrm to avoid a name-clash with
2022-06-25 Luke Kenneth Casso... correct undefined in av.mdwn bmask
2022-06-24 Luke Kenneth Casso... invert mode-bits in bmask bm field
2022-06-24 Luke Kenneth Casso... sigh, bm not mode argument to bmask
2022-06-23 Luke Kenneth Casso... else must be on separate line in pseudocode av.mdwn
2022-06-23 Luke Kenneth Casso... missing "Special Registers Altered" on av.mdwn
2022-06-23 Andrey MiroshnikovAdded bmask, pywriter failing
2022-06-22 Andrey MiroshnikovModified cprop pseudo-code due to parser bug
2022-06-22 Andrey MiroshnikovAdded entries for cprop, not sure if correct
2022-06-20 Luke Kenneth Casso... add absolute-signed-diff next to absolute-unsigned...
2022-06-20 Luke Kenneth Casso... rename absadd[us] to absdac[ud]
2022-06-19 Jacob Lifshayfix minu[.] to be unsigned
2022-06-19 Luke Kenneth Casso... add absadds - signed accumulating add. DRAFT
2022-06-19 Luke Kenneth Casso... add absadd (unsigned) DRAFT
2022-06-19 Luke Kenneth Casso... add absolute-difference DRAFT
2022-06-19 Luke Kenneth Casso... add average-add DRAFT pseudocode and CSV
2022-06-19 Luke Kenneth Casso... add the rest of min/max DRAFT av opcodes
2022-06-19 Luke Kenneth Casso... add maxs DRAFT instruction
2022-05-14 Luke Kenneth Casso... cut/paste error resulted in Rc=0 twice, should be Rc=1
2022-05-14 Luke Kenneth Casso... cut/paste error resulted in Rc=0 twice, should be Rc=1
2022-05-12 Luke Kenneth Casso... add "DRAFT" in front of svfparith instruction descriptions
2022-05-03 Luke Kenneth Casso... code-comments on madded and divmod2du should say RS...
2022-05-03 Luke Kenneth Casso... properly fix pagereader.py to parse markdown with inden...
2022-05-03 Jacob Lifshayadd Rc to ternlogi
2022-05-03 Jacob Lifshayfix syntax error
2022-04-29 Luke Kenneth Casso... higher bits need to be checked for overflow not lower
2022-04-29 Luke Kenneth Casso... invert RC and RA, making divmod2du more like divdu
2022-04-27 Luke Kenneth Casso... accidentally added svfixedarith.mdwn to wiki rather...
2022-01-18 Jacob Lifshaygrev[w][i][.] pseudo-code works
2022-01-14 Jacob Lifshayremove stray newline
2022-01-14 Jacob Lifshayadd grev[w][i][.] pseudo-code
2021-12-11 Luke Kenneth Casso... remove ROTL64(1, idx), just use TLI[7-idx] it is shorte...
2021-12-11 Luke Kenneth Casso... use concat in ternlogi to reduce code size
2021-12-10 Jacob Lifshaychange ternlogi to not have Rc field
2021-12-09 Jacob Lifshayadd initial ternlogi pseudo-code
2021-10-13 Dmitry Selyutinfixedlogical: simplify extsw
2021-10-13 Dmitry Selyutinfixedlogical: simplify extsh
2021-10-13 Dmitry Selyutinfixedlogical: simplify extsb
2021-09-29 Dmitry Selyutinfixedlogical: switch xoris to XCASTU
2021-09-29 Dmitry Selyutinfixedlogical: switch oris to XCASTU
2021-09-29 Dmitry Selyutinfixedlogical: switch andis. to XCASTU
2021-09-29 Dmitry Selyutinfixedlogical: switch xori to XCASTU
2021-09-29 Dmitry Selyutinfixedlogical: switch ori to XCASTU
2021-09-29 Dmitry Selyutinfixedlogical: switch andi. to XLCASTU
2021-09-07 Dmitry Selyutinfixedtrap: switch tw to XLEN
2021-09-07 Dmitry Selyutinfixedtrap: switch twi to XLEN
2021-09-07 Jacob LifshayXLEN-ify bcd instructions
2021-09-04 Dmitry Selyutincomparefixed: switch cmpeqb to XLEN
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