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add .gitignore to ignore the generated vhdl
[openpower-isa.git]
/
openpower
/
isatables
/
RM-1P-3S1D.csv
2021-11-17
Jacob Lifshay
rename ternary->ternlog and associated form/field TI...
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2021-11-12
Jacob Lifshay
change ternaryi to correct register fields
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2021-07-23
Luke Kenneth Casso...
add sv.fdmadds unit test
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2021-06-27
Luke Kenneth Casso...
add new (experimental) ffmadds and ffmsubs, for FFT...
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2021-06-25
Luke Kenneth Casso...
update sv_analysis.py to match new CONDITIONs field...
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2021-06-15
Luke Kenneth Casso...
fix sv_analysis.py for 3R-1W-CRo case, add fmadds/fmsub...
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2021-05-18
Luke Kenneth Casso...
add beginning support for SVP64 IEEE754 FP
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2021-04-23
Luke Kenneth Casso...
add isatables extracted from microwatt and v3.0B spec
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