git.libre-soc.org Git - openpower-isa.git/history - openpower/isatables/RM-2P-1S1D.csv

2022-07-27	Jacob Lifshay	add another test and fix broken fishmv pseudocode	blob \| commitdiff \| raw
2022-07-26	Luke Kenneth Casso...	add example fmvis instruction to trans/svp64.py	blob \| commitdiff \| raw \| diff to current
2022-07-26	Konstantinos Marga...	Add fmvis instruction + tests, bug #887	blob \| commitdiff \| raw \| diff to current
2022-05-02	Luke Kenneth Casso...	re-run sv_analysis to add mode field to csvs	blob \| commitdiff \| raw \| diff to current
2022-01-06	Jacob Lifshay	add grev[w][i] instructions	blob \| commitdiff \| raw \| diff to current
2021-08-08	Luke Kenneth Casso...	add bc and bclr to sv_analysis	blob \| commitdiff \| raw \| diff to current
2021-08-01	Luke Kenneth Casso...	add BCD operations to SVP64	blob \| commitdiff \| raw \| diff to current
2021-07-16	Luke Kenneth Casso...	add fsins and fcoss to simulator	blob \| commitdiff \| raw \| diff to current
2021-06-25	Luke Kenneth Casso...	update sv_analysis.py to match new CONDITIONs field...	blob \| commitdiff \| raw \| diff to current
2021-05-18	Luke Kenneth Casso...	add beginning support for SVP64 IEEE754 FP	blob \| commitdiff \| raw \| diff to current
2021-04-23	Luke Kenneth Casso...	add isatables extracted from microwatt and v3.0B spec	blob \| commitdiff \| raw \| diff to current