bmask does not have Rc=1 variant
[openpower-isa.git] / openpower / isatables / minor_22.csv
2022-06-24 Luke Kenneth Casso... bmask does not have Rc=1 variant
2022-06-23 Luke Kenneth Casso... add BM2-Form to power_enums.py
2022-06-23 Andrey MiroshnikovAdded bmask, pywriter failing
2022-06-23 Luke Kenneth Casso... add explanatory comments on minor_22.csv
2022-06-23 Luke Kenneth Casso... add comment-stripping to get_csv()
2022-06-22 Andrey MiroshnikovAdded entries for cprop, not sure if correct
2022-06-20 Luke Kenneth Casso... add absolute-signed-diff next to absolute-unsigned...
2022-06-20 Luke Kenneth Casso... rename absadd[us] to absdac[ud]
2022-06-19 Luke Kenneth Casso... add absadds - signed accumulating add. DRAFT
2022-06-19 Luke Kenneth Casso... add absadd (unsigned) DRAFT
2022-06-19 Luke Kenneth Casso... add absolute-difference DRAFT
2022-06-19 Luke Kenneth Casso... add average-add DRAFT pseudocode and CSV
2022-06-19 Luke Kenneth Casso... add the rest of min/max DRAFT av opcodes
2022-06-19 Luke Kenneth Casso... add maxs DRAFT instruction
2022-06-19 Luke Kenneth Casso... extend minor_22.csv bitsel pattern to cover bits 21..31
2022-05-20 Luke Kenneth Casso... bit of a mess being sorted out
2022-05-19 Dmitry Selyutintemporarily revert opcode changes
2022-05-19 Dmitry Selyutinisatables/minor_22.csv: reflect a new XO bit
2021-11-05 Jacob Lifshayadd comment2 and unofficial fields to existing instructions
2021-07-24 Luke Kenneth Casso... added an extra SVP64 instruction, svstep, to replace...
2021-07-11 Luke Kenneth Casso... whoops 0b00002 is not binary
2021-07-11 Luke Kenneth Casso... add SVREMAP new Form / Fields and CSV entry
2021-07-11 Luke Kenneth Casso... rename svremap to svshape
2021-07-01 Luke Kenneth Casso... add TEMPORARY svremap form and instruction
2021-06-24 Luke Kenneth Casso... add extra CONDITION column to CSVs
2021-04-23 Luke Kenneth Casso... add isatables extracted from microwatt and v3.0B spec