cpu: make ExecSymbol show the symbol in addition to address
[gem5.git] / src / cpu / BaseCPU.py
2020-09-15 Bobby R. Brucemisc: Merge branch 'release-staging-v20.1.0.0' into...
2020-09-15 Bobby R. Brucecpu,misc: Revert problematic terminology renames in...
2020-09-10 Shivani Parekhmisc: Replaced master/slave terminology
2020-08-26 Emily Brickeycpu: update port terminology
2020-08-05 Gabe Blackcpu: Remove the "profile" parameter and plumbing.
2020-07-04 Bobby R. Brucemisc: Merged m5ops_base hotfix into develop
2020-06-08 Bobby R. Brucemisc: Merge hotfix v20.0.0.2 into develop
2020-06-02 Bobby R. Brucemisc: Merge branch version update into develop
2020-06-02 Bobby R. Brucemisc: Merge in 'hotfix-m5-tick-rounding-error'
2020-05-28 Bobby R. BruceMerge branch 'release-staging-v20.0.0.0' into develop
2020-05-28 Bobby R. Brucemisc: Merge branch 'release-staging-v20.0.0.0' into...
2020-05-23 Gabe Blackcpu: Remove the ancient do_quiesce config option.
2020-04-29 Anouk Van Laersim-power: Specify the states a PowerState object can...
2020-04-29 Nils Asmussencpu,configs: let RISC-V use the PT walker cache.
2020-02-26 Bobby R. Brucemisc: merge branch 'release-staging-v19.0.0.0' into...
2020-02-24 Bobby R. Brucemisc: Merged release-staging-v19.0.0.0 into develop
2020-02-17 Gabe Blackcpu: Delete authors lists from the cpu directory.
2020-02-13 Gabe Blackcpu: Remove alpha specialized code.
2020-02-13 Gabe Blackarch,cpu: Make the CPU's ISA parameter type BaseISA.
2019-10-19 Gabe Blackcpu,arm: Push the stage 2 MMUs out of the CPU into...
2019-10-19 Gabe Blackarch: Make a base class for Interrupts.
2019-10-18 Gabe Blackcpu: Turn the stage 2 ARM MMUs from params to children.
2019-10-17 Gabe Blackcpu: Get rid of load count based events.
2019-08-10 Gabe Blackcpu: Pull more arch specialization to the top of BaseCP...
2019-08-10 Gabe Blackx86: Move some fixed or dummy config information into...
2019-04-28 Gabe Blackmem: Minimize the use of MemObject.
2019-02-22 Andreas Sandbergpython: Fix param -> int conversion issues
2019-02-22 Andreas Sandbergpython: Make iterator handling Python 3 compatible
2019-02-12 Andreas Sandbergpython: Don't assume SimObjects live in the global...
2018-03-06 Gabe Blackscons: Switch from the print statement to the print...
2018-01-29 Glenn Bergmansarm: DT autogeneration - Generate cpus node
2018-01-12 Xiaoyu Masim: Allow passing a user-defined L2XBar to addTwoLevel...
2018-01-11 Gabe Blackcpu: Make the CPU's TLB parameter a BaseTLB.
2017-11-29 Andreas Sandbergcpu: Don't override ISA if provided by user
2017-11-20 Jose Marinhocpu: Make automatic transition to OFF optional
2017-11-20 Anouk Van Laerpwr: Adds logic to enter power gating for the cpu model
2017-07-12 Jose Marinhocpu, sim: Add param to force CPUs to wait for GDB
2017-05-02 Andreas Sandbergpython: Use PyBind11 instead of SWIG for Python wrappers
2015-07-20 Brandon Pottersyscall_emul: [patch 13/22] add system call retry capab...
2016-11-30 Alec Roelkearch: [Patch 1/5] Added RISC-V base instruction set...
2016-04-05 Geoffrey Blakecpu: Query CPU for inst executed from Python
2015-09-30 Mitch Hayengaisa,cpu: Add support for FS SMT Interrupts
2015-03-02 Andreas Hanssonmem: Move crossbar default latencies to subclasses
2015-03-02 Andreas Hanssonarm: Share a port for the two table walker objects
2015-01-25 Ali Saidicpu: Put all CPU instruction tracers in a single file
2014-09-20 Andreas Hanssonmem: Rename Bus to XBar to better reflect its behaviour
2014-05-09 Akash Bagdiacpu, arm: Allow the specification of a socket field
2014-01-24 ARM gem5 Developersarm: Add support for ARMv8 (AArch64 & AArch32)
2013-09-04 Andreas Hanssoncpu: Move the branch predictor out of the BaseCPU
2013-06-27 Akash Bagdiasim: Add the notion of clock domains to all ClockedObjects
2013-06-27 Akash Bagdiaconfig: Remove redundant explicit setting of default...
2013-06-11 Andreas Sandbergcpu: Add support for scheduling multiple inst/load...
2013-04-22 Timothy M. Jonescpu: Let python scripts obtain the number of instructio...
2013-04-22 Dam Sunwoocpu: generate SimPoint basic block vector profiles
2013-02-19 Andreas Hanssonx86: Move APIC clock divider to Python
2013-02-15 Andreas Sandbergcpu: Add CPU metadata om the Python classes
2013-01-24 Nilay Vaish ext... branch predictor: move out of o3 and inorder cpus
2013-01-07 Andreas Sandbergcpu: Flush TLBs on switchOut()
2013-01-07 Andreas Sandbergcpu: Rename defer_registration->switched_out
2013-01-07 Andreas Sandbergcpu: Introduce sanity checks when switching between...
2013-01-07 Andreas Sandbergarch: Make the ISA class inherit from SimObject
2012-11-02 Andreas Sandbergsim: Include object header files in SWIG interfaces
2012-10-15 Andreas HanssonRegression: Use CPU clock and 32-byte width for L1...
2012-09-25 Andreas Sandbergsim: Move CPU-specific methods from SimObject to the...
2012-08-28 Andreas HanssonClock: Add a Cycles wrapper class and use where applicable
2012-08-21 Andreas HanssonCPU: Remove overloaded function_trace_start parameter
2012-08-21 Andreas HanssonClock: Move the clock and related functions to ClockedO...
2012-05-31 Andreas HanssonBus: Split the bus into a non-coherent and coherent bus
2012-03-09 Geoffrey BlakeCheckerCPU: Make CheckerCPU runtime selectable instead...
2012-03-01 Nilay Vaishx86: Fix switching of CPUs
2012-02-13 Andreas HanssonMEM: Introduce the master/slave port roles in the Pytho...
2012-02-01 Gabe BlackMerge ... head, hopefully the last time for this batch.
2012-01-31 Geoffrey BlakeCheckerCPU: Re-factor CheckerCPU to be compatible with...
2012-01-31 Gabe BlackMerge with main repository.
2012-01-29 Gabe BlackYet another merge with the main repository.
2012-01-28 Gabe BlackMerge with the main repo.
2012-01-16 Gabe BlackMerge yet again with the main repository.
2012-01-17 Andreas HanssonCPU: Moving towards a more general port across CPU...
2012-01-07 Gabe BlackAnother merge with the main repository.
2012-01-07 Gabe BlackMerge with the main repository again.
2012-01-07 Gabe BlackMerge with main repository.
2011-12-01 Ali SaidiARM: Add support for having a TLB cache.
2011-11-18 Gabe BlackSE/FS: Get rid of FULL_SYSTEM in the CPU directory.
2011-11-02 Gabe BlackSE/FS: Get rid of FULL_SYSTEM in sim.
2011-10-16 Gabe BlackARM: Turn on the page table walker on ARM in SE mode.
2011-10-13 Gabe BlackX86: Turn on the page table walker in SE mode.
2011-10-09 Gabe BlackSE/FS: Build the Interrupt objects in SE mode.
2011-03-26 Korey Sewellmips: cleanup ISA-specific code
2011-02-07 Joel Hestnessmcpat: Adds McPAT performance counters
2011-02-04 Gabe BlackConfig: Keep track of uncached and cached ports separately.
2011-02-02 Gabe BlackX86: Add L1 caches for the TLB walkers.
2010-11-23 Gabe BlackX86: Loosen an assert for x86 and connect the APIC...
2010-06-02 Ali SaidiARM: Implement the ARM TLB/Tablewalker. Needs performan...
2010-01-19 Derek Howermerge
2009-10-27 Timothy M. JonesPOWER: Add support for the Power ISA
2009-09-22 Nathan Binkertpython: Move more code into m5.util allow SCons to...
2009-04-21 Nathan BinkertAutomated merge with ssh://m5sim.org//repo/m5
2009-04-21 Nathan Binkertarm: Unify the ARM tlb. We forgot about this when...
2009-04-09 Nathan Binkerttlb: More fixing of unified TLB
2009-04-09 Gabe Blacktlb: Don't separate the TLB classes into an instruction...
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