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radeon: enable Hyper-Z on r600g and radeonsi by default
[mesa.git]
/
src
/
gallium
/
drivers
/
nouveau
/
codegen
/
nv50_ir_target_nvc0.cpp
2014-09-09
Ilia Mirkin
nv50/ir: avoid array overrun when checking for supporte...
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2014-05-28
Alexandre Courbot
nvc0/ir: use SM35 ISA with GK20A
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2014-05-14
Ben Skeggs
nvc0: maxwell isa has no per-instruction join modifier
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2014-05-14
Ben Skeggs
nvc0: allow for easier modification of compiler library...
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2014-04-28
Ilia Mirkin
nvc0/ir: add support for new bitfield manipulation...
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2014-04-26
Ilia Mirkin
nvc0/ir: add support for SAMPLEMASK sysval
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2014-04-26
Ilia Mirkin
nvc0: add support for PIPE_CAP_SAMPLE_SHADING
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2014-03-18
Ilia Mirkin
nv50/ir/gk110: add 64/128-bit fetch/export support
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2013-12-06
Ben Skeggs
nvc0: fixup gk110 and up not being listed in various...
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2013-09-11
Johannes Obermayr
Move nv30, nv50 and nvc0 to nouveau.
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