deepcopy is really slow and unnecessary here
[openpower-isa.git] / src / openpower / decoder / isa / caller.py
2023-06-14 Jacob Lifshaycache SVP64Instruction.Prefix instance since it's slow...
2023-06-13 Jacob Lifshayremove fcvttgs since it's redundant
2023-06-03 Dmitry Selyutininsndb: rename types into core
2023-06-03 Dmitry Selyutininsndb: revert recent renaming
2023-06-03 Luke Kenneth Casso... using names of modules that are identical to commonly...
2023-06-02 Dmitry Selyutinpower_insn: decouple into separate module
2023-05-27 Luke Kenneth Casso... https://bugs.libre-soc.org/show_bug.cgi?id=1091
2023-05-24 Luke Kenneth Casso... note on FP Exception about DDFF VLi=0/1
2023-05-24 Jacob LifshayISACaller: generate FP trap
2023-05-21 Luke Kenneth Casso... explicitly update FPSCR from list of return results
2023-05-21 Luke Kenneth Casso... code-comment spelling
2023-05-19 Jacob Lifshaycompute CR1 for non-compare fp Rc=1 instructions
2023-05-18 Jacob Lifshayfix CR0 output for fmvtg*/fcvttg*
2023-05-16 Luke Kenneth Casso... replace self.insnlog.append with self.trace function
2023-05-15 Luke Kenneth Casso... got linked-list-pointer-chasing working
2023-05-15 Luke Kenneth Casso... have to now add LD/ST-update instructions to list of...
2023-05-12 Jacob Lifshayadd support for *_flag global variables needed by bfp_...
2023-05-10 Luke Kenneth Casso... add very very very basic write-out of instruction log
2023-05-10 Jacob LifshayMerge branch 'support-fields'
2023-05-10 Luke Kenneth Casso... fix data-dependent fail-first on load
2023-05-10 Luke Kenneth Casso... extend previous hard-coded magic constant (256) used...
2023-05-10 Jacob Lifshaychange FPSCR to a required parameter of ISACallerHelper support-fields
2023-05-10 Jacob LifshayRevert "remove now-unnecessary SO global, since XER...
2023-05-10 Jacob Lifshayadd self.FPSCR
2023-05-10 Jacob Lifshayremove now-unnecessary SO global, since XER[SO] syntax...
2023-05-10 Jacob Lifshayadd support for accessing XER using XER.SO syntax ...
2023-05-06 Luke Kenneth Casso... add FPSCR to ISACaller
2023-05-04 Konstantinos Marga... merge maddrs/msubrs, unit tests changed accordingly
2023-05-04 Konstantinos Marga... Add 2 more instructions to help with 2-coeff butterfly
2023-05-04 Konstantinos Marga... WIP: maddsubrs initial approach
2023-05-04 Jacob Lifshayadd fcvt/fmv -- no tests yet
2023-04-28 Luke Kenneth Casso... reduce fdmadds down to only 3 operands, RT-overwrite...
2023-04-25 Luke Kenneth Casso... check RC1, add data-dependent fail-first LD/ST test
2023-04-25 Jacob Lifshayreplace min/max[su][.] with minmax[.]
2023-04-18 Jacob Lifshayadd shaddw
2023-04-06 Luke Kenneth Casso... add power_decode_svp64_rm.py capability for new LD...
2023-04-04 Luke Kenneth Casso... comment about massive unnecessary code-duplication...
2023-03-30 Jacob Lifshayfix add-like CA/OV outputs
2023-03-30 Jacob Lifshayadd addex to simulator
2023-03-30 Jacob Lifshayfix typo when getting pseudo-code output variables
2023-01-15 Dmitry Selyutinpower_enums: clean code
2023-01-15 Dmitry Selyutinpower_insn: sort opcodes by sections
2023-01-01 Luke Kenneth Casso... enable misaligned Mem in ISACaller by default
2022-12-29 Luke Kenneth Casso... print out memory exception details, on unaligned
2022-11-11 Jacob Lifshayadd maddedus
2022-10-29 Luke Kenneth Casso... add dsld. (Rc=1) test, make overflow acceptable to...
2022-10-27 Dmitry Selyutinisa/caller.py: support shadd/shadduw instructions
2022-10-24 Luke Kenneth Casso... add maxs. combined with cmp capability
2022-10-22 Jacob Lifshayfix get_masked_reg and add test
2022-10-22 Jacob Lifshayformat code removing unused imports
2022-10-21 Luke Kenneth Casso... move chacha20 to separate test, set/get masked regs...
2022-10-19 Luke Kenneth Casso... TODO, sort out remap indices order
2022-10-16 Luke Kenneth Casso... debug print correction
2022-10-16 Luke Kenneth Casso... sigh, have to use yield from on get_out_map()
2022-10-16 Luke Kenneth Casso... rewrite get_idx_out2 in ISACaller to split out
2022-10-16 Luke Kenneth Casso... rewrite get_idx_out in ISACaller to split out
2022-10-16 Luke Kenneth Casso... code-shuffle, rework get_idx_in() to separate out the...
2022-10-14 Luke Kenneth Casso... SVP64RMModeDecode detects Post-Inc LDST-imm mode
2022-10-14 Luke Kenneth Casso... add ld/st-immediate "post-inc" mode support. unit test...
2022-10-11 Luke Kenneth Casso... whoops zero-error on masked-out
2022-10-10 Luke Kenneth Casso... add elwidth overrides to get_idx_out2
2022-10-08 Luke Kenneth Casso... fix format in debug log
2022-10-08 Luke Kenneth Casso... forgot to add offset on GPR() get
2022-10-08 Luke Kenneth Casso... add elwidth overrides on destination (write) in ISACaller.
2022-10-08 Luke Kenneth Casso... split out base,offset in register decoding for elwidth...
2022-10-07 Luke Kenneth Casso... more work on inssort. add useful reg-dump in ISACaller
2022-10-06 Luke Kenneth Casso... nope. failfirst needs to always save the result, but...
2022-10-06 Luke Kenneth Casso... sort out CROPs fail-first in ISACaller. needed to...
2022-10-06 Luke Kenneth Casso... make fail-first cope with sv.cmp which uses CR[BF]
2022-10-06 Luke Kenneth Casso... search for BF in registers to over-ride Vector lookup...
2022-10-06 Luke Kenneth Casso... starting to add sv.cmp support and failfirst, had to add
2022-10-02 Luke Kenneth Casso... comments for why preinc is called for svstep
2022-10-01 Luke Kenneth Casso... skip svstate_pre_inc on svremap
2022-10-01 Luke Kenneth Casso... no svstate instruction
2022-10-01 Luke Kenneth Casso... svstep calls SVSTATE_NEXT so needs svstate_pre_inc
2022-10-01 Luke Kenneth Casso... replacing setvl-svstep with just svstep
2022-10-01 Luke Kenneth Casso... comments
2022-10-01 Luke Kenneth Casso... comments
2022-10-01 Luke Kenneth Casso... minor cleanup in ISACaller on result handling
2022-10-01 Luke Kenneth Casso... simplify ISACaller execute_one
2022-10-01 Luke Kenneth Casso... simplify setting default SVSHAPE SPRs to zero
2022-09-30 Luke Kenneth Casso... set srcstep/dststep to zero in StepLoop (ISACaller...
2022-09-30 Luke Kenneth Casso... comments/variables-cleanup
2022-09-30 Luke Kenneth Casso... add sv.bc/vs - VLset - test. truncates VL at the vector...
2022-09-30 Luke Kenneth Casso... whitespace
2022-09-30 Luke Kenneth Casso... use regs variables in get_predint
2022-09-30 Luke Kenneth Casso... comments
2022-09-29 Luke Kenneth Casso... update iterators in ISACaller, not used yet
2022-09-29 Jacob Lifshayrename madded->maddedu for consistency with PowerISA...
2022-09-29 Jacob Lifshayrename divrem2du->divmod2du for consistency with PowerI...
2022-09-29 Jacob Lifshayadd bigint ops
2022-09-28 Luke Kenneth Casso... srcstep
2022-09-28 Luke Kenneth Casso... rename iterators init function
2022-09-28 Luke Kenneth Casso... redundant comment
2022-09-28 Luke Kenneth Casso... split out svstate update in ISACaller
2022-09-28 Luke Kenneth Casso... move failfirst check to separate function in ISACaller
2022-09-28 Luke Kenneth Casso... bugfix reset remaps and get subvl early
2022-09-27 Luke Kenneth Casso... hack to check skipping on predicate being all-zero.
2022-09-27 Luke Kenneth Casso... sort out predicate loop-skip on pack/unpack
2022-09-27 Luke Kenneth Casso... adapt loops to include predicate-mask skipping in ISACaller
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