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add LD-half-swap for i-DCT which does not work. redesign needed
[openpower-isa.git]
/
src
/
openpower
/
decoder
/
isa
/
test_caller_fp.py
2021-06-23
Luke Kenneth Casso...
better ways to do sign-inversion (without multiply...
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2021-06-15
Luke Kenneth Casso...
add fmadds and fmsubs to Power ISA pseudo-code, add...
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2021-06-08
Luke Kenneth Casso...
whoops, carry-over during rounding picks MSB not LSB
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2021-06-08
Luke Kenneth Casso...
whoops copy sign over on zero
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2021-06-08
Luke Kenneth Casso...
exponent bitwidth in DOUBLE2SINGLE needs to be 11 bits...
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2021-06-02
Luke Kenneth Casso...
fmuls test showing rounding error against qemu
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2021-06-02
Luke Kenneth Casso...
found FP single-conversion error, from the pseudocode...
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2021-05-24
Luke Kenneth Casso...
add extra (dummy) mul operation, 0*0
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2021-05-24
Luke Kenneth Casso...
fmuls is fine
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2021-05-16
Luke Kenneth Casso...
add fpcvt.mdwn pseudocode which calls new auto-generate...
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2021-05-15
Luke Kenneth Casso...
FP mul test, correct pseudocode to use FRC
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2021-05-15
Luke Kenneth Casso...
issue with sub-decoders
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2021-05-15
Luke Kenneth Casso...
comments
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2021-05-15
Luke Kenneth Casso...
add fcpsgn unit test
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2021-05-15
Luke Kenneth Casso...
add fnabs unit test
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2021-05-15
Luke Kenneth Casso...
add fabs unit test
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2021-05-15
Luke Kenneth Casso...
add fp mv test, correct pseudocode
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2021-05-15
Luke Kenneth Casso...
add fmr test and associated decoder (optional with...
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2021-05-15
Luke Kenneth Casso...
add new fp load / store with update unit test
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2021-05-14
Luke Kenneth Casso...
add FP load test lfsx
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2021-05-14
Luke Kenneth Casso...
add FRA ISACaller name decoding
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2021-05-14
Luke Kenneth Casso...
add first FP load test, still a lot TODO
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