move D-Immediate rewriting in ISACaller into separate function
[openpower-isa.git] / src / openpower / decoder / isa /
2022-07-18 Luke Kenneth Casso... move D-Immediate rewriting in ISACaller into separate...
2022-07-18 Luke Kenneth Casso... move inputs in ISACaller into get_input()
2022-07-18 Luke Kenneth Casso... move debug remap to ISACaller.remap_debug()
2022-07-18 Luke Kenneth Casso... whitespace and function-return code-morphing in ISACaller
2022-07-18 Luke Kenneth Casso... move another function in ISACaller (check_write)
2022-07-18 Luke Kenneth Casso... begin function split in ISACaller
2022-07-18 Luke Kenneth Casso... remove duplicate code create ISACaller.advance_svstate_...
2022-07-18 Luke Kenneth Casso... add SUBVL (substep) support to PowerDecoder2 and to...
2022-07-18 Luke Kenneth Casso... add substep getter/setter to SVP64State
2022-07-16 Luke Kenneth Casso... simplify remapyield.py, skip shows the bit to be skipped
2022-07-14 Luke Kenneth Casso... got fed up of long list of ifs for manually decoded...
2022-07-11 Luke Kenneth Casso... add mm=1 svindex test, setting single targetted SVSHAPE
2022-07-10 Luke Kenneth Casso... add yx svindex test, needed to compute size of 2nd dim
2022-07-10 Luke Kenneth Casso... Indexed SVSHAPE add bypass mode when dim sizes are 1
2022-07-10 Luke Kenneth Casso... add second svindex test, modulo 3
2022-07-10 Luke Kenneth Casso... fix svindex unit test, experiment setting dimensions
2022-07-10 Luke Kenneth Casso... fix SVSHAPE iterator for index case, stop deepcopy
2022-07-10 Luke Kenneth Casso... add new svindex sv.add test with arbitrary index map
2022-07-10 Luke Kenneth Casso... non-persistence enabled on svindex as well as svremap
2022-07-10 Luke Kenneth Casso... fix svindex pseudocode
2022-07-09 Luke Kenneth Casso... pass GPR to SVSHAPEs in ISACaller
2022-07-09 Luke Kenneth Casso... add gpr lookup in Indexed SVSHAPE iterator (no elwidths...
2022-07-09 Luke Kenneth Casso... rough unit test ahowing Index REMAP basically functiona...
2022-07-09 Luke Kenneth Casso... add support for Indexed mode in SVSHAPE
2022-07-06 Luke Kenneth Casso... add first stub of svindex pseudocode
2022-07-06 Luke Kenneth Casso... convert Logical svp64_cases.py to new vector reg form
2022-07-06 Luke Kenneth Casso... convert ALU svp64_cases.py to new vector reg form
2022-07-06 Luke Kenneth Casso... converted test_caller_svstate.py to new reg format
2022-07-05 Andrey Miroshnikovconvert test_caller_svp64.py to new vector numbering...
2022-07-05 Andrey Miroshnikovconvert test_caller_svp64_predication.py to new vector...
2022-07-05 Andrey Miroshnikovconvert test_caller_svp64_ldst.py to new vector numberi...
2022-07-05 Andrey MiroshnikovUpdated the nmigen.sim import
2022-07-05 Andrey Miroshnikovconvert test_caller_svp64_fft.py to new vector numberin...
2022-07-05 Andrey Miroshnikovconvert test_caller_svp64_bc.py to new vector numbering...
2022-07-05 Andrey Miroshnikovconvert test_caller_svp64_dct.py to new vector numberin...
2022-07-05 Luke Kenneth Casso... converted test_caller_svp64_matrix.py to new reg format
2022-07-05 Luke Kenneth Casso... converted test_caller_svp64_fp.py to new reg format
2022-07-05 Luke Kenneth Casso... converted test_caller_svp64_mapreduce.py to new reg...
2022-07-05 Luke Kenneth Casso... convert test_caller_setvl.py to new vector numbering...
2022-07-02 Luke Kenneth Casso... add setvl CTR tests, fix CTR mode
2022-07-02 Luke Kenneth Casso... setvl has new CTR mode, making room in encoding needed
2022-06-26 Luke Kenneth Casso... add predicate mask test svstep
2022-06-26 Luke Kenneth Casso... add predicated srcstep
2022-06-26 Luke Kenneth Casso... make svstep output srcstep/dststep, basically viota
2022-06-26 Luke Kenneth Casso... again fix number of arguments to svremap,
2022-06-26 Luke Kenneth Casso... test_caller_svstate.py: end-of-loop condition sets...
2022-06-26 Luke Kenneth Casso... svp64_matrix.py svremap reduce to 7 args from 8 (again)
2022-06-26 Luke Kenneth Casso... svremap only takes 7 args not 8, same as in svp64_fft.py
2022-06-26 Luke Kenneth Casso... one too many arguments to svremap in svp64_fft.py test
2022-06-26 Luke Kenneth Casso... whoops hack-use of DOUBLE2SINGLE in test_caller_transce...
2022-06-26 Luke Kenneth Casso... add test case for kaivb to jump to 0x2700
2022-06-23 Andrey MiroshnikovAdded bmask, pywriter failing
2022-06-22 Andrey MiroshnikovAdded cprop to caller, enums, svp64
2022-06-20 Luke Kenneth Casso... add absolute-signed-diff next to absolute-unsigned...
2022-06-20 Luke Kenneth Casso... rename absadd[us] to absdac[ud]
2022-06-19 Jacob Lifshayupdate after adding av instructions
2022-06-19 Luke Kenneth Casso... add absadd (unsigned) DRAFT
2022-06-19 Luke Kenneth Casso... add absolute-difference DRAFT
2022-06-19 Luke Kenneth Casso... add average-add DRAFT pseudocode and CSV
2022-06-19 Luke Kenneth Casso... add maxs DRAFT instruction
2022-05-03 Jacob Lifshayadd Rc to ternlogi
2022-05-03 Jacob Lifshayformat code
2022-05-03 Jacob Lifshayadd svfixedarith.py to .gitignore
2022-04-20 Dmitry Selyutinselectable_int: derive SelectableIntMapping on per...
2022-04-20 Dmitry Selyutinisa.caller: support default SVP64PrefixFields initializ...
2022-04-19 Dmitry Selyutinisa.caller: support whole integer pseudo-field
2022-04-19 Dmitry Selyutinisa.caller: refactor SVP64PrefixFields class
2022-04-19 Dmitry Selyutinisa.caller: refactor SVP64RMFields class
2022-04-07 Luke Kenneth Casso... whitespace (80 char limit)
2022-04-07 Luke Kenneth Casso... comment 64-bit of predicate (all 1s)
2022-03-26 Luke Kenneth Casso... Revert "add python generator version of tree reduction"
2022-03-25 Jacob Lifshayadd python generator version of tree reduction
2022-01-18 Jacob Lifshaygrev[w][i][.] pseudo-code works
2022-01-18 Jacob Lifshayformat code
2022-01-18 Jacob Lifshayadd test_caller_logical.py
2022-01-06 Jacob Lifshayadd stand-alone simulator bitmanip test
2021-12-21 Luke Kenneth Casso... ISACaller (actually RADIXMMU) only do virtual memory...
2021-12-20 Luke Kenneth Casso... whoops forgot to trap if non-execute (instruction)...
2021-12-19 Luke Kenneth Casso... TODO notes for executing ISACaller Invalid Instruction...
2021-12-19 Luke Kenneth Casso... pass the mode (LOAD,EXECUTE,STORE) through ISACaller...
2021-12-10 Jacob Lifshaychange ternlogi to not have Rc field
2021-12-09 Jacob Lifshaymake ternlogi tests run
2021-12-09 Jacob Lifshayadd initial ternlogi pseudo-code
2021-12-04 Luke Kenneth Casso... raise a MemException in ISACaller RADIXMMU
2021-11-30 Luke Kenneth Casso... attempting to use PowerDecode2 in non-svp64 mode
2021-11-10 Luke Kenneth Casso... add creation of 8 and 16 DCT butterfly diagrams
2021-11-04 klehmancaller.py: Fix ISACaller modifying test state
2021-10-23 R Veera KumarAdd a new test caller for ALU based on shift_rot test...
2021-10-10 Dmitry Selyutintest_caller_exts: extsb/extsh/extsw test
2021-09-29 Dmitry Selyutinisa/caller: initialize helper and redirect XLEN
2021-09-28 Luke Kenneth Casso... remove unneeded module import
2021-09-28 Luke Kenneth Casso... convert svp64 fft test just like the dct one
2021-09-28 Luke Kenneth Casso... convert test_caller_svp64_dct.py unit test to use new...
2021-09-28 Luke Kenneth Casso... move FPDIV, FPMUL (etc) to ISAFPHelpers class
2021-09-25 Luke Kenneth Casso... inherit ISACallerHelper in ISACaller
2021-09-24 Luke Kenneth Casso... rename shift tests, move to test cases directory
2021-09-24 Luke Kenneth Casso... rename files, test_issuer.py is for the TestIssuer,
2021-09-24 klehmanshift_rot expected cases
2021-09-24 klehmandecoder test_issuer
2021-09-23 Luke Kenneth Casso... add stfs unit test
next