2022-10-25 |
Dmitry Selyutin | pysvp64asm: support shadd/shadduw instructions |
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2022-10-25 |
Dmitry Selyutin | pysvp64asm: introduce more flexible Z23 wrapper |
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2022-10-25 |
Dmitry Selyutin | test_pysvp64dis: test shadd/shadduw instructions |
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2022-10-25 |
Dmitry Selyutin | minor_4.csv: support shadd/shadduw instructions |
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2022-10-24 |
Luke Kenneth Casso... | add maxs. combined with cmp capability |
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2022-10-23 |
Luke Kenneth Casso... | use svshape2 instead of svindex for the 4th shape |
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2022-10-22 |
Luke Kenneth Casso... | add extra pysvp64dis tests for divmod2du and maddedu |
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2022-10-22 |
Luke Kenneth Casso... | argh, extremely annoying: 4-operand dsld/dsrd is not... |
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2022-10-22 |
Luke Kenneth Casso... | remove redundant case_dsrd3 |
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2022-10-22 |
Luke Kenneth Casso... | bigint shuffle |
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2022-10-22 |
Jacob Lifshay | fix get_masked_reg and add test |
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2022-10-22 |
Jacob Lifshay | format code removing unused imports |
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2022-10-21 |
Luke Kenneth Casso... | code-comments |
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2022-10-21 |
Luke Kenneth Casso... | add 2nd outer loop, CTR 2 rounds, in chacha20 test |
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2022-10-21 |
Luke Kenneth Casso... | move chacha20 to separate test, set/get masked regs... |
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2022-10-21 |
Luke Kenneth Casso... | move HASK, ROTL32, ROTL64, MASK32, into helper class |
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2022-10-20 |
Luke Kenneth Casso... | comments |
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2022-10-20 |
Luke Kenneth Casso... | add first chacha20 round test |
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2022-10-19 |
Dmitry Selyutin | sv_binutils_fptrans: fix registers generation |
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2022-10-19 |
Luke Kenneth Casso... | TODO, sort out remap indices order |
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2022-10-18 |
Jacob Lifshay | add test for scalar sv.maddedu |
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2022-10-18 |
Jacob Lifshay | add missing files to .gitignore |
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2022-10-16 |
Luke Kenneth Casso... | debug print correction |
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2022-10-16 |
Luke Kenneth Casso... | sigh, have to use yield from on get_out_map() |
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2022-10-16 |
Luke Kenneth Casso... | rewrite get_idx_out2 in ISACaller to split out |
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2022-10-16 |
Luke Kenneth Casso... | rewrite get_idx_out in ISACaller to split out |
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2022-10-16 |
Luke Kenneth Casso... | add unit test showing two svindex calls, found bugs, |
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2022-10-16 |
Luke Kenneth Casso... | code-shuffle, rework get_idx_in() to separate out the... |
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2022-10-14 |
Dmitry Selyutin | sv_binutils_fptrans: fix opcodes mode |
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2022-10-14 |
Dmitry Selyutin | power_insn: really skip sv. entries for PPC database |
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2022-10-14 |
Dmitry Selyutin | sv_binutils_fptrans: generate all permutations |
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2022-10-14 |
Dmitry Selyutin | pysvp64asm: fix coding style |
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2022-10-14 |
Dmitry Selyutin | power_insn: skip sv. instructions in PPC database |
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2022-10-14 |
Dmitry Selyutin | power_insn: fix AA match |
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2022-10-14 |
Dmitry Selyutin | power_insn: do not allow default records |
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2022-10-14 |
Luke Kenneth Casso... | add max-with-getting-index-of vertical-first loop example |
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2022-10-14 |
Luke Kenneth Casso... | SVP64RMModeDecode detects Post-Inc LDST-imm mode |
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2022-10-14 |
Luke Kenneth Casso... | correct comments |
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2022-10-14 |
Luke Kenneth Casso... | add in zeroing on test strncpy |
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2022-10-14 |
Luke Kenneth Casso... | remove unneeded svstate from test |
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2022-10-14 |
Luke Kenneth Casso... | add strncpy example - 6 instructions |
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2022-10-14 |
Luke Kenneth Casso... | add sv.stwu/pi example in test_sv_load_store_postinc |
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2022-10-14 |
Luke Kenneth Casso... | add ld/st-immediate "post-inc" mode support. unit test... |
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2022-10-14 |
Luke Kenneth Casso... | add /pi to sv/trans/svp64.py and power_insns.py |
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2022-10-14 |
Luke Kenneth Casso... | add new LD-Immediate Post constants |
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2022-10-12 |
Luke Kenneth Casso... | add sv.divmod2du test, inverse of the sv.madded |
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2022-10-12 |
Luke Kenneth Casso... | comments clean-up on bigint big-mul case |
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2022-10-11 |
Luke Kenneth Casso... | add asciidump option to Mem class |
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2022-10-11 |
Luke Kenneth Casso... | whoops zero-error on masked-out |
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2022-10-10 |
Luke Kenneth Casso... | add elwidth overrides on Indexed REMAP, 8-bit example... |
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2022-10-10 |
Luke Kenneth Casso... | add elwidth overrides to get_idx_out2 |
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2022-10-08 |
Luke Kenneth Casso... | fix format in debug log |
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2022-10-08 |
Luke Kenneth Casso... | forgot to add offset on GPR() get |
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2022-10-08 |
Luke Kenneth Casso... | add elwidth overrides on destination (write) in ISACaller. |
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2022-10-08 |
Luke Kenneth Casso... | split out base,offset in register decoding for elwidth... |
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2022-10-08 |
Luke Kenneth Casso... | add 8-bit elwidth alu svp64 case |
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2022-10-08 |
Luke Kenneth Casso... | add rfscv to major_19.csv, add test_pysvp64dis.py unit... |
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2022-10-08 |
Luke Kenneth Casso... | drat |
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2022-10-08 |
Luke Kenneth Casso... | add sc and scv support after moving from major.csv... |
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2022-10-08 |
Luke Kenneth Casso... | vector name "RSp" not recognised in sv.stq, added as... |
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2022-10-08 |
Luke Kenneth Casso... | add stq to CSV files and unit test to test_pysvp64dis.py |
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2022-10-08 |
Luke Kenneth Casso... | separate out DQ and DS to separate custom_immediates |
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2022-10-08 |
Luke Kenneth Casso... | use new base-class EXTSOperand, derive from ImmediateOp... |
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2022-10-08 |
Luke Kenneth Casso... | convert TargetAddrOperand to base class EXTSOperand |
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2022-10-08 |
Luke Kenneth Casso... | add lq and CONST_DQ |
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2022-10-08 |
Luke Kenneth Casso... | restore tests, accidentally disabled |
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2022-10-08 |
Luke Kenneth Casso... | add XER bits to register enums |
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2022-10-08 |
Luke Kenneth Casso... | add addex to csv and sv_analysis db. also needs CryIn... |
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2022-10-07 |
Luke Kenneth Casso... | more work on inssort. add useful reg-dump in ISACaller |
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2022-10-06 |
Luke Kenneth Casso... | nope. failfirst needs to always save the result, but... |
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2022-10-06 |
Luke Kenneth Casso... | fix fail-first to exclude failed element in VLi=0 mode |
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2022-10-06 |
Luke Kenneth Casso... | sort out CROPs fail-first in ISACaller. needed to... |
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2022-10-06 |
Luke Kenneth Casso... | make fail-first cope with sv.cmp which uses CR[BF] |
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2022-10-06 |
Luke Kenneth Casso... | add insert sort svp64 test |
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2022-10-06 |
Luke Kenneth Casso... | search for BF in registers to over-ride Vector lookup... |
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2022-10-06 |
Luke Kenneth Casso... | starting to add sv.cmp support and failfirst, had to add |
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2022-10-06 |
Luke Kenneth Casso... | add PredicateBaseRM decode to CR Ops Simple mode as... |
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2022-10-06 |
Luke Kenneth Casso... | add vli mode to ff=5 CR ops |
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2022-10-06 |
Luke Kenneth Casso... | whoops must only be PredicateBaseRM in CROpFF5RM |
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2022-10-06 |
Luke Kenneth Casso... | add sv.cmp (ffirst-5) decode/encode asm support |
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2022-10-06 |
Luke Kenneth Casso... | slightly different crops failfirst mode bits |
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2022-10-06 |
Luke Kenneth Casso... | add sv.cmp and try fail-first test_pysvp64dist.py |
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2022-10-02 |
Luke Kenneth Casso... | remove complaints about standard Cray-style Vectors... |
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2022-10-02 |
Luke Kenneth Casso... | comments for why preinc is called for svstep |
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2022-10-02 |
Luke Kenneth Casso... | comment out selectableint getitem logs |
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2022-10-01 |
Luke Kenneth Casso... | skip svstate_pre_inc on svremap |
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2022-10-01 |
Luke Kenneth Casso... | no svstate instruction |
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2022-10-01 |
Luke Kenneth Casso... | svstep calls SVSTATE_NEXT so needs svstate_pre_inc |
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2022-10-01 |
Luke Kenneth Casso... | replacing setvl-svstep with just svstep |
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2022-10-01 |
Luke Kenneth Casso... | replacing setvl-svstep with just svstep |
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2022-10-01 |
Luke Kenneth Casso... | replacing setvl-svstep with just svstep |
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2022-10-01 |
Luke Kenneth Casso... | comments |
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2022-10-01 |
Luke Kenneth Casso... | comments |
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2022-10-01 |
Luke Kenneth Casso... | minor cleanup in ISACaller on result handling |
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2022-10-01 |
Luke Kenneth Casso... | simplify ISACaller execute_one |
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2022-10-01 |
Luke Kenneth Casso... | simplify setting default SVSHAPE SPRs to zero |
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2022-10-01 |
Jacob Lifshay | increase pcdec. output compression by skipping impossib... |
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2022-09-30 |
Jacob Lifshay | prefix codes tests pass |
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2022-09-30 |
Luke Kenneth Casso... | ctr mode not needed, just use unconditional CTR dec |
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2022-09-30 |
Luke Kenneth Casso... | set srcstep/dststep to zero in StepLoop (ISACaller... |
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