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Allow the formal engine to perform a same-cycle result in the ALU
[soc.git]
/
src
/
regfile
/ regfile.py
2020-03-09
Luke Kenneth Casso...
move all source directories to soc so that "import...
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2019-06-18
Luke Kenneth Casso...
add address and output mode from LDSTCUs
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2019-05-15
Luke Kenneth Casso...
very weird: invert readable vector, cscore works
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2019-05-14
Luke Kenneth Casso...
experimenting with cscore, overlapping instructions
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2019-05-08
Luke Kenneth Casso...
disable writethru for now
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2019-05-08
Luke Kenneth Casso...
add regfile array test
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2019-05-08
Luke Kenneth Casso...
start on unit test
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2019-05-08
Luke Kenneth Casso...
whoops connect enable / data correct way round in regfi...
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2019-05-08
Luke Kenneth Casso...
add ORing of port inputs together
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2019-05-08
Luke Kenneth Casso...
add names to read/write ports, add priority picker...
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2019-05-07
Luke Kenneth Casso...
add a variant of a regfile that has individual read...
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2019-05-07
Luke Kenneth Casso...
add regfile.py
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