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use shifter opcode
[soc.git]
/
src
/
regfile
/
2019-05-15
Luke Kenneth Casso...
very weird: invert readable vector, cscore works
tree
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commitdiff
2019-05-14
Luke Kenneth Casso...
experimenting with cscore, overlapping instructions
tree
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commitdiff
2019-05-08
Luke Kenneth Casso...
disable writethru for now
tree
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commitdiff
2019-05-08
Luke Kenneth Casso...
add regfile array test
tree
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commitdiff
2019-05-08
Luke Kenneth Casso...
start on unit test
tree
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commitdiff
2019-05-08
Luke Kenneth Casso...
whoops connect enable / data correct way round in regfi...
tree
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commitdiff
2019-05-08
Luke Kenneth Casso...
add ORing of port inputs together
tree
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commitdiff
2019-05-08
Luke Kenneth Casso...
add names to read/write ports, add priority picker...
tree
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commitdiff
2019-05-07
Luke Kenneth Casso...
add a variant of a regfile that has individual read...
tree
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commitdiff
2019-05-07
Luke Kenneth Casso...
add regfile.py
tree
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commitdiff