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sort out core write latching: gate by busy, and use CompUnit dest output
[soc.git]
/
src
/
soc
/
config
/
loadstore.py
2020-07-02
Luke Kenneth Casso...
add bare wishbone option to TestIssuer, sort out ports
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2020-07-01
Luke Kenneth Casso...
minor reorg on how Bus and Config classes are set up
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2020-06-27
Luke Kenneth Casso...
reconfigureable PortInterface testing now possible
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2020-06-26
Luke Kenneth Casso...
code-morph which redirects lsmem unit test through...
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2020-06-26
Luke Kenneth Casso...
add a test SRAM that lives behind a minerva LoadStoreUn...
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2020-06-26
Luke Kenneth Casso...
add reconfigureable Load/Store class
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