refactoring (see #216 Comment 43)
[soc.git] / src / soc / experiment / l0_cache.py
2020-05-25 Tobias Platenrefactoring (see #216 Comment 43)
2020-05-25 Tobias Platenwhitespace changes
2020-05-25 Tobias Platenimplement DataMerger interface
2020-05-24 Cesar StraussRename the internal DFF of latchregisters to avoid...
2020-05-23 Luke Kenneth Casso... add stub DataMerger class
2020-05-08 Luke Kenneth Casso... send address to memory only for one cycle and acknowled...
2020-05-08 Luke Kenneth Casso... prototype LD/ST L0 cache/buffer was bouncing address...
2020-05-06 Luke Kenneth Casso... mention need for DualPortSplitter class
2020-05-04 Luke Kenneth Casso... comments
2020-05-04 Luke Kenneth Casso... take out wait for busy in L0BufferCache tests
2020-05-04 Luke Kenneth Casso... whitespace cleanup
2020-05-04 Luke Kenneth Casso... bit of a mess, but functional. unit test passes on...
2020-05-04 Luke Kenneth Casso... hmmm trying to get st to acknowledge properly
2020-05-04 Luke Kenneth Casso... add links to bugreport and to memory/cache wiki page
2020-05-04 Luke Kenneth Casso... L0 cache/buffer first unit test, working except for...
2020-05-04 Luke Kenneth Casso... first cut at "basic" L0 Cache/Buffer (untested), only...
2020-05-04 Luke Kenneth Casso... document PortInterface, start on "dummy" L0CacheBuffer
2020-04-27 Luke Kenneth Casso... add LDST PortInterface class