syntax error correction
[soc.git] / src / soc / experiment / score6600.py
2020-07-22 Jacob LifshayMerge remote-tracking branch 'origin/master'
2020-07-22 Jacob Lifshayformat code
2020-07-12 Luke Kenneth Casso... rename InternalOp to MicrOp
2020-04-17 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-04-11 Luke Kenneth Casso... spelling mistake
2020-04-11 Luke Kenneth Casso... holy cow, decode and run instruction works!
2020-04-11 Luke Kenneth Casso... test additional instructions
2020-04-11 Luke Kenneth Casso... adding immediates, tracking down a bug
2020-04-10 Luke Kenneth Casso... connect up ALU properly to pass full InternalOp subset...
2020-04-10 Luke Kenneth Casso... add 2nd add instruction to see what happens (success)
2020-04-10 Luke Kenneth Casso... eek, first cut at using POWER decoder2 in 6600 simulato...
2020-04-08 Luke Kenneth Casso... absolute imports
2020-04-06 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-04-06 Jacob LifshayMerge branch 'fix-tests'
2020-04-06 Jacob Lifshayalmost all tests work
2020-03-23 Luke Kenneth Casso... split sim classes out into separate module
2020-03-10 Luke Kenneth Casso... add "done" signal to CompALU and LDSTCompALU to be...
2020-03-10 Luke Kenneth Casso... initial test LD comp unit in scoreboard
2020-03-09 Luke Kenneth Casso... try adding test memory store to LDSTCompUnit
2020-03-09 Luke Kenneth Casso... sort imports on scoreboard
2020-03-09 Luke Kenneth Casso... move all source directories to soc so that "import...