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syntax error correction
[soc.git]
/
src
/
soc
/
experiment
/
score6600.py
2020-07-22
Jacob Lifshay
Merge remote-tracking branch 'origin/master'
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2020-07-22
Jacob Lifshay
format code
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2020-07-12
Luke Kenneth Casso...
rename InternalOp to MicrOp
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2020-04-17
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-04-11
Luke Kenneth Casso...
spelling mistake
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2020-04-11
Luke Kenneth Casso...
holy cow, decode and run instruction works!
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2020-04-11
Luke Kenneth Casso...
test additional instructions
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2020-04-11
Luke Kenneth Casso...
adding immediates, tracking down a bug
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2020-04-10
Luke Kenneth Casso...
connect up ALU properly to pass full InternalOp subset...
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2020-04-10
Luke Kenneth Casso...
add 2nd add instruction to see what happens (success)
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2020-04-10
Luke Kenneth Casso...
eek, first cut at using POWER decoder2 in 6600 simulato...
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2020-04-08
Luke Kenneth Casso...
absolute imports
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2020-04-06
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-04-06
Jacob Lifshay
Merge branch 'fix-tests'
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2020-04-06
Jacob Lifshay
almost all tests work
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2020-03-23
Luke Kenneth Casso...
split sim classes out into separate module
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2020-03-10
Luke Kenneth Casso...
add "done" signal to CompALU and LDSTCompALU to be...
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2020-03-10
Luke Kenneth Casso...
initial test LD comp unit in scoreboard
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2020-03-09
Luke Kenneth Casso...
try adding test memory store to LDSTCompUnit
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2020-03-09
Luke Kenneth Casso...
sort imports on scoreboard
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2020-03-09
Luke Kenneth Casso...
move all source directories to soc so that "import...
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