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debugging decoding of SPRs (fast)
[soc.git]
/
src
/
soc
/
fu
/
div
/
2020-07-04
Luke Kenneth Casso...
reduce steps per stage to 8
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commitdiff
2020-07-03
Luke Kenneth Casso...
set only div/rem supported
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2020-07-02
Luke Kenneth Casso...
increase combinatorial stages to 8
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2020-07-02
Luke Kenneth Casso...
reduce DIV radix to 1
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2020-06-30
Luke Kenneth Casso...
code-morph on div pipeline
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commitdiff
2020-06-29
Luke Kenneth Casso...
use correct ALUHelpers in div test
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2020-06-29
Luke Kenneth Casso...
sort out syntax errors in div
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2020-06-29
Luke Kenneth Casso...
first unit test for div
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2020-06-19
Luke Kenneth Casso...
whitespace update
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2020-06-18
Jacob Lifshay
div pipe completed except for tests
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commitdiff
2020-06-18
Jacob Lifshay
finish code to calculate the 64-bit output of the div...
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2020-06-18
Jacob Lifshay
actually remove todo comment for manually checking...
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commitdiff
2020-06-18
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
tree
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commitdiff
2020-06-18
Jacob Lifshay
fix bug and manually check div overflow code against...
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commitdiff
2020-06-18
Jacob Lifshay
working on adding rest of stage classes for div pipeline
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commitdiff
2020-06-11
Luke Kenneth Casso...
rename get_sim_cr_a to get_wr_sim_cr_a for now
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2020-06-10
Luke Kenneth Casso...
re-do cookie-cut of alu test_pipe_caller.py over to...
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commitdiff
2020-06-10
Luke Kenneth Casso...
ilang file output change from alu_pipeline.il to div_pi...
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commitdiff
2020-06-10
Luke Kenneth Casso...
cookie-cut alu test_pipe_caller.py over
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commitdiff
2020-06-10
Jacob Lifshay
create div pipe setup stage
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2020-06-04
Luke Kenneth Casso...
use copy of FHDLTestCase
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2020-05-23
Luke Kenneth Casso...
add gitignore
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2020-05-22
Luke Kenneth Casso...
div probably uses ALU not Logical, needs double-checkin...
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commitdiff
2020-05-22
Luke Kenneth Casso...
rename Logical to Div in fu div test
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commitdiff
2020-05-22
Luke Kenneth Casso...
cookie-cut start on div pipe
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