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Allow the formal engine to perform a same-cycle result in the ALU
[soc.git]
/
src
/
soc
/
fu
/
mul
/ pre_stage.py
2022-02-27
Luke Kenneth Casso...
start on converting MUL and DIV pipelines to XLEN
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2021-10-10
Luke Kenneth Casso...
replace PartitionedSignal with SimdSignal
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2020-07-18
Luke Kenneth Casso...
missing conversion of DIV to Div
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2020-07-09
Luke Kenneth Casso...
add new stages etc. to get multiply working without...
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2020-07-08
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-07-06
Luke Kenneth Casso...
investigating mul pipeline
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2020-07-06
Luke Kenneth Casso...
first cut at mul test pipeline
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2020-07-06
Luke Kenneth Casso...
add first cut at fu mul pipeline
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