correction on single bit flags
[soc.git] / src /
2020-03-01 Luke Kenneth Casso... correction on single bit flags
2020-03-01 Luke Kenneth Casso... fix up syntax errors in power_decoder
2020-03-01 Luke Kenneth Casso... missing commas
2020-03-01 Luke Kenneth Casso... add some basic comments to PowerOp and PowerDecoder...
2020-03-01 Luke Kenneth Casso... separate out PowerOps from PowerDecoder, simplifies...
2020-02-29 Michael NolanAdd tests for minor_30 and minor_31 decoding tables
2020-02-29 Michael NolanAdd default case to decoder
2020-02-29 Michael NolanAdd fields from the ones in IBM's Microwatt
2020-02-29 Michael NolanAdd decoder/test for minor_19 field
2020-02-29 Michael NolanAdd code to download csv files from wiki if they don...
2020-02-29 Michael NolanMove enums to a separate file
2020-02-29 Michael NolanCorrect cry in field from a single bit to an enum
2020-02-29 Michael NolanCleanup testbench, add messages to assertions
2020-02-29 Michael NolanAdd in remaining fields from major decoder
2020-02-29 Michael NolanAdd signals for single bit flags in major.csv
2020-02-29 Michael NolanAdd input and output register selector fields
2020-02-29 Michael NolanMinor cleanup
2020-02-29 Michael NolanMove decoder.py to power_major_decoder.py
2020-02-29 Michael NolanAdd internal op field to major decoder
2020-02-29 Michael NolanBegin adding power ISA decoder
2020-01-25 Tobias Platenconvert ram tp modules
2020-01-24 Tobias Platentranslate slice_top and rab_slice from systemverilog...
2020-01-23 Tobias Platenadd more converted header files
2020-01-23 Tobias Platenbegin axi_rab to nmigen conversion
2020-01-17 Luke Kenneth Casso... update to new revision nmigen
2020-01-17 Luke Kenneth Casso... get familiar with tests again
2019-09-16 Tobias Platentlb_content now supports 512G pages
2019-09-11 Tobias Platenterapage lookup
2019-09-10 Tobias Platentlb_content update test
2019-09-09 Tobias Platenadd unittest for tlb_content.py
2019-08-25 Tobias Platenforgot to add one signal
2019-08-24 Tobias Platenadd is_512G to the data structure
2019-08-07 Tobias Platenpartial Unit Test for TLB
2019-08-04 Tobias Platentlb_test WIP
2019-08-01 Luke Kenneth Casso... move priority picker to nmutil
2019-07-25 Tobias PlatenMerge branch 'master' of https://git.libre-riscv.org...
2019-07-25 Tobias Platenfix UnusedElaboratable warning in TLB code
2019-07-24 Luke Kenneth Casso... add TLB elaboratable
2019-07-21 Tobias PlatenTLB testbench WIP
2019-07-21 isengaaraimplement page table lookup using 4 levels
2019-06-19 Luke Kenneth Casso... forgot to pull ld_o/st_o through from LDST CompUnits
2019-06-19 Luke Kenneth Casso... sort out address match global nomatch signal
2019-06-18 Luke Kenneth Casso... move mem into scoreboard (really should be outside...
2019-06-18 Luke Kenneth Casso... add separate read/write port
2019-06-18 Luke Kenneth Casso... whoops syntax error
2019-06-18 Luke Kenneth Casso... write out data only on go_write
2019-06-18 Luke Kenneth Casso... clarify comment
2019-06-18 Luke Kenneth Casso... add address and output mode from LDSTCUs
2019-06-18 Luke Kenneth Casso... sort out go_ld_i and go_st_i
2019-06-18 Luke Kenneth Casso... add temporary immediate-activation of go_addr on adr_re...
2019-06-17 Luke Kenneth Casso... add transitive accumulation of LD/STs into MDM
2019-06-17 Luke Kenneth Casso... remove TODO (done)
2019-06-16 Luke Kenneth Casso... fix several test imports, add Elaboratable
2019-06-16 Luke Kenneth Casso... fix test run errors
2019-06-15 Luke Kenneth Casso... rename match to nomatch, connect ld_i and st_i
2019-06-15 Luke Kenneth Casso... convert addr match into latched (SRLatch) version,...
2019-06-15 Luke Kenneth Casso... use new ready/valid to ALU in CompLDST
2019-06-10 Luke Kenneth Casso... start connecting memory function unit
2019-06-10 Luke Kenneth Casso... only set adr_rel_o on LD or ADD/SUB, must wait for...
2019-06-10 Luke Kenneth Casso... starting to run into things being broken in LD/ST Comp...
2019-06-10 Luke Kenneth Casso... properly set the number of integer ALUs (2 at the moment)
2019-06-10 Luke Kenneth Casso... set number of ALUs to 2
2019-06-10 Luke Kenneth Casso... test LD/ST issue
2019-06-10 Luke Kenneth Casso... add in ld/st operand pseudo-opcode
2019-06-10 Luke Kenneth Casso... add in a TestMemory class
2019-06-10 Luke Kenneth Casso... added in the LD/ST Comp Unit (not connected up yet...
2019-06-10 Luke Kenneth Casso... move MemFunctionUnits to separate module
2019-06-10 Luke Kenneth Casso... move FUMemMatchMatrix to mdm module
2019-06-09 Luke Kenneth Casso... link address matching inputs to outside MemMatrix,...
2019-06-09 Luke Kenneth Casso... bring in cancel array into FURegDepMatrix
2019-06-09 Luke Kenneth Casso... make partialaddrmatch a matrix
2019-06-08 Luke Kenneth Casso... rename variables
2019-06-08 Luke Kenneth Casso... add 2nd test for mem dependency, use FU-Regs and FU...
2019-06-08 Luke Kenneth Casso... convert Reg_Rsv and rest of FU_Reg Matrix to variable...
2019-06-08 Luke Kenneth Casso... use loop around src nums in FU Reg Matrix
2019-06-08 Luke Kenneth Casso... convert FU_RW_Pend accumulator to src-vector
2019-06-08 Luke Kenneth Casso... remove unneeded signals
2019-06-08 Luke Kenneth Casso... start propagating arrays of src regs up through depende...
2019-06-08 Luke Kenneth Casso... whitespace
2019-06-08 Luke Kenneth Casso... whoops use reduce(or_) not bool to merge bitwise src...
2019-06-08 Luke Kenneth Casso... use new array-based dep cell in dep matrix
2019-06-08 Luke Kenneth Casso... dependence cell to use arrays
2019-06-08 Luke Kenneth Casso... reordering connections on mem-dep matrices
2019-06-08 Luke Kenneth Casso... experiment connecting ld/st matrix to fu/mem one
2019-06-08 Luke Kenneth Casso... add fu-mem versions of fu-fu matrix and picker vec
2019-06-08 Luke Kenneth Casso... rename rsel vectors in mem dep cell
2019-06-08 Luke Kenneth Casso... add fu-mem dependency cell based on fu_dep_cell.py
2019-06-07 Luke Kenneth Casso... rename v_rd_rsel_o in dependence cell as well
2019-06-07 Luke Kenneth Casso... rename fu-regs rd/wr sel vector
2019-06-07 Luke Kenneth Casso... extend ld/st mem test
2019-06-07 Luke Kenneth Casso... start preliminary test of load/store dependency matrices
2019-06-07 Luke Kenneth Casso... continue miss_handler.py conversion
2019-06-06 Luke Kenneth Casso... add first conversion of ariane miss handler, WIP
2019-06-05 Luke Kenneth Casso... rename load_i and stor_i to ld_pend_i / st_pend_i,...
2019-06-05 Luke Kenneth Casso... add mirror copy of FU_Regs Dep Matrix, names changed...
2019-06-05 Luke Kenneth Casso... add addrgen comment
2019-06-03 Luke Kenneth Casso... add docstring for address match comparator
2019-06-03 Luke Kenneth Casso... add to docstring
2019-06-03 Luke Kenneth Casso... connect up LD/ST matrix properly
2019-06-03 Luke Kenneth Casso... add ldst_matrix.py back in, needs some work though
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