fix form and pseudo-code for fmvis, tests in 64-bit mode
[openpower-isa.git] / src /
2022-07-26 Konstantinos Marga... fix form and pseudo-code for fmvis, tests in 64-bit...
2022-07-26 Konstantinos Marga... fix fmvis decoder, it's now a 2-operand instruction
2022-07-26 Konstantinos Marga... Add fmvis instruction + tests, bug #887
2022-07-25 Dmitry Selyutinsvp64.py: fix alignment
2022-07-25 Dmitry Selyutinsvp64.py: update svindex operands
2022-07-23 Luke Kenneth Casso... dump output from pypowersim_fp
2022-07-21 Luke Kenneth Casso... whoops missing variables in new subfunction after
2022-07-21 Luke Kenneth Casso... add dsubstep to ISACaller
2022-07-21 Luke Kenneth Casso... sort out subvl unit test with expected results
2022-07-21 Luke Kenneth Casso... fix loopend conditions for subvectors in ISACaller
2022-07-20 Luke Kenneth Casso... rename substep to ssubstep, add dsubstep to SVP64State
2022-07-20 Luke Kenneth Casso... add first subvl unit test, subvl comes from
2022-07-18 Luke Kenneth Casso... move D-Immediate rewriting in ISACaller into separate...
2022-07-18 Luke Kenneth Casso... move inputs in ISACaller into get_input()
2022-07-18 Luke Kenneth Casso... move debug remap to ISACaller.remap_debug()
2022-07-18 Luke Kenneth Casso... whitespace and function-return code-morphing in ISACaller
2022-07-18 Luke Kenneth Casso... move another function in ISACaller (check_write)
2022-07-18 Luke Kenneth Casso... begin function split in ISACaller
2022-07-18 Luke Kenneth Casso... remove duplicate code create ISACaller.advance_svstate_...
2022-07-18 Luke Kenneth Casso... add SUBVL (substep) support to PowerDecoder2 and to...
2022-07-18 Luke Kenneth Casso... add substep getter/setter to SVP64State
2022-07-18 Luke Kenneth Casso... rename SVSTATE.svstep to SVSTATE.substep to avoid
2022-07-16 Luke Kenneth Casso... simplify remapyield.py, skip shows the bit to be skipped
2022-07-14 Luke Kenneth Casso... got fed up of long list of ifs for manually decoded...
2022-07-12 Luke Kenneth Casso... add recognition of 0xNNN and 0bMMMM to sv/trans/svp64.py
2022-07-12 Luke Kenneth Casso... add FRS as destination to PowerDecoder2 DecodeOut
2022-07-11 Luke Kenneth Casso... add mm=1 svindex test, setting single targetted SVSHAPE
2022-07-11 Luke Kenneth Casso... fix issue in SelectableInt.__rsub__ causing truncation...
2022-07-11 Luke Kenneth Casso... fix issue in SelectableInt using slices involving Selec...
2022-07-11 Andrey MiroshnikovAdded insn initialisation for grev() func
2022-07-10 Luke Kenneth Casso... add yx svindex test, needed to compute size of 2nd dim
2022-07-10 Luke Kenneth Casso... Indexed SVSHAPE add bypass mode when dim sizes are 1
2022-07-10 Luke Kenneth Casso... add second svindex test, modulo 3
2022-07-10 Luke Kenneth Casso... fix svindex unit test, experiment setting dimensions
2022-07-10 Luke Kenneth Casso... fix SVSHAPE iterator for index case, stop deepcopy
2022-07-10 Luke Kenneth Casso... add new svindex sv.add test with arbitrary index map
2022-07-10 Luke Kenneth Casso... non-persistence enabled on svindex as well as svremap
2022-07-10 Luke Kenneth Casso... fix svindex pseudocode
2022-07-09 Luke Kenneth Casso... pass GPR to SVSHAPEs in ISACaller
2022-07-09 Luke Kenneth Casso... add gpr lookup in Indexed SVSHAPE iterator (no elwidths...
2022-07-09 Luke Kenneth Casso... rough unit test ahowing Index REMAP basically functiona...
2022-07-09 Luke Kenneth Casso... add support for Indexed mode in SVSHAPE
2022-07-06 Luke Kenneth Casso... add first stub of svindex pseudocode
2022-07-06 Dmitry Selyutinsvp64.py: allow macros as register names
2022-07-06 Dmitry Selyutinsvp64.py: generate registers
2022-07-06 Luke Kenneth Casso... add svindex to power_enums.py, minor_22.csv
2022-07-06 Luke Kenneth Casso... convert Logical svp64_cases.py to new vector reg form
2022-07-06 Luke Kenneth Casso... convert ALU svp64_cases.py to new vector reg form
2022-07-06 Luke Kenneth Casso... converted test_caller_svstate.py to new reg format
2022-07-05 Andrey Miroshnikovconvert test_caller_svp64.py to new vector numbering...
2022-07-05 Andrey Miroshnikovconvert test_caller_svp64_predication.py to new vector...
2022-07-05 Andrey Miroshnikovconvert test_caller_svp64_ldst.py to new vector numberi...
2022-07-05 Andrey MiroshnikovUpdated the nmigen.sim import
2022-07-05 Andrey Miroshnikovconvert test_caller_svp64_fft.py to new vector numberin...
2022-07-05 Andrey Miroshnikovconvert test_caller_svp64_bc.py to new vector numbering...
2022-07-05 Andrey Miroshnikovconvert test_caller_svp64_dct.py to new vector numberin...
2022-07-05 Luke Kenneth Casso... converted test_caller_svp64_matrix.py to new reg format
2022-07-05 Luke Kenneth Casso... converted test_caller_svp64_fp.py to new reg format
2022-07-05 Luke Kenneth Casso... converted test_caller_svp64_mapreduce.py to new reg...
2022-07-05 Luke Kenneth Casso... convert test_caller_setvl.py to new vector numbering...
2022-07-05 Luke Kenneth Casso... add "*%" and "*" vector-numbering convention
2022-07-05 Luke Kenneth Casso... add note about bug #884 new reg vector naming convention
2022-07-05 Luke Kenneth Casso... add regression test for completely borked value from...
2022-07-05 Luke Kenneth Casso... take deepcopy of regs passed in to avoid accidental...
2022-07-02 Luke Kenneth Casso... add setvl CTR tests, fix CTR mode
2022-07-02 Luke Kenneth Casso... setvl has new CTR mode, making room in encoding needed
2022-06-30 Luke Kenneth Casso... do CSV isatables explicitly in sv_analysis.py
2022-06-30 Luke Kenneth Casso... explicit output of opcode_regs_deduped in mdwn table...
2022-06-28 Luke Kenneth Casso... add recognition of "sv." to pysvp64asm
2022-06-28 Luke Kenneth Casso... remove qemu co-simulation, dump output expected results
2022-06-26 Luke Kenneth Casso... add predicate mask test svstep
2022-06-26 Luke Kenneth Casso... whoops svp64.py testing wrong variable on sv.svstep
2022-06-26 Luke Kenneth Casso... add predicated srcstep
2022-06-26 Luke Kenneth Casso... make svstep output srcstep/dststep, basically viota
2022-06-26 Luke Kenneth Casso... rename SVRM *field* to SVrm to avoid a name-clash with
2022-06-26 Dmitry Selyutinsvp64.py: decrement SVd operand
2022-06-26 Dmitry Selyutinsvp64.py: fix ignored field range
2022-06-26 Dmitry Selyutinsvp64.py: drop commented code
2022-06-26 Dmitry Selyutinsvp64.py: fix fsins/fcoss X-FORM
2022-06-26 Luke Kenneth Casso... again fix number of arguments to svremap,
2022-06-26 Luke Kenneth Casso... whitespace
2022-06-26 Luke Kenneth Casso... test_caller_svstate.py: end-of-loop condition sets...
2022-06-26 Luke Kenneth Casso... svp64_matrix.py svremap reduce to 7 args from 8 (again)
2022-06-26 Luke Kenneth Casso... svremap only takes 7 args not 8, same as in svp64_fft.py
2022-06-26 Luke Kenneth Casso... one too many arguments to svremap in svp64_fft.py test
2022-06-26 Luke Kenneth Casso... whoops hack-use of DOUBLE2SINGLE in test_caller_transce...
2022-06-26 Luke Kenneth Casso... svp64.py: sync SVRM-Form used for svshape
2022-06-26 Luke Kenneth Casso... svp64.py: fix svshape and setvl plus couple of oddities
2022-06-26 Luke Kenneth Casso... svp64.py: add -FORM headers to more functions
2022-06-26 Luke Kenneth Casso... svp64.py: fix bmask entry
2022-06-26 Dmitry Selyutinsvp64.py: group 32-bit instructions into the table
2022-06-26 Dmitry Selyutinsvp64.py: align indentation
2022-06-26 Luke Kenneth Casso... add test case for kaivb to jump to 0x2700
2022-06-26 Luke Kenneth Casso... add TrapTestCase for KAIVB
2022-06-26 Luke Kenneth Casso... hmm do expected state in rfid trap case
2022-06-25 Luke Kenneth Casso... correct input example for SOF case_3_bmask
2022-06-25 Andrey MiroshnikovAdded sif/sof
2022-06-25 Luke Kenneth Casso... corrections to test cases, it is not quite
2022-06-25 Luke Kenneth Casso... update comments in av_cases.py test_1_bmask
2022-06-24 Andrey MiroshnikovAdded second bmask test case, designed to be multi...
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