soc.git
4 years agoHave lsmem handle stall and valid signals correctly
Michael Nolan [Wed, 24 Jun 2020 18:18:42 +0000 (14:18 -0400)]
Have lsmem handle stall and valid signals correctly

4 years agoUpdate comments on LoadStoreUnitInterface again
Michael Nolan [Wed, 24 Jun 2020 18:03:12 +0000 (14:03 -0400)]
Update comments on LoadStoreUnitInterface again

4 years agoUpdate comments on LoadStoreUnitInterface
Michael Nolan [Wed, 24 Jun 2020 17:46:20 +0000 (13:46 -0400)]
Update comments on LoadStoreUnitInterface

4 years agoAdd handling of byte reads and writes
Michael Nolan [Wed, 24 Jun 2020 17:16:13 +0000 (13:16 -0400)]
Add handling of byte reads and writes

4 years agoAdd more complete testbench for lsmem.py
Michael Nolan [Wed, 24 Jun 2020 17:09:10 +0000 (13:09 -0400)]
Add more complete testbench for lsmem.py

4 years agoSuper basic first try of testmem with load store unit interface
Michael Nolan [Wed, 24 Jun 2020 16:59:40 +0000 (12:59 -0400)]
Super basic first try of testmem with load store unit interface

4 years agomove comments to minerva LoadStoreInterface
Luke Kenneth Casson Leighton [Wed, 24 Jun 2020 15:53:13 +0000 (16:53 +0100)]
move comments to minerva LoadStoreInterface

4 years agoimport minerva and use LoadStoreUnitInterface
Luke Kenneth Casson Leighton [Wed, 24 Jun 2020 15:40:08 +0000 (16:40 +0100)]
import minerva and use LoadStoreUnitInterface

4 years agoAdd specification for load store interface
Michael Nolan [Wed, 24 Jun 2020 15:28:11 +0000 (11:28 -0400)]
Add specification for load store interface

4 years agomodify PortInterface so subfields include the port's name
Michael Nolan [Tue, 23 Jun 2020 17:47:17 +0000 (13:47 -0400)]
modify PortInterface so subfields include the port's name

4 years agoannoying error in latest nmigen
Luke Kenneth Casson Leighton [Tue, 23 Jun 2020 16:10:44 +0000 (17:10 +0100)]
annoying error in latest nmigen

4 years agoTstL0CacheBuffer returns array of ports differently now
Luke Kenneth Casson Leighton [Tue, 23 Jun 2020 15:47:54 +0000 (16:47 +0100)]
TstL0CacheBuffer returns array of ports differently now

4 years agoremove unused module
Luke Kenneth Casson Leighton [Mon, 22 Jun 2020 19:34:20 +0000 (20:34 +0100)]
remove unused module

4 years agosimplified L0CacheBuffer down to a "PortInterface Arbiter"
Luke Kenneth Casson Leighton [Mon, 22 Jun 2020 19:24:02 +0000 (20:24 +0100)]
simplified L0CacheBuffer down to a "PortInterface Arbiter"

4 years agoadd TestMemoryPortInterface class which is designed to replace L0CacheBuffer in
Luke Kenneth Casson Leighton [Mon, 22 Jun 2020 12:45:11 +0000 (13:45 +0100)]
add TestMemoryPortInterface class which is designed to replace L0CacheBuffer in
unit tests, allowing L0CacheBuffer to be developed on its own terms

4 years agocomments for LDST CompUnit test
Luke Kenneth Casson Leighton [Mon, 22 Jun 2020 12:06:34 +0000 (13:06 +0100)]
comments for LDST CompUnit test

4 years agoenable byte-reverse in CompLDSTUnit test
Luke Kenneth Casson Leighton [Mon, 22 Jun 2020 12:02:07 +0000 (13:02 +0100)]
enable byte-reverse in CompLDSTUnit test

4 years agoremove CompLDSTOpSubset, replace with just data_len.
Luke Kenneth Casson Leighton [Mon, 22 Jun 2020 11:12:10 +0000 (12:12 +0100)]
remove CompLDSTOpSubset, replace with just data_len.

4 years agomove BE/LE byte-reverse into LDSTCompUnit
Luke Kenneth Casson Leighton [Mon, 22 Jun 2020 10:49:41 +0000 (11:49 +0100)]
move BE/LE byte-reverse into LDSTCompUnit

4 years agoexpand Memory width to 64 and granularity to 16 in SRAM test
Luke Kenneth Casson Leighton [Sat, 20 Jun 2020 12:28:35 +0000 (13:28 +0100)]
expand Memory width to 64 and granularity to 16 in SRAM test

4 years agoadd asserts to check data output is correct
Luke Kenneth Casson Leighton [Sat, 20 Jun 2020 12:16:00 +0000 (13:16 +0100)]
add asserts to check data output is correct

4 years agoadd test_sram_wishbone.py
Luke Kenneth Casson Leighton [Sat, 20 Jun 2020 11:55:26 +0000 (12:55 +0100)]
add test_sram_wishbone.py
https://bugs.libre-soc.org/show_bug.cgi?id=382

4 years agoAdd code, commented-out, for TRAP so as to not break test_caller.py
colepoirier [Sat, 20 Jun 2020 01:30:54 +0000 (18:30 -0700)]
Add code, commented-out, for TRAP so as to not break test_caller.py

4 years agowhitespace update
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 21:30:01 +0000 (22:30 +0100)]
whitespace update

4 years agomove trunc_div and trunc_rem to nmutil
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 21:16:55 +0000 (22:16 +0100)]
move trunc_div and trunc_rem to nmutil

4 years agoadd comments on trunc_div and trunc_rem
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 20:29:30 +0000 (21:29 +0100)]
add comments on trunc_div and trunc_rem

4 years agoadd divide-by-zero test to test_div_sim.py
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 16:49:32 +0000 (17:49 +0100)]
add divide-by-zero test to test_div_sim.py

4 years agoadd docstring comment for SelectableInt
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 14:39:04 +0000 (15:39 +0100)]
add docstring comment for SelectableInt

4 years agoadd test_0_moduw and correct name to trunc_rem
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 14:30:45 +0000 (15:30 +0100)]
add test_0_moduw and correct name to trunc_rem

4 years agoadd abs SelectableInt unit test (very quick)
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 14:27:25 +0000 (15:27 +0100)]
add abs SelectableInt unit test (very quick)

4 years agoadd SelectableInt.abs
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 14:25:04 +0000 (15:25 +0100)]
add SelectableInt.abs
https://bugs.libre-soc.org/show_bug.cgi?id=324#c19

4 years agoadd another bad hack in parser.py which identifies "undefined" slice assignment
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 14:21:15 +0000 (15:21 +0100)]
add another bad hack in parser.py which identifies "undefined" slice assignment

4 years agoadd in really bad hack which calls trunc_div or trunc_mod
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 14:14:37 +0000 (15:14 +0100)]
add in really bad hack which calls trunc_div or trunc_mod
https://bugs.libre-soc.org/show_bug.cgi?id=324#c16

4 years agoadd trunc_div and trunch_rem to decoder helpers
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 14:03:28 +0000 (15:03 +0100)]
add trunc_div and trunch_rem to decoder helpers
https://bugs.libre-soc.org/show_bug.cgi?id=324

4 years agoauto-assign needs to use concat / selectconcat
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 13:01:39 +0000 (14:01 +0100)]
auto-assign needs to use concat / selectconcat

4 years agowhoops detected page name wrong, for special case fixedshift
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 12:50:13 +0000 (13:50 +0100)]
whoops detected page name wrong, for special case fixedshift

4 years agobit of a mess. getting carry recognised and output for shiftrot
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 12:45:01 +0000 (13:45 +0100)]
bit of a mess.  getting carry recognised and output for shiftrot
was interfering with fixedarith carry "implicit" computation.
had to special-case this in pywriter.py and parser.py

4 years agoadd auto-assign mode detecting uninitialised variable slices
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 12:08:18 +0000 (13:08 +0100)]
add auto-assign mode detecting uninitialised variable slices

4 years agodiv needs to be floordiv
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 10:36:12 +0000 (11:36 +0100)]
div needs to be floordiv

4 years agoadd true and floor div to SelectableInt
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 09:54:14 +0000 (10:54 +0100)]
add true and floor div to SelectableInt

4 years agoadd simulator test for divw
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 09:49:20 +0000 (10:49 +0100)]
add simulator test for divw

4 years agodo mix-in for test_sim.py so that jacob can write some div tests without
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 02:06:41 +0000 (03:06 +0100)]
do mix-in for test_sim.py so that jacob can write some div tests without
having to run all the other ones

4 years agoadd TODO comments to upgrade L0CacheBuffer to a new TestMemoryLoadStoreUnit
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 02:00:58 +0000 (03:00 +0100)]
add TODO comments to upgrade L0CacheBuffer to a new TestMemoryLoadStoreUnit

4 years agoparameterise LoadStoreUnitInterface to be expandable
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 01:44:24 +0000 (02:44 +0100)]
parameterise LoadStoreUnitInterface to be expandable

4 years agodiv pipe completed except for tests
Jacob Lifshay [Thu, 18 Jun 2020 23:11:10 +0000 (16:11 -0700)]
div pipe completed except for tests

4 years agofinish code to calculate the 64-bit output of the div pipeline
Jacob Lifshay [Thu, 18 Jun 2020 22:47:12 +0000 (15:47 -0700)]
finish code to calculate the 64-bit output of the div pipeline

4 years agoactually remove todo comment for manually checking against instruction models
Jacob Lifshay [Thu, 18 Jun 2020 22:32:50 +0000 (15:32 -0700)]
actually remove todo comment for manually checking against instruction models

4 years agoMerge branch 'master' of ssh://git.libre-riscv.org:922/soc
Jacob Lifshay [Thu, 18 Jun 2020 22:31:14 +0000 (15:31 -0700)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc

4 years agofix bug and manually check div overflow code against instruction models
Jacob Lifshay [Thu, 18 Jun 2020 22:27:39 +0000 (15:27 -0700)]
fix bug and manually check div overflow code against instruction models

4 years agoenable general test cases in test_issuer
Luke Kenneth Casson Leighton [Thu, 18 Jun 2020 17:05:59 +0000 (18:05 +0100)]
enable general test cases in test_issuer

4 years agogot loop example operational by noting when PC fastreg changed
Luke Kenneth Casson Leighton [Thu, 18 Jun 2020 17:05:40 +0000 (18:05 +0100)]
got loop example operational by noting when PC fastreg changed

4 years agouse different way to pass instructions to test_issuer ISACaller
Luke Kenneth Casson Leighton [Thu, 18 Jun 2020 10:29:29 +0000 (11:29 +0100)]
use different way to pass instructions to test_issuer ISACaller

4 years agodebugging test_issuer.py general test cases
Luke Kenneth Casson Leighton [Thu, 18 Jun 2020 10:26:35 +0000 (11:26 +0100)]
debugging test_issuer.py general test cases

4 years agoget instructions immediately from assembly code
Luke Kenneth Casson Leighton [Thu, 18 Jun 2020 10:26:10 +0000 (11:26 +0100)]
get instructions immediately from assembly code

4 years agomove test_sim.py unit tests to different class (split)
Luke Kenneth Casson Leighton [Thu, 18 Jun 2020 10:06:16 +0000 (11:06 +0100)]
move test_sim.py unit tests to different class (split)

4 years agoslightly hacky way to keep an eye on the PC
Luke Kenneth Casson Leighton [Thu, 18 Jun 2020 09:58:18 +0000 (10:58 +0100)]
slightly hacky way to keep an eye on the PC

4 years agowhoops generate core ilang not TestIssuer
Luke Kenneth Casson Leighton [Thu, 18 Jun 2020 09:52:06 +0000 (10:52 +0100)]
whoops generate core ilang not TestIssuer

4 years agouse while / exception in test_compunit loop
Luke Kenneth Casson Leighton [Thu, 18 Jun 2020 09:50:47 +0000 (10:50 +0100)]
use while / exception in test_compunit loop

4 years agoinvestigating mtocrf/mtcrf issue
Luke Kenneth Casson Leighton [Thu, 18 Jun 2020 09:45:04 +0000 (10:45 +0100)]
investigating mtocrf/mtcrf issue

4 years agoworking on adding rest of stage classes for div pipeline
Jacob Lifshay [Thu, 18 Jun 2020 02:56:07 +0000 (19:56 -0700)]
working on adding rest of stage classes for div pipeline

4 years agoadd bug reference to mtocrf/mtcrf name decoding
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 19:43:08 +0000 (20:43 +0100)]
add bug reference to mtocrf/mtcrf name decoding

4 years agodecoding assembly instruction name, move to separate function
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 19:39:21 +0000 (20:39 +0100)]
decoding assembly instruction name, move to separate function

4 years agogetting sim instruction decoder to reproduce asm instruction disassembly
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 19:20:35 +0000 (20:20 +0100)]
getting sim instruction decoder to reproduce asm instruction disassembly

4 years agoupdate submodule
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 17:32:12 +0000 (18:32 +0100)]
update submodule

4 years agoadd comment/assembly decode in power enums
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 17:31:40 +0000 (18:31 +0100)]
add comment/assembly decode in power enums

4 years agoupdate test_sim.py to do a simple execution loop: decode-execute-decode-execute
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 16:46:33 +0000 (17:46 +0100)]
update test_sim.py to do a simple execution loop: decode-execute-decode-execute

4 years agoadd loop example, required a bit of munging.
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 16:10:21 +0000 (17:10 +0100)]
add loop example, required a bit of munging.

4 years agoget fu compunit test to use ISACaller instruction-memory
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 14:55:04 +0000 (15:55 +0100)]
get fu compunit test to use ISACaller instruction-memory

4 years agogot fed up of adding arguments to ISACaller / ISA, use *args and **kwargs
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 14:46:04 +0000 (15:46 +0100)]
got fed up of adding arguments to ISACaller / ISA, use *args and **kwargs

4 years agosplit execute and setup of ISACaller instruction execution
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 14:40:46 +0000 (15:40 +0100)]
split execute and setup of ISACaller instruction execution
into two phases

4 years agocomment ISACaller setup
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 14:24:27 +0000 (15:24 +0100)]
comment ISACaller setup

4 years agostart to add in independent execution into ISACaller
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 14:20:35 +0000 (15:20 +0100)]
start to add in independent execution into ISACaller

4 years agoadd a fake program counter to ISACaller
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 13:42:47 +0000 (14:42 +0100)]
add a fake program counter to ISACaller

4 years agouse an independent power decoder in ISACaller
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 13:42:33 +0000 (14:42 +0100)]
use an independent power decoder in ISACaller

4 years agoadd "respect_pc" boolean to ISACaller
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 13:20:06 +0000 (14:20 +0100)]
add "respect_pc" boolean to ISACaller

4 years agoadd optional instruction memory
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 13:07:59 +0000 (14:07 +0100)]
add optional instruction memory

4 years agosplit out TestIssuer into separate module
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 11:17:31 +0000 (12:17 +0100)]
split out TestIssuer into separate module

4 years agoremove unneeded yield
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 11:08:08 +0000 (12:08 +0100)]
remove unneeded yield

4 years agoenable all tests again in test_core.py and test_issuer.py
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 05:41:09 +0000 (06:41 +0100)]
enable all tests again in test_core.py and test_issuer.py

4 years agogot test_issuer FSM operating. bit of a hack
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 05:39:53 +0000 (06:39 +0100)]
got test_issuer FSM operating.  bit of a hack

4 years agodebugging test_issuer, getting FSM working
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 04:42:10 +0000 (05:42 +0100)]
debugging test_issuer, getting FSM working

4 years agooutput to issuer_simulator.vcd
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 04:14:40 +0000 (05:14 +0100)]
output to issuer_simulator.vcd

4 years agoadd first version unit test for TestIssuer
Luke Kenneth Casson Leighton [Tue, 16 Jun 2020 18:33:05 +0000 (19:33 +0100)]
add first version unit test for TestIssuer

4 years agoreduce instruction depth to 6 bits in TestIssuer
Luke Kenneth Casson Leighton [Tue, 16 Jun 2020 18:32:46 +0000 (19:32 +0100)]
reduce instruction depth to 6 bits in TestIssuer

4 years agomove debug statements to check function
Luke Kenneth Casson Leighton [Tue, 16 Jun 2020 18:21:20 +0000 (19:21 +0100)]
move debug statements to check function

4 years agohack LD/ST ad/st together, allow PC to be set externally
Luke Kenneth Casson Leighton [Tue, 16 Jun 2020 18:12:01 +0000 (19:12 +0100)]
hack LD/ST ad/st together, allow PC to be set externally

4 years agomove check regs in simple core to separate function
Luke Kenneth Casson Leighton [Tue, 16 Jun 2020 17:29:37 +0000 (18:29 +0100)]
move check regs in simple core to separate function

4 years agomove test core reg set up into separate function
Luke Kenneth Casson Leighton [Tue, 16 Jun 2020 17:24:43 +0000 (18:24 +0100)]
move test core reg set up into separate function

4 years agoset up a TestIssuer class with a FSM for doing instruction issue to simple core
Luke Kenneth Casson Leighton [Tue, 16 Jun 2020 17:18:20 +0000 (18:18 +0100)]
set up a TestIssuer class with a FSM for doing instruction issue to simple core

4 years agoadd ports to TestMemory
Luke Kenneth Casson Leighton [Tue, 16 Jun 2020 17:16:53 +0000 (18:16 +0100)]
add ports to TestMemory

4 years agoadd beginnings of TestIssuer class, to issue instructions to simple core
Luke Kenneth Casson Leighton [Tue, 16 Jun 2020 14:39:03 +0000 (15:39 +0100)]
add beginnings of TestIssuer class, to issue instructions to simple core

4 years agoweird: adding TestMemory with no port causes nmigen recursion-exceeded
Luke Kenneth Casson Leighton [Tue, 16 Jun 2020 13:00:12 +0000 (14:00 +0100)]
weird: adding TestMemory with no port causes nmigen recursion-exceeded

4 years agorefer to signals directly in Test Core
Luke Kenneth Casson Leighton [Tue, 16 Jun 2020 12:57:41 +0000 (13:57 +0100)]
refer to signals directly in Test Core

4 years agoadd test instruction memory SRAM
Luke Kenneth Casson Leighton [Tue, 16 Jun 2020 12:41:17 +0000 (13:41 +0100)]
add test instruction memory SRAM

4 years agoupdate popcount docstring
Luke Kenneth Casson Leighton [Tue, 16 Jun 2020 11:15:42 +0000 (12:15 +0100)]
update popcount docstring

4 years agostart trying to fill in some comments in Minerva L1 cache code
Luke Kenneth Casson Leighton [Mon, 15 Jun 2020 23:52:30 +0000 (00:52 +0100)]
start trying to fill in some comments in Minerva L1 cache code

4 years agowhitespace cleanup
Luke Kenneth Casson Leighton [Mon, 15 Jun 2020 20:56:24 +0000 (21:56 +0100)]
whitespace cleanup

4 years agoimports and syntax errors fixed (found test_cache.py)
Luke Kenneth Casson Leighton [Mon, 15 Jun 2020 20:55:39 +0000 (21:55 +0100)]
imports and syntax errors fixed (found test_cache.py)

4 years agomore whitespace
Luke Kenneth Casson Leighton [Mon, 15 Jun 2020 19:53:43 +0000 (20:53 +0100)]
more whitespace

4 years agomore whitespace on minerva (no unit tests, so cannot check it)
Luke Kenneth Casson Leighton [Mon, 15 Jun 2020 19:51:56 +0000 (20:51 +0100)]
more whitespace on minerva (no unit tests, so cannot check it)