i965/blorp: unit test compiling msaa-8 cms to cms

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/blorp: unit test compiling msaa-8 ums to cms

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/blorp: unit test compiling blend and scaled

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/blorp: allow unit tests to compile and dump assembly

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: dump the disassembly to the given file

instead of ignoring the argument and always dumping to
standard output.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/fs: allow fs-generator use without gl_fragment_program

Prepares the generator to accept hand-crafted blorp programs.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/fs: generate fs programs also without any 8-width instructions

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

freedreno/a3xx: fix blend state corruption issue

Using RMW on banked context registers is not safe.  The value read
could be the wrong one.  So if there has been a DRAW_IDX launched,
the RMW must be preceded by a WAIT_FOR_IDLE to ensure the read part
of RMW sees the correct value.

To avoid unnecessary WFI's, keep track if there is a need for WFI,
and only emit one if needed.  Furthermore, keep track if we even
need to update the register in the first place.

And to cut down on the amount of RMW to avoid excessive WFI's, at the
tiling/GMEM level we can always overwrite RB_RENDER_CONTROL, as the
state at beginning of draw/clear cmds (which we IB to) is always
undefined.  In the draw/clear commands, we always still use RMW (with
WFI if needed), but only if the register value actually changes.  (At
points where the current value cannot be known, the saved value is
reset to ~0, which includes bits outside of RBRC_DRAW_STATE, so there
never is chance for confusion.)

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno: prepare for hw binning

Actually assign VSC_PIPE's properly, which will be needed for tiling.
And introduce fd_tile for per-tile state (including the assignment of
tile to VSC_PIPE).  This gives us the proper pipe setup that we'll
need for hw binning pass, and also cleans things up a bit by not having
to pass so many parameters around.  And will also make it easier to
introduce different tiling patterns (since we may no longer render
tiles in a simple left-to-right top-to-bottom pattern).

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno: resync generated headers

Signed-off-by: Rob Clark <robclark@freedesktop.org>

r600g: fix SUMO2 pci id

0x9649 is sumo2, not sumo.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
CC: "9.2" "10.0" <mesa-stable@lists.freedesktop.org>

scons: Add system library linker flags on LLVM 3.5.

llvn-3.5svn r197664 split out the linker flags from ldflags to
system-libs.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>

r600/pipe: Stop leaking context->start_compute_cs_cmd.buf on EG/CM

Found while tracking down memory leaks in VDPAU playback

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
CC: "10.0" <mesa-stable@lists.freedesktop.org>

st/vdpau: Destroy context when initialization fails

Prevents a potential memory leak found when tracking down something else.

Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
CC: "10.0" <mesa-stable@lists.freedesktop.org>

radeon/llvm: Free target data at end of optimization

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
CC: "10.0" <mesa-stable@lists.freedesktop.org>

r600/compute: Use the correct FREE macro when deleting compute state

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
CC: "10.0" <mesa-stable@lists.freedesktop.org>

r600/compute: Free compiled kernels when deleting compute state

v2: Remove unnecessary null pointer check

CC: "10.0" <mesa-stable@lists.freedesktop.org>

radeon/compute: Stop leaking LLVMContexts in radeon_llvm_parse_bitcode

Previously we were creating a new LLVMContext every time that we called
radeon_llvm_parse_bitcode, which caused us to leak the context every time
that we compiled a CL program.

Sadly, we can't dispose of the LLVMContext at the point that it was being
created because evergreen_launch_grid (and possibly the SI equivalent) was
assuming that the context used to compile the kernels was still available.

Now, we'll create a new LLVMContext when creating EG/SI compute state, store
it there, and pass it to all of the places that need it.

The LLVM Context gets destroyed when we delete the EG/SI compute state.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
CC: "10.0" <mesa-stable@lists.freedesktop.org>

pipe_loader/sw: close dev->lib when initialization fails

Prevents a memory leak.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
CC: "10.0" <mesa-stable@lists.freedesktop.org>

clover: Remove unused variable

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
CC: "10.0" <mesa-stable@lists.freedesktop.org>

llvmpipe: use pipe_sampler_view_release() to avoid segfault

This fixes another case of faulting when freeing a pipe_sampler_view
that belongs to a previously destroyed context.

Cc: "10.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Jonathan Liu <net147@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

st/mesa: use pipe_sampler_view_release()

This fixes a crash where old_view->context was already freed in the
pipe_sampler_view_reference function contained in
src/gallium/auxiliary/utils/u_inlines.h. As a result, the
sampler_view_destroy function pointer contained 0xfeeefeee indicating
freed heap memory.

Cc: "10.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Jonathan Liu <net147@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

i915: Add support for gl_FragData[0] reads.

Similar to 556a47a2621073185be83a0a721a8ba93392bedb, without this reading from
gl_FragData[0] would cause a software fallback.

Bugzilla: https://bugs.winehq.org/show_bug.cgi?id=33964
Signed-off-by: Henri Verbeet <hverbeet@gmail.com>
Cc: 10.0 9.2 9.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

radeonsi: Use htile_buffer for depth only when there is no stencil.

Signed-off-by: Marek Olšák <marek.olsak@amd.com>

winsys/radeon: remove superfluous distinction of cases

Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>

mesa: inline r200 radeon texture format macros to facility search and replace

Signed-off-by: Mark Mueller <MarkKMueller@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>

mesa: Fix build to properly check for supported compiler flags

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=72708
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Lauri Kasanen <cand@gmx.com>

mesa: It is not possible to have GLSL < 1.20

This hasn't been possible for a long time.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: Clean up bad code formatting left from previous commit

Also s/_EXT// on enums that are now part of core.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: GL_EXT_packed_depth_stencil is not optional

Every driver supports it.  All current and future Gallium drivers always
support it, and all existing classic drivers support it.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

radeon: Sort list of enabled extensions

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

r200: Sort list of enabled extensions

Note that ARB_occlusion_query was previously enabled twice.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

glx: Simplify __glxGetMscRate, it only needs the screen, not a drawable

Useful in its own right, but also needed for adaptive vsync.

No regressions in the piglit glx-oml-sync-control-getmscrate test.

Signed-off-by: Lauri Kasanen <cand@gmx.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Tested-by: Ian Romanick <ian.d.romanick@intel.com>

dri3: Rename DRI3_MAX_BACK to DRI3_NUM_BACK

It is the maximum number of back buffers, but the name is confusing and is
easily read as the maximum back buffer index. Chage to DRI3_NUM_BACK to make
the intended usage a bit clearer.

Signed-off-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Set fast color clear mcs_state on newly allocated image miptrees

Just copying code from the dri2 path to set up the fast color clear state.

This also removes a couple of bogus intel_region_reference calls.

Signed-off-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Correct check for re-bound buffer in intel_update_image_buffer

The buffer-object is the persistent thing passed through the loader, so when
updating an image buffer, check to see if it is already bound to the provided
bo. The region, on the other hand, is allocated separately for the miptree,
and so will never be the same as that passed back from the loader.

Signed-off-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

dri3: Clean up struct dri3_drawable

Move the depth field up with width and height.

Remove unused previous_time and frames fields.

Signed-off-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

dri3: Free resources when drawable is destroyed.

Always nice to clean up after ourselves.

Signed-off-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

dri3: Switch to libxshmfence version 1.1

libxshmfence v1.0 foolishly used 'int32_t *' for the fence type, which
works when the fence is a linux futex. However, version 1.1
changes the exported datatype to 'struct xshmfence *'

Require libxshmfence version 1.1 and switch the API around.

Signed-off-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Use RED for depth texture formats rather than INTENSITY.

While looking through the documentation, I found this in the Sandybridge
PRM (Volume 4, Part 1, Page 140):
"Use of sample_c with SURFTYPE_CUBE surfaces is undefined with the
 following surface formats: I24X8_UNORM, L24X8_UNORM, A24X8_UNORM,
 I32_FLOAT, L32_FLOAT, A32_FLOAT."

I haven't observed this to be true, but it suggests that we may want to
use other formats.

We already perform DEPTH_TEXTURE_MODE swizzling in the shaders, and
don't rely on the surface format to splat things appropriately.  So
using RED should work just as well as INTENSITY.

A few notes about the formats:
- R24_UNORM_X8_TYPELESS has the exact same properties as I24X8_UNORM.
- R16_UNORM and R32_FLOAT are additionally supported as a render target,
  while the old I16_UNORM/I32_FLOAT formats are not.
- R32_FLOAT_X8X24_TYPELESS is not supported as a render target, while
  the old format (R32G32_FLOAT) was.  However, it shares the same
  properties as the formats we use for Z24, so it should suffice.

This makes translate_tex_format and brw_blorp_surface_info::set
a bit more similar.

No Piglit changes on Sandybridge or Ivybridge.  No oglconform changes on
Sandybridge.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965/gen6: Fix HiZ hang in WebGL Google Maps

Emitting flushes before depth and hiz resolves at the top of blorp's
state emission fixes the hang. Marchesin and I found the fix
experimentally, as opposed to adhering to a documented hardware
workaround.  A more minimal fix likely exists, but this gets the job
done.

Fixes HiZ hangs in the new WebGL Google maps on Sandybridge Chrome OS.
Tested by zooming in and out continuously for 2 hours.

This patch is based on
https://chromium.googlesource.com/chromiumos/overlays/chromiumos-overlay/+/8bc07bb70163c3706fb4ba5f980e57dc942f56dd

CC: mesa-stable@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=70740
Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Store QPitch in intel_mipmap_tree.

Broadwell allows us to specify an arbitrary value for QPitch, rather
than baking a specific formula into the hardware and requiring software
to lay things out to match.  The only restriction is that the software
provided QPitch needs to be large enough so successive array slices do
not overlap.

In order to support this flexibility, software needs to specify QPitch
in a bunch of packets.  Storing QPitch makes that easy, and allows us to
adjust it in a single place should we wish to change it in the future.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>

i965: Add support for Broadwell's new register types.

Broadwell introduces support for Q, UQ, and HF types.  It also extends
DF support to allow immediate values.

Irritatingly, although HF and DF both support immediates, they're
represented by a different value depending on the register file.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

i965: Add BRW_REGISTER_TYPE_DF.

Ivybridge, Baytrail, and Haswell support double float register types,
but do not support them as immediate values.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

i965: Abstract BRW_REGISTER_TYPE_* into an enum with unique values.

On released hardware, values 4-6 are overloaded.  For normal registers,
they mean UB/B/DF.  But for immediates, they mean UV/VF/V.

Previously, we just created #defines for each name, reusing the same
value.  This meant we could directly splat the brw_reg::type field into
the assembly encoding, which was fairly nice, and worked well.

Unfortunately, Broadwell makes this infeasible: the HF and DF types are
represented as different numeric values depending on whether the
source register is an immediate or not.

To preserve sanity, I decided to simply convert BRW_REGISTER_TYPE_* to
an abstract enum that has a unique value for each register type, and
write translation functions.  One nice benefit is that we can add
assertions about register files and generations.

I've chosen not to convert brw_reg::type to the enum, since converting
it caused a lot of trouble due to C++ enum rules (even though it's
defined in an extern "C" block...).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

i965: Decode three-source register types directly.

Three-source instructions use a different encoding for register types
(and have a much more limited set to choose from).

Previously, we translated those into BRW_REGISTER_TYPE_* values, then
reused the existing reg_encoding mapping.

Doing it directly is more straightforward and actually less code.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

i965: Disassemble UV types, not UB types.

UB types have never been supported as immediates.  On Gen4-5, register
encoding 4 is "Reserved."  On Gen6+, it means UV.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

i965: Add missing BRW_REGISTER_TYPE_UV.

Sandybridge added support for packed unsigned vectors.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

i965: Fix 3DSTATE_PUSH_CONSTANT_ALLOC_PS packet creation.

When adding geometry shader support, we accidentally reversed the size
and offset parameters.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Cc: "10.0" <mesa-stable@lists.freedesktop.org>

i965: Use {point_sprite,flat}_enable variable names instead of dw*.

Calling the local variables flat_enable and point_sprite_enable is
clearer than dw16 and such.  It also matches the names used in
calculate_attr_overrides, which computes them.

v2: Add /* dw16 */ and /* dw10 */ comments, requested by Jordan.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

i965: Zero out {point_sprite,flat}_enables in calculate_attr_overrides.

calculate_attr_overrides is responsible for computing the point sprite
and flat-shading enable bitfields.  It does so by OR'ing in a bunch of
bits.  However, it relied on the caller to set the initial value to
zero.  This is pretty fragile - if the caller neglects to zero out those
variables, then the enable bitfields end up full of garbage, which shows
up as random things being flat-shaded.

This patch moves the zero-initialization into calculate_attr_overrides,
so that the computation is completely in one place.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

i965: Delete bogus BRW_REGISTER_TYPE_HF define.

git blame ascribes this to the initial commit of the driver.

No released hardware has ever supported half float, according to the
documentation for SrcType in the ISA reference.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

Report that no function found if signature lookup is empty

If no function signature is found for a function name, report that the
function is not found instead of printing an empty list of candidates.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

Use line number information from entire function expression

This patch changes the error reporting behavior for incorrect function
invocation (triggered by match_function_by_name() unable to find a
matching function call) from using the line number information
associated to the function name term to using the line number
information of the entire function expression. Fixes bug #72264.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=72264
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: "10.0" <mesa-stable@lists.freedesktop.org>

radeonsi: Only scan pixel shaders for TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS

It's not relevant for other shader types.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

r600g: Fix spelling error

Trivial change, testing commit access

egl: break instead of looping after driver is found

Stop searching for a driver after success.

Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
Reviewed-By: Gong, Zhigang <zhigang.gong@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: Assert variable coming from get_variable() in get_current_attrib

Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: Add asserts into emit_fog_instructions

Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

glx: Fix two identical null check errors in driSet/GetInterval

Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

st_glsl_to_tgsi: add support for prim id fragment shader input

For GLSL 1.50 we can get frag shaders with primitive id as an
input, add support to the translator for this.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

mesa: add asserts in load_texunit_bumpmap

In load_texunit_bumpmap tc_array is asserted so lets assert
rot_mat_0 and rot_mat_1 also which are coming from same path.

Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

glx: add missing null check in dri2_bind_tex_image

Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: minor simplification in _mesa_es3_error_check_format_and_type()

The type_valid local was set to true and never changed.

glx: Add missing null check in dri2CreateDrawable

Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: Verify memory allocations success in _mesa_PushAttrib

Check for malloc() returning null to fix Klocwork warnings.
Minor clean-ups by BrianP.

Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: Verify memory allocations success in _mesa_PushClientAttrib

Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: Change save_attrib_data() to return boolean

Change save_attrib_data() to return true/false depending on success.

Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: add API/extension checks for 3-component texture buffer formats

The GL_RGB32F, GL_RGB32UI and GL_RGB32I texture buffer formats are
only supposed to be allowed if the GL_ARB_texture_buffer_object_rgb32
extension is supported.  Note that the texture buffer extensions
require a core profile.  This patch adds those checks.

Fixes the soon-to-be-added
arb_clear_buffer_object-negative-bad-internalformat piglit test.

mesa: 78-column wrapping in extensions.c

mesa: Cleanup mesa/main/bufferobj.h

Column wrapping and space between lines.

Reviewed-by: Brian Paul <brianp@vmware.com>

Modify release notes to include ARB_clear_buffer_object extension

Reviewed-by: Brian Paul <brianp@vmware.com>

Add ARB_clear_buffer_object to list of supported extensions

Reviewed-by: Brian Paul <brianp@vmware.com>

st/mesa: plug in default buffer object driver functions

In particular, this plugs in the new ClearBufferSubData() fallback
driver function.

mesa: Implement functions for clear_buffer_object extensions

Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: Modify get_buffer() to allow for a variable error code

Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: Add bufferobj_range_mapped function

Add function to test if the buffer is already mapped and if so,
if the mapped range overlaps the given range.
Modify the _mesa_InvalidateBufferSubData function to use
the new function.

Enable buffer_object_subdata_range_good() to use bufferobj_range_mapped

Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: get_texbuffer_format(): differentiate between core and compat context

alpha, lumincance and intensity formats are illegal in a core context.
Add a check to return MESA_FORMAT_NONE if one of those is requested within
a core context.

Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: Modify format validation to check for extension not context version

Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: Make validate_texbuffer_format function available externally

 - change storage class from static to extern
 - rename validate_texbuffer_format to _mesa_validate_texbuffer_format

Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: Add infrastructure for GL_ARB_clear_buffer_object

 - add xml file for extension
 - add reference in gl_API.xml
 - add pointer to device driver function table (dd.h)
 - update dispatch_sanity.cpp

Reviewed-by: Brian Paul <brianp@vmware.com>

clover: Append buffers that use CL_MEM_USE_HOST_PTR.

Specs say it's legal for implementations to use internal copies, and
the write synchronization seems to work.  Fixes clCreateBuffer
(together with previous patches) and buffer-flags piglits.

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Acked-by: Francisco Jerez <currojerez@riseup.net>

clover: Add parameter checks to clCreateBuffer.

v2: Use fewer if statements and functional tricks instead of single-use method,
    suggested by Francisco Jerez.
    Squash two small patches into one.

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

configure.ac: remove -fcolor-diagnostics from LLVM flags

When LLVM is build with Clang, "llvm-config --cxxflags" contains the
-fcolor-diagnostics flag. It is not recognized by gcc and the build
fails. Fix by removing the flag.

Signed-off-by: Markus Trippelsdorf <markus@trippelsdorf.de>
Signed-off-by: Brian Paul <brianp@vmware.com>

st/dri: Check for kernel support before enabling fd sharing v2

The dri2 state tracker is checking for driver support before enabling
dri2ImageExtension version 7. This commit adds a check that also the
kernel driver supports fd sharing through prime.

Note that this adds a libdrm dependency on dri2.c.

v2: Removed unnecessary clamping of bool expression

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Christopher James Halse Rogers <christopher.halse.rogers@canonical.com>

radeonsi: set CB_DISABLE if the color mask is 0

Also needed for the DB in-place decompression according to hw docs.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

radeonsi: add the htile buffer to the CS ioctl buffer list

This may fix the GPU crashes.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

glsl: Replace _mesa_glsl_parser_targets enum with gl_shader_type.

These enums were redundant.

Reviewed-by: Brian Paul <brianp@vmware.com>

main: Move MESA_SHADER_TYPES outside of gl_shader_type enum.

This will avoid spurious compiler warnings in the patch that follows.

Reviewed-by: Brian Paul <brianp@vmware.com>

glsl: Don't return bad values from _mesa_shader_type_to_index.

This will avoid compiler warnings in the patch that follows.  There
should be no user-visible effect because the change only affects the
behaviour when an invalid enum is passed to
_mesa_shader_type_to_index(), and that can only happen if there is a
bug elsewhere in Mesa.

Reviewed-by: Brian Paul <brianp@vmware.com>

swrast: silence driContextSetFlags() parameter type warning

st/dri: fix compiler warning for driCopySubBufferExtension

radeonsi: improve HiZ precision for less and lequal depth functions

r600g needs this too.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: make DB_RENDER_OVERRIDE an invariant register

All this cruft was ported from r600g and isn't needed on SI and later
according to hw docs. If we implemented HiS, we would set it to 0.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: flush HTILE when appropriate

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

st/xa: Add new map flags

Replicate some of the gallium pipe transfer functionality.
Also bump minor to signal availability of this feature.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Jakob Bornecrantz <jakob@vmware.com>

Haiku: Add in public GL kit headers

* These make up the base of what C++ GL Haiku applications
  use for 3D rendering.
* Not placed in includes/GL to prevent Haiku headers from
  getting installed on non-Haiku systems.

Acked-by: Brian Paul <brianp@vmware.com>

freedreno: dummy-draw workaround for a320

Fixes gpu lockups in supertuxkart.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

r600g: expose 32-bit integer vertex formats

This advertises GL_ARB_texture_buffer_object_rgb32.

radeonsi: move invariant regs to si_init_config

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>