Luke Kenneth Casson Leighton [Sun, 5 Aug 2018 09:19:03 +0000 (10:19 +0100)]
minor cleanup, include epydoc in Makefile
Luke Kenneth Casson Leighton [Fri, 3 Aug 2018 09:20:14 +0000 (10:20 +0100)]
fix name in mkConnection
Luke Kenneth Casson Leighton [Fri, 3 Aug 2018 09:18:39 +0000 (10:18 +0100)]
do config start addresses
Luke Kenneth Casson Leighton [Fri, 3 Aug 2018 08:57:01 +0000 (09:57 +0100)]
remove tab indentation
Luke Kenneth Casson Leighton [Fri, 3 Aug 2018 08:32:00 +0000 (09:32 +0100)]
pep8 cleanup
Luke Kenneth Casson Leighton [Fri, 3 Aug 2018 08:31:22 +0000 (09:31 +0100)]
output #defines based on config memory maps
Luke Kenneth Casson Leighton [Fri, 3 Aug 2018 08:01:16 +0000 (09:01 +0100)]
whoops typo in binary number
Luke Kenneth Casson Leighton [Fri, 3 Aug 2018 08:00:27 +0000 (09:00 +0100)]
write out fast instance defines separately
Luke Kenneth Casson Leighton [Fri, 3 Aug 2018 07:56:44 +0000 (08:56 +0100)]
split out memory map defines
Luke Kenneth Casson Leighton [Fri, 3 Aug 2018 06:47:33 +0000 (07:47 +0100)]
read config mux and output to slow_peripherals.bsv
Sneha Madle [Thu, 2 Aug 2018 13:37:23 +0000 (19:07 +0530)]
decided to use new spec
Sneha Madle [Thu, 2 Aug 2018 13:16:35 +0000 (18:46 +0530)]
default MUX config to microtest
Luke Kenneth Casson Leighton [Fri, 3 Aug 2018 05:18:05 +0000 (06:18 +0100)]
set up defaults for mux
Luke Kenneth Casson Leighton [Fri, 3 Aug 2018 05:15:24 +0000 (06:15 +0100)]
set up defaults for mux
Luke Kenneth Casson Leighton [Fri, 3 Aug 2018 04:57:56 +0000 (05:57 +0100)]
add peripherals makefile template
Luke Kenneth Casson Leighton [Fri, 3 Aug 2018 04:23:19 +0000 (05:23 +0100)]
config default needs to be a dict not a list
Neel [Fri, 3 Aug 2018 04:25:23 +0000 (09:55 +0530)]
pinspecs now take mux width
Luke Kenneth Casson Leighton [Thu, 2 Aug 2018 11:31:32 +0000 (12:31 +0100)]
add rst0 to sdram
Luke Kenneth Casson Leighton [Thu, 2 Aug 2018 10:40:49 +0000 (11:40 +0100)]
try different clock combination
Luke Kenneth Casson Leighton [Thu, 2 Aug 2018 10:21:15 +0000 (11:21 +0100)]
try different clock for sdr
Luke Kenneth Casson Leighton [Thu, 2 Aug 2018 10:13:21 +0000 (11:13 +0100)]
fix sdmmc interface
Luke Kenneth Casson Leighton [Thu, 2 Aug 2018 09:43:19 +0000 (10:43 +0100)]
rename sd to mmc
Luke Kenneth Casson Leighton [Thu, 2 Aug 2018 09:38:26 +0000 (10:38 +0100)]
remove accidental exit
Luke Kenneth Casson Leighton [Thu, 2 Aug 2018 09:32:29 +0000 (10:32 +0100)]
rename sd to mmc
Luke Kenneth Casson Leighton [Thu, 2 Aug 2018 09:03:24 +0000 (10:03 +0100)]
remove SDRAM typedef
Luke Kenneth Casson Leighton [Thu, 2 Aug 2018 08:52:15 +0000 (09:52 +0100)]
add memory map configs
Luke Kenneth Casson Leighton [Thu, 2 Aug 2018 06:36:29 +0000 (07:36 +0100)]
fix dedicated outputs, hard-code enable line to 1
Luke Kenneth Casson Leighton [Thu, 2 Aug 2018 06:36:18 +0000 (07:36 +0100)]
add SDRAM clock output
Luke Kenneth Casson Leighton [Thu, 2 Aug 2018 06:35:56 +0000 (07:35 +0100)]
add SDRAM clock output
Luke Kenneth Casson Leighton [Thu, 2 Aug 2018 06:17:22 +0000 (07:17 +0100)]
add comments
Luke Kenneth Casson Leighton [Thu, 2 Aug 2018 06:13:30 +0000 (07:13 +0100)]
pass over config in json format
Luke Kenneth Casson Leighton [Thu, 2 Aug 2018 06:03:01 +0000 (07:03 +0100)]
convert to dictionary spec system
Luke Kenneth Casson Leighton [Wed, 1 Aug 2018 12:24:42 +0000 (13:24 +0100)]
AddingPeripherals.mdwn
Luke Kenneth Casson Leighton [Wed, 1 Aug 2018 12:22:31 +0000 (13:22 +0100)]
AddingPeripherals.mdwn
Luke Kenneth Casson Leighton [Wed, 1 Aug 2018 11:49:17 +0000 (12:49 +0100)]
AddingPeripherals.mdwn
Luke Kenneth Casson Leighton [Wed, 1 Aug 2018 11:21:14 +0000 (12:21 +0100)]
AddingPeripherals.mdwn
Luke Kenneth Casson Leighton [Wed, 1 Aug 2018 11:04:51 +0000 (12:04 +0100)]
AddingPeripherals.mdwn
Luke Kenneth Casson Leighton [Wed, 1 Aug 2018 11:02:18 +0000 (12:02 +0100)]
AddingPeripherals.mdwn
Luke Kenneth Casson Leighton [Wed, 1 Aug 2018 10:39:50 +0000 (11:39 +0100)]
AddingPeripherals.mdwn
Luke Kenneth Casson Leighton [Wed, 1 Aug 2018 10:19:30 +0000 (11:19 +0100)]
AddingPeripherals.mdwn
Luke Kenneth Casson Leighton [Wed, 1 Aug 2018 09:54:46 +0000 (10:54 +0100)]
add sdram dual axi4 configs
Luke Kenneth Casson Leighton [Wed, 1 Aug 2018 09:08:06 +0000 (10:08 +0100)]
AddingPeripherals.mdwn
Luke Kenneth Casson Leighton [Wed, 1 Aug 2018 09:07:19 +0000 (10:07 +0100)]
AddingPeripherals.mdwn
Luke Kenneth Casson Leighton [Wed, 1 Aug 2018 09:05:19 +0000 (10:05 +0100)]
AddingPeripherals.mdwn
Luke Kenneth Casson Leighton [Wed, 1 Aug 2018 08:49:13 +0000 (09:49 +0100)]
AddingPeripherals.mdwn
Luke Kenneth Casson Leighton [Wed, 1 Aug 2018 08:01:12 +0000 (09:01 +0100)]
AddingPeripherals.mdwn
Luke Kenneth Casson Leighton [Wed, 1 Aug 2018 07:40:45 +0000 (08:40 +0100)]
AddingPeripherals.mdwn
Luke Kenneth Casson Leighton [Wed, 1 Aug 2018 07:39:09 +0000 (08:39 +0100)]
AddingPeripherals.mdwn
Luke Kenneth Casson Leighton [Wed, 1 Aug 2018 07:38:53 +0000 (08:38 +0100)]
add sdram interface, remove unneeded import
Luke Kenneth Casson Leighton [Wed, 1 Aug 2018 07:30:53 +0000 (08:30 +0100)]
remove unneeded imports
Luke Kenneth Casson Leighton [Wed, 1 Aug 2018 07:30:19 +0000 (08:30 +0100)]
AddingPeripherals.mdwn
Luke Kenneth Casson Leighton [Wed, 1 Aug 2018 07:30:04 +0000 (08:30 +0100)]
AddingPeripherals.mdwn
Luke Kenneth Casson Leighton [Wed, 1 Aug 2018 07:29:56 +0000 (08:29 +0100)]
add sdr as fast-bus peripheral
Luke Kenneth Casson Leighton [Wed, 1 Aug 2018 07:09:31 +0000 (08:09 +0100)]
rename sd to mmc to avoid name clash with sdram
Luke Kenneth Casson Leighton [Wed, 1 Aug 2018 07:05:10 +0000 (08:05 +0100)]
AddingPeripherals.mdwn
Luke Kenneth Casson Leighton [Wed, 1 Aug 2018 06:57:27 +0000 (07:57 +0100)]
change spec for SDR DQM to +
Luke Kenneth Casson Leighton [Wed, 1 Aug 2018 06:52:37 +0000 (07:52 +0100)]
whoops name wrong
Luke Kenneth Casson Leighton [Wed, 1 Aug 2018 06:11:44 +0000 (07:11 +0100)]
add sdram peripheral to i_class
Luke Kenneth Casson Leighton [Wed, 1 Aug 2018 05:50:12 +0000 (06:50 +0100)]
AddingPeripherals.mdwn
Luke Kenneth Casson Leighton [Wed, 1 Aug 2018 05:46:47 +0000 (06:46 +0100)]
AddingPeripherals.mdwn
Luke Kenneth Casson Leighton [Wed, 1 Aug 2018 05:46:33 +0000 (06:46 +0100)]
add sdram3 function
Luke Kenneth Casson Leighton [Tue, 31 Jul 2018 07:59:44 +0000 (08:59 +0100)]
when muxwidth == 1 output pin directly
Luke Kenneth Casson Leighton [Tue, 31 Jul 2018 07:51:15 +0000 (08:51 +0100)]
use dedicated cell output for muxwidth = 1
Luke Kenneth Casson Leighton [Tue, 31 Jul 2018 07:42:04 +0000 (08:42 +0100)]
update i_class pinspec
Luke Kenneth Casson Leighton [Tue, 31 Jul 2018 07:20:30 +0000 (08:20 +0100)]
fix cell bit widths if muxwidth = 1
Luke Kenneth Casson Leighton [Tue, 31 Jul 2018 07:05:27 +0000 (08:05 +0100)]
output cell mux peripheral side
Luke Kenneth Casson Leighton [Tue, 31 Jul 2018 07:02:20 +0000 (08:02 +0100)]
start code-gen for mux cells
Luke Kenneth Casson Leighton [Tue, 31 Jul 2018 06:57:41 +0000 (07:57 +0100)]
read cell width and bank from pinmap.txt
Luke Kenneth Casson Leighton [Tue, 31 Jul 2018 06:52:12 +0000 (07:52 +0100)]
put pinbank and mux widths into pinmap.txt
Luke Kenneth Casson Leighton [Tue, 31 Jul 2018 06:39:08 +0000 (07:39 +0100)]
remove muxwidths
Luke Kenneth Casson Leighton [Tue, 31 Jul 2018 06:37:47 +0000 (07:37 +0100)]
write mux width and read back in
Luke Kenneth Casson Leighton [Tue, 31 Jul 2018 06:28:23 +0000 (07:28 +0100)]
remove write_ptp, add bitwidths.txt file
Luke Kenneth Casson Leighton [Tue, 31 Jul 2018 06:08:24 +0000 (07:08 +0100)]
make mux cells possible to be 1 wide
Luke Kenneth Casson Leighton [Tue, 31 Jul 2018 06:03:14 +0000 (07:03 +0100)]
pass in muxwidth as argument
Luke Kenneth Casson Leighton [Tue, 31 Jul 2018 06:00:21 +0000 (07:00 +0100)]
specify mux width by argument
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 10:41:43 +0000 (11:41 +0100)]
comment out fb master ifc
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 10:23:48 +0000 (11:23 +0100)]
add master connection
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 10:00:55 +0000 (11:00 +0100)]
sort out jtag clock/reset interchange
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 09:39:39 +0000 (10:39 +0100)]
hmm something suspicious with jtag tck/reset
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 09:22:19 +0000 (10:22 +0100)]
whoops iocell_side interface in wrong template
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 09:19:22 +0000 (10:19 +0100)]
comment out jtag clock sync for now
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 09:18:46 +0000 (10:18 +0100)]
TMS JTAG is an input
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 09:10:47 +0000 (10:10 +0100)]
add iocell peripheral and jtag pins
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 09:06:20 +0000 (10:06 +0100)]
add iocell peripheral and jtag pins
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 08:31:46 +0000 (09:31 +0100)]
invert clock/spc link for input pintypes
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 07:53:27 +0000 (08:53 +0100)]
correct flexbus connections
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 07:47:11 +0000 (08:47 +0100)]
sort out flexbus vector pincon
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 07:31:50 +0000 (08:31 +0100)]
sort out flexbus vector pincon
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 07:20:28 +0000 (08:20 +0100)]
add pin renaming for vector connections
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 06:31:45 +0000 (07:31 +0100)]
flexbus clock-synced
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 06:19:26 +0000 (07:19 +0100)]
vectorise pincon sync
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 05:53:09 +0000 (06:53 +0100)]
clock resolution
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 05:40:10 +0000 (06:40 +0100)]
add lcd clock sync
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 05:04:16 +0000 (06:04 +0100)]
format rgbttl connections
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 04:52:33 +0000 (05:52 +0100)]
missed mk_pincon rename for sdcard
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 04:51:28 +0000 (05:51 +0100)]
missed mk_pincon rename for sdcard
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 04:50:32 +0000 (05:50 +0100)]
missed mk_pincon rename for eint
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 04:48:58 +0000 (05:48 +0100)]
whoops _mk_pincon bypass
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 04:48:35 +0000 (05:48 +0100)]
whoops _mk_pincon bypass
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 04:47:28 +0000 (05:47 +0100)]
uart clock and reset
projects / pinmux.git / log