xmlpool: remove shebang from gen_xmlpool.py

Analogous to earlier commit(s).

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

genxml: remove shebang from gen_pack_header.py

Analogous to earlier commit(s).

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

nir: remove shebang from python scripts

Analogous to earlier commit(s).

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

st/xa: suffix xa-indent{,.sh} and add a shebang line

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

gallium/tools: use correct shebang for python scripts

These are python2 scripts and the generic "python" may point to
python3.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

gallium/tools: do not hardcode bash location

It is not guaranteed to be in /bin

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andreas Boll <andreas.boll.dev@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

gallium/tests: remove execute bit from TGSI shader - vert-uadd.sh

Just like the the dozens of other shaders, the file is parsed by
separate tool and not executed.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

mapi/gen: remove shebang from python scripts

All of those should be executed $PYTHON2/python2 [or equivalent] hence
why they are missing the execute bit.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

mapi: do not mandate bash for es*api/ABI-check

Seemingly there is nothing bash specific in these. The Debian
checkbashisms does not spot neither run in zsh.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

bin/perf-annotate-jit: add .py suffix

To provide direct feedback about the file in question.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

i965: remove shebang from brw_nir_trig_workarounds.py

Analogous to earlier commit(s).

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

i965: remove execute bit from brw_nir_trig_workarounds.py

Analogous to earlier commit(s).

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

mesa: remove shebang from python scripts

Analogous to earlier commit(s).

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

mesa: remove execute bit from main/format_parser.py

Analogous to earlier commit(s).

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

amd: remove shebang from python scripts

Analogous to earlier commit(s).

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

amd: remove execute bit from python scripts

Analogous to earlier commit(s).

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

gallium: remove shebang from python scripts

Analogous to earlier commit(s).

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

gallium: remove execute bit from the python script(s)

Analogous to earlier commit(s).

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

svga: remove shebang from svgadump/svga_dump.py

Analogous to earlier commit(s).

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

svga: remove execute bit from svga_dump.py

The file is used to generate svgadump/svga_dump.c... in theory at least.
Atm. the file is checked in-tree but that is about to change later
commits.

As we get to that we'll use $PYTHON2 or equivalent as used throughout
the tree.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

freedreno: remove shebang from ir3_nir_trig.py

Analogous to earlier commit(s).

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

freedreno: remove execute bit from ir3_nir_trig.py

The file is meant to be called with $(PYTHON2) and not executed
directly.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

glsl: remove shebang from python scripts

All of the scripts are [must be] executed via $PYTHON2 [or equivalent]
hence why they are missing the execute bit.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

glsl/tests: remove execute bit from compare_ir python script

Nearly all the python scripts used in-tree are invoked via $PYTHON2 or
equivalent. As such having the execute bit not needed and generally
ill-advised.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

glsl/tests: suffix .sh/.py files as applicable

This makes it easier/clearer as to:
 - if the file should have the execute bit set (.py should not)
 - do we need the shebang in the first place and if so what it should be

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

mesa: drop the execute bit from gl.xml

This is a spec file which is parsed by scripts.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andreas Boll <andreas.boll.dev@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

mapi/glapi: remove unused next_available_offset.sh

Afaict there was no [documented] users since it was introduced.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

gbm: Export a per plane getter for offset

Unlike stride, there was no previous offset getter, so it can be right
on the first try.

v2: Return EINVAL when plane is greater than total planes to make it
match the similar APIs.
Avoid leak after fromPlanar (Daniel)
Make sure when getting offsets we consider dumb images (Daniel)

v3: Use Jason's recommendation for handling the non-planar case.

v4: Return int64_t so we can get real errors

v5: Add an assertion for dumb BOs (Jason)

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Daniel Stone <daniels@collabora.com>

gbm: Export a per plane getter for stride

v2: Preserve legacy behavior when plane is 0 (Jason Ekstrand)
EINVAL when input plane is greater than total planes (Jason Ekstrand)
Don't leak the image after fromPlanar (Daniel)
Move bo->image check below plane count preventing bad index succeeding (Daniel)

v3: Fix DRIimage leak (using Jason's recommended change)
Make plane 0 return planar stride. This might break legacy behavior (Jason)

v4: Move bogus hunk for get_handle_for_plane to the right patch (Jason)
Fix error handling path to be cleaner (Jason)

v5: Add assert for dumb BOs to make sure plane == 0 (Jason)

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com> (v1)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Daniel Stone <daniels@collabora.com>

gbm: Create a gbm_device getter for stride

This will be used so we can query information per plane.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Daniel Stone <daniels@collabora.com>

gbm: Export a getter for per plane handles

v2: Make the error return be -1 instead of 0 because I think 0 is
actually valid.

v3: Set errno to EINVAL when the specified plane is above the total
planes. (Jason Ekstrand)
Return the bo's handle if there is no image ie. for dumb images like cursor (Daniel)

v4:
- Add assertions about plane == 0 (Jason)
- Add a comment about new restriction on planar dumb bo which is not an
earlier patch in the series.
- Correctly refactor from v2 in this patch; it ended up rebased into the
wrong patch.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Daniel Stone <daniels@collabora.com>

gbm: Export a plane getter function

This will be used by clients that need to know the number of planes
allocated for them on behalf of the GL or other API. The best current
example of this is when an extra "plane" is allocated to store
compression data for the primary plane.

v2: Return 1 for cases where there is no image, ie. dumb bo (Daniel)

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Daniel Stone <daniels@collabora.com>

gbm: Explicitly disallow a planar dumb BO

As more GBM functionality support planes is being evaluated, it becomes
clear that a dumb bo can never actually be planar. It's questionable
whether it was ever feasible to do this, and later functionality will
implicitly assume a dumb BO is non-planar.

v2: Include stdbool.h

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Acked-by: Daniel Stone <daniels@collabora.com>

i965: Rename brw_format_for_mesa_format() to brw_isl_format_for_mesa_format()

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

i965: Add more Haswell OA metrics sets

This extends the brw_oa_hsw.xml to expose these additional queries:

- Compute Metrics Basic Gen7.5
- Compute Metrics Extended Gen7.5
- Memory Reads Distribution Gen7.5
- Memory Writes Distribution Gen7.5
- Metric set Sampler Balance

Signed-off-by: Robert Bragg <robert@sixbynine.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Expose OA counters via INTEL_performance_query

This adds support for exposing basic Observation Architecture
performance counters on Haswell.

This support is based on the i915 perf kernel interface which is used
to configure the OA unit, allowing Mesa to emit MI_REPORT_PERF_COUNT
commands around queries to collect counter snapshots.

To take into account the small chance that some of the 32bit counters
could wrap around for long queries (~50 milliseconds for a GT3 Haswell @
1.1GHz) the implementation also collects periodic metrics.

Signed-off-by: Robert Bragg <robert@sixbynine.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

exec_list: Add a foreach_list_typed_from macro

This allows iterating list nodes from a given start point instead of
necessarily the list head.

Signed-off-by: Robert Bragg <robert@sixbynine.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Add script to gen code for OA counter queries

Avoiding lots of error prone boilerplate and easing our ability to add +
maintain support for multiple OA performance counter queries for each
generation:

This adds a python script to generate code for building up
performance_queries from the metric sets and counters described in
brw_oa_hsw.xml as well as functions to normalize each counter based on
the RPN expressions given.

Although the XML file currently only includes a single metric set, the
code generated assumes there could be many sets.

The metrics as described in XML get translated into C structures
which are registered in a brw->perfquery.oa_metrics_table hash table
keyed by the GUID of the metric set in XML.

v2: numerous python style improvements (Dylan)
v3: Makefile.am fixups (Emil)
v4: Pattern rule for codegen + orthogonal .c and .h rules (Robert)

Signed-off-by: Robert Bragg <robert@sixbynine.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965: extend query/counter structs for OA queries

In preparation for generating code from brw_oa_hsw.xml for describing OA
performance counter queries this adds some OA specific members to
brw_perf_query that our generated code will initialize:

- The oa_metric_set_id is the ID we will pass to
  DRM_IOCTL_I915_PERF_OPEN, and is an ID got via sysfs under:
  /sys/class/drm/<card>/metrics/<guid/id

- The oa_format is the OA report layout we will request from the kernel

- The accumulator offsets determine where the different groups of A, B
  and C counters are located within an intermediate 64bit 'accumulator'
  buffer.

Additionally brw_perf_query_counter now has 64bit or float _read()
callback members for OA counters.

Signed-off-by: Robert Bragg <robert@sixbynine.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965: brw_context.h additions for OA unit query codegen

In preparation for generating code from the XML performance counter meta
data, this makes some additions to brw_context.h for this code to be
able to reference.

It adds a brw->perfquery.oa_metrics_table hash table for indexing built
up query descriptions by the GUID that is expected to be advertised by
the kernel (via sysfs) to be able to use that query.

It adds an 'OA_COUNTERS' brw_query_kind to be assigned to queries built
up by generated code.

It adds a brw->perfquery.sys_vars structure to have a consistent place
to represent the different system variables like $EuCoresTotalCount and
$EuSlicesTotalCount that are referenced by OA counter normalization
equations.

  Although extending + referencing gen_device_info for these variables
  was considered, these are some of the (mostly minor) reasons for
  going with a dedicated structure:

  - Currently we only need this info for the performance_query backend
    and it might be a bit tedious to go back and initialize the state
    for pre-Haswell devinfo structures.
  - Considering the $SubsliceMask then the requirement for how multiple
    per-slice masks are packed only comes from how the variables are
    references by availability tests in XML, and might not be a good
    general representation for tracking subslice masks if another use
    case arises.
  - If we used gen_device_info then we'd likely want to avoid making
    assumptions about the C types during codegen and adding explicit
    casts, while that's not necessary with a dedicated struct with all
    members being uint64_t.
  - This structure and the code for initializing it is currently shared
    (just through copy & paste) with a few other projects dealing with
    OA counters, and that's been convenient so far.

Signed-off-by: Robert Bragg <robert@sixbynine.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965: XML description of Haswell OA metric set

In preparation for exposing Gen Observation Architecture performance
counters via INTEL_performance_query this adds an XML description for an
initial 'Render Metrics Basic Gen7.5' query and corresponding counters.

The intention is to auto generate code for building a query from these
counters as well as the code for normalizing the individual counters.

Note that the upstream for this XML data is currently GPU Top:

  https://github.com/rib/gputop

The files are maintained under gputop-data/ and they are themselves
derived from files in an internal 'MDAPI XML' schema. There are scripts
under gputop-scripts/ and make rules in gputop-data/Makefile.xml for
maintaining these files.

Signed-off-by: Robert Bragg <robert@sixbynine.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

nv50/ir: check for origin insn in findOriginForTestWithZero

Function arguments do not have an "origin" instruction, causing a
NULL-pointer dereference without this check.

Signed-off-by: Pierre Moreau <pierre.morrow@free.fr>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

mesa/main: make use of lookup_samplerobj_locked()

There is no need to check sampler == 0 twice. This removes now
unused _mesa_lookup_samplerobj_locked().

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa/main: inline {begin,end}_samplerobj_lookups()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

glsl/blob: clear padding bytes

Since blob is intended for serializing data, it's not a good idea to
leave padding holes with uninitialized data, which may leak heap
contents and hurt compression if the blob is later compressed, like
done by shader cache. Clear it.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

util/disk_cache: fix size subtraction on 32bit

Negating size_t on 32bit produces a 32bit result. This was effectively
adding values close to UINT_MAX to the cache size (the files are usually
small) instead of intended subtraction.
Fixes 'make check' disk_cache failures on 32bit.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

util/disk_cache: fix compressed size calculation

It incorrectly doubles the size on each iteration.

Fixes: 85a9b1b5 "util/disk_cache: compress individual cache entries"
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

glsl: builtin: always return clones of the builtins

Builtins are created once and allocated using their own private ralloc
context. When reparenting IR that includes builtins, we might be steal
bits of builtins. This is problematic because these builtins might now
be freed when the shader that includes then last is disposed. This
might also lead to inconsistent ralloc trees/lists if shaders are
created on multiple threads.

Rather than including builtins directly into a shader's IR, we should
include clones of them in the ralloc context of the shader that
requires them. This fixes double free issues we've been seeing when
running shader-db on a big multicore (72 threads) server.

v2: Also rename _mesa_glsl_find_builtin_function_by_name() to better
    reflect how this function is used. (Ken)

v3: Rename ctx to mem_ctx (Ken)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Delete render ring prelude.

This was a hook I came up when trying to do the initial performance
counter work years ago.  Nothing's used it for a long time, and the
upcoming performance counter support doesn't want it either.

So, goodbye render ring prelude.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

swr: s/uint/enum pipe_render_cond_flag/

Fix build error.

swr_context.cpp: In function ‘void swr_blit(pipe_context*, const pipe_blit_info*)’:
swr_context.cpp:336:44: error: invalid conversion from ‘uint {aka unsigned int}’ to ‘pipe_render_cond_flag’ [-fpermissive]
                                       ctx->render_cond_mode);
                                       ~~~~~^~~~~~~~~~~~~~~~

Fixes: b0d39384307d ("gallium: s/uint/enum pipe_render_cond_flag/ for set_render_condition()")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100133
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

radv: Don't flush the CB before doing a fast clear eliminate.

The only way we write CMASK/DCC compressed textures through shaders
is fast clears and CMASK/DCC inits, which have their own flushes.
Hence the CB cache is always up to date.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Don't emit cache flushes on subpass switch.

I think we should only flush right before an action (draw/dispatch etc.),
as otherwise it is too easy to issue redundant flushes.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Only flush for the needed stages, and before the flushes.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Don't invalidate CB/DB for images that aren't modified outside CB/DB.

Without stores, the only writes are fast clears, transfers and metadata
initialization, each of which have the appropiate invalidations already.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Flush more caches after writes.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Don't flush for fixed-function reading.

The data should always be in memory after a src flush.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Invalidate the correct caches for CB/DB dst barriers.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Determine cache flushes per object.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

mesa/main: remove unused _mesa_new_texture_image()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>

radv/ac: fixup texture coord to have right number of channels.

Jason has patches to add validation to this area, this should fix
radv shaders.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

st/nine: pass NULL to ureg_get_tokens()

The number of tokens in never used and the pointer is NULL checked
so just pass NULL.

Reviewed-by: Axel Davy <axel.davy@ens.fr>

docs: ARB_shader_atomic_counter_ops is enabled on i965/gen7+.

This extension was enabled in commit 40dd45d0c6aa ("i965: Enable
ARB_shader_atomic_counter_ops") but the commit failed to update the
release notes or features.txt. The release notes ship has sailed, since
the commit was in 13.0.

vc4: Fix math with a condition flag set.

Math results land in r4, regardless of the condition.  To implement them,
we just need to ensure that the results are moved out of r4 (as often
happens anyway, the values is live across another math instruction), so
that we can attach the condition to the MOV.

Fixes dEQP-GLES2.functional.shaders.random.all_features.fragment.93 and a
couple others, that were assertion failing that their conditions hadn't
been handled during the QIR->QPU stage.

vc4: Fix register pressure cost estimates when a src appears twice.

This ended up confusing the scheduler for things like fabs (implemented as
fmaxabs x, x) or squaring a number, and it would try to avoid scheduling
them because it appeared more expensive than other instructions.

Fixes failure to register allocate in
dEQP-GLES2.functional.uniform_api.random.3 with almost no shader-db
effects (+.35% max temps)

vc4: Report to shader-db how many threads a fragment shader has.

Doing instruction count analysis when we emit the thread switches that
will save us from tons of stalls is kind of missing the point.

Revert "vc4: Lazily emit our FS/VS input loads."

This reverts commit 292c24ddac5acc35676424f05291c101fcd47b3e.  It broke a
lot of GLES2 deqp, and I see at least one problem that will require some
serious rework to fix.

radeonsi: fix elimination of literal VS outputs

broken when switched to the new intrinsics.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

loader: Move non-error message to debug level

Currently when running mesa on imx6 the following loader warnings
are seen:

# kmscube -D /dev/dri/card1
MESA-LOADER: device is not located on the PCI bus
MESA-LOADER: device is not located on the PCI bus
MESA-LOADER: device is not located on the PCI bus
Using display 0x1920948 with EGL version 1.4

As this is not an error message, change it to debug level in
order to have a cleaner log output.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

android: r600: fix libmesa_amd_common dependency

Adding libmesa_amd_common dependency and exporting its headers,
avoids the following building error:

external/mesa/src/gallium/drivers/r600/evergreen_compute.c:29:10: fatal error: 'ac_binary.h' file not found
         ^
1 error generated.

Fixes: 3bbbb63 "automake: r600: radeonsi: correctly manage libamd_common.la linking"
Fixes: 503fb13 "radeon/ac: switch to ac_shader_binary_config_start()"
v2 [Emil Velikov: drop unneeded LOCAL_EXPORT_C_INCLUDE_DIRS]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

gallium/targets: rework the empty targets removal

Earlier commit added extra tracking and we've attempted to remove the
vdpau/other folder if empty. V2 of said commit dropped the pipe
to /dev/null and the explicit "true" override.

Sadly both of those are needed since there's no guarantee that the
folder will be empty before we [mesa] make install.

Since we're bringing those two back, there's no need to track if we've
installed anything, and simply do "rm -d foo/ &>/dev/null || true"

Tested-by: Andy Furniss <adf.lists@gmail.com>
Reported-by: Andy Furniss <adf.lists@gmail.com>
Fixes: 1cd4fde053 ("gallium/targets: don't leave an empty target directory(ies)")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

util/indices: minor clean-ups

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

radeonsi: s/uint/enum pipe_shader_type/

This can probably be done in more places in the driver.

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

gallium: s/uint/enum pipe_render_cond_flag/ for set_render_condition()

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

gallium: s/uint/enum pipe_shader_type/ for set_constant_buffer()

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

gallium: s/unsigned/enum pipe_shader_type/ for get_compiler_options()

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

virgl: s/unsigned/enum pipe_shader_type/

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

swr: s/unsigned/enum pipe_shader_type/

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

softpipe: s/unsigned/enum pipe_shader_type/

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

llvmpipe: s/unsigned/enum pipe_shader_type/

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

freedreno: s/unsigned/enum pipe_shader_type/

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

etnaviv: s/unsigned/enum pipe_shader_type/

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

draw: s/unsigned/enum pipe_shader_type/

and some s/uint/enum pipe_shader_type/

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

cso: s/unsigned/enum pipe_shader_type/

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

gallium: s/unsigned/enum pipe_shader_type/ for pipe_screen::get_shader_param()

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

anv: change BLOCK_POOL_MEMFD_SIZE to exactly 2GB

This is what comment above definition says and change fixes issue with
32bit build where BLOCK_POOL_MEMFD_SIZE is used as ftruncate parameter
and constant currently gets converted from 4294967296 to 0.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

Revert "configure.ac: Use PKG_CHECK_VAR for wayland-scanner."

This reverts commit 8a26e944399ae4d0fd662e5106f0b34f5ced462d.

Revert "configure.ac: Use PKG_CHECK_VAR for libclc."

This reverts commit 706074cc96cec8bad6c3569fc53b0b3a05ad176f.

i965: Remove use of deprecated drm_intel_aub routines

With mesa/drm commit cd2f91e18db087edf93fed828e568ee53b887860
Author: Kristian Høgsberg Kristensen <kristian.h.kristensen@intel.com>
Date:   Fri Jul 31 10:47:50 2015 -0700

    intel: Drop aub dumping functionality

the drm_intel_aub routines are mere stubs and do nothing. Likewise
remove our invocations.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

spirv: Silence unused variable warnings in release mode

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

anv: Make the framebuffer-renderpass format assert non-fatal

This should let Dota 2 run on debug builds though it will spew errors
like mad.  Hopefully, Valve will get this fixed sooner rather than
later.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

anv: Drop the anv_validate block helper

Over the course of driver development, we've come up with a number of
different schemes for adding giant blocks of asserts inside the driver.
This one is only being used once in anv_pipeline.c and the way it's
being used actually generates compiler warnings in release builds.  This
commit drops the anv_validate macro and just puts the contents of the
one validation function in side of a "#ifdef DEBUG" guard.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

anv: Get rid of the stub() macros

Except for a few unimplemented things on gen7, we don't really have
stubs anymore so we should drop this.  This commit replaces the few gen7
stub() calls with explicitly labeled finishme's and makes the sparse
binding stuff silently no-op or return a FEATURE_NOT_PRESENT error.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

anv: Remove a pointless finishme

We've been supporting multiple shaders per module for some time now.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

anv: Convert the HiZ finishme's to perf_warn

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

anv: Add a performance warning helper

This acts identically to anv_finishme except that it only dumps out
these nice log messages if you run with INTEL_DEBUG=perf.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

st/mesa: don't propagate uniforms when restoring from cache

We will have already loaded the uniforms when the parameter list
was restored from cache.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radv: remove duplicate initialization of alphaToOne feature

Fixes a GCC warning when compiling with -Wextra:
radv_device.c:463:47: warning: initialized field overwritten [-Woverride-init]

Signed-off-by: Damien Grassart <damien@grassart.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: disable mip point pre clamping.

No idea what this does, but disabling it fixes a bunch
of failing CTS tests in the lod area, so let's go with that.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv/ac: fix multiple descriptor sets with dynamic buffers

The dynamic_offset_offset in the descriptor set binding layout is
relative to the dynamic_offset_start for the set in the pipeline
layout.

Cc: 17.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Fredrik Höglund <fredrik@kde.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: fix the size of the dynamic_buffers array

A buffer descriptor is 16 bytes, not 16 dwords.

Signed-off-by: Fredrik Höglund <fredrik@kde.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>