Francisco Jerez [Tue, 3 Mar 2020 21:20:47 +0000 (13:20 -0800)]
intel/fs: Fix workaround for VxH indirect addressing bug under control flow.
The current workaround for this hardware bug involved marking the ADD
instruction used to initialize the address register as NoMask on
Gen12, which was based on the assumption that the problem was caused
by a hardware bug affecting the application of the execution mask to
the address register write.
However that doesn't seem to be the case: The address register write
was working correctly, the real problem leading to hangs on TGL is
that the indirect addressing logic is unable to deal with garbage
values in the address register (e.g. misaligned offsets), even for
channels which are currently inactive due to non-uniform control flow.
The current workaround isn't able to avoid that situation in general,
since the result of the NoMask ADD instruction for a dead channel is
calculated based on the corresponding (dead) component of the
indirect_byte_offset source, which would still be undefined in the
likely case that the source was initialized under control flow itself.
This would lead to hangs whenever MOV_INDIRECT was used under
non-uniform control flow in some scenarios like a tessellation shader
from GFXBench5/gl_4 (AKA Car Chase) on TGL. In addition I've managed
to reproduce the same issue on earlier platforms by initializing the
whole address register with garbage before the ADD instruction, so
this seems to be a long-standing issue we have avoided mostly by luck.
This patch fixes the problem and applies the workaround to all
platforms, since even when the hardware is able to deal with garbage
address values without hanging there might be a significant
performance cost from reading random GRF registers due to the useless
extra EU cycles spent fetching registers for dead channels and due to
the potential for unintended serialization with respect to other
random instructions that could be executed in parallel, which may have
had a cost of the order of hundreds of cycles in the worst case
scenario.
Fixes: f93dfb509c "intel/fs: Write the address register with NoMask for MOV_INDIRECT"
Tested-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Ian Romanick [Tue, 25 Feb 2020 19:37:01 +0000 (11:37 -0800)]
intel/fs: Allow NOT instructions in conditional discard optimization
I don't know why I explicitly disallowed NOT in the first place. :(
All Intel platforms had similar results. (Ice Lake shown)
total instructions in shared programs:
14549846 ->
14549770 (<.01%)
instructions in affected programs: 12934 -> 12858 (-0.59%)
helped: 76
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.13% max: 5.56% x̄: 1.04% x̃: 0.90%
95% mean confidence interval for instructions value: -1.00 -1.00
95% mean confidence interval for instructions %-change: -1.25% -0.84%
Instructions are helped.
total cycles in shared programs:
203793967 ->
203792696 (<.01%)
cycles in affected programs: 77920 -> 76649 (-1.63%)
helped: 67
HURT: 1
helped stats (abs) min: 2 max: 36 x̄: 19.00 x̃: 16
helped stats (rel) min: 0.04% max: 4.68% x̄: 2.35% x̃: 2.28%
HURT stats (abs) min: 2 max: 2 x̄: 2.00 x̃: 2
HURT stats (rel) min: 0.03% max: 0.03% x̄: 0.03% x̃: 0.03%
95% mean confidence interval for cycles value: -20.75 -16.63
95% mean confidence interval for cycles %-change: -2.57% -2.05%
Cycles are helped.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3965>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3965>
Ian Romanick [Mon, 24 Feb 2020 19:22:02 +0000 (11:22 -0800)]
intel/fs: Do cmod prop again after scheduling
Pre-RA scheduling can create more opportunities for CMOD propagation.
This takes advantage of that.
It may be worth doing this again in post-RA scheduling, but there are
additional problems there.
I'm a little torn about the use of the OPT() macro. On the one hand, it
would be confusing to see dumps from INTEL_DEBUG=optimizer that don't
match the final output. On the other hand, since register allocation
can fail, the same pass can be run multiple times. Each time one or
both passes might or might not make progress. This would also lead to
incongruous, confusing output.
Ice Lake
total instructions in shared programs:
14549808 ->
14548529 (<.01%)
instructions in affected programs: 231985 -> 230706 (-0.55%)
helped: 632
HURT: 0
helped stats (abs) min: 1 max: 32 x̄: 2.02 x̃: 1
helped stats (rel) min: 0.05% max: 2.56% x̄: 0.57% x̃: 0.41%
95% mean confidence interval for instructions value: -2.25 -1.79
95% mean confidence interval for instructions %-change: -0.61% -0.54%
Instructions are helped.
total cycles in shared programs:
203770850 ->
203776599 (<.01%)
cycles in affected programs:
2495653 ->
2501402 (0.23%)
helped: 282
HURT: 197
helped stats (abs) min: 1 max: 242 x̄: 20.37 x̃: 16
helped stats (rel) min: <.01% max: 11.65% x̄: 0.91% x̃: 0.64%
HURT stats (abs) min: 2 max: 609 x̄: 58.35 x̃: 20
HURT stats (rel) min: <.01% max: 10.97% x̄: 1.35% x̃: 0.66%
95% mean confidence interval for cycles value: 5.27 18.73
95% mean confidence interval for cycles %-change: -0.16% 0.21%
Inconclusive result (%-change mean confidence interval includes 0).
LOST: 0
GAINED: 2
Skylake
total instructions in shared programs:
13447708 ->
13446594 (<.01%)
instructions in affected programs: 216813 -> 215699 (-0.51%)
helped: 623
HURT: 0
helped stats (abs) min: 1 max: 32 x̄: 1.79 x̃: 1
helped stats (rel) min: 0.06% max: 2.86% x̄: 0.59% x̃: 0.42%
95% mean confidence interval for instructions value: -1.99 -1.59
95% mean confidence interval for instructions %-change: -0.63% -0.55%
Instructions are helped.
total cycles in shared programs:
193759224 ->
193762726 (<.01%)
cycles in affected programs:
2540035 ->
2543537 (0.14%)
helped: 249
HURT: 190
helped stats (abs) min: 2 max: 196 x̄: 16.67 x̃: 14
helped stats (rel) min: <.01% max: 4.71% x̄: 0.66% x̃: 0.62%
HURT stats (abs) min: 2 max: 614 x̄: 40.27 x̃: 14
HURT stats (rel) min: 0.02% max: 5.78% x̄: 0.86% x̃: 0.37%
95% mean confidence interval for cycles value: 2.57 13.39
95% mean confidence interval for cycles %-change: -0.11% 0.11%
Inconclusive result (%-change mean confidence interval includes 0).
LOST: 0
GAINED: 1
Broadwell
total instructions in shared programs:
13418631 ->
13417393 (<.01%)
instructions in affected programs: 243192 -> 241954 (-0.51%)
helped: 694
HURT: 0
helped stats (abs) min: 1 max: 31 x̄: 1.78 x̃: 1
helped stats (rel) min: 0.06% max: 2.86% x̄: 0.59% x̃: 0.44%
95% mean confidence interval for instructions value: -1.95 -1.62
95% mean confidence interval for instructions %-change: -0.62% -0.55%
Instructions are helped.
total cycles in shared programs:
200822940 ->
200829128 (<.01%)
cycles in affected programs:
2128651 ->
2134839 (0.29%)
helped: 251
HURT: 226
helped stats (abs) min: 1 max: 200 x̄: 14.32 x̃: 12
helped stats (rel) min: <.01% max: 3.56% x̄: 0.60% x̃: 0.50%
HURT stats (abs) min: 2 max: 611 x̄: 43.28 x̃: 18
HURT stats (rel) min: 0.02% max: 7.03% x̄: 0.93% x̃: 0.54%
95% mean confidence interval for cycles value: 7.44 18.50
95% mean confidence interval for cycles %-change: 0.02% 0.23%
Cycles are HURT.
Haswell and Ivy Bridge had similar results. (Haswell shown)
total instructions in shared programs:
11569710 ->
11568829 (<.01%)
instructions in affected programs: 147862 -> 146981 (-0.60%)
helped: 487
HURT: 0
helped stats (abs) min: 1 max: 34 x̄: 1.81 x̃: 1
helped stats (rel) min: 0.12% max: 4.75% x̄: 0.57% x̃: 0.45%
95% mean confidence interval for instructions value: -2.03 -1.59
95% mean confidence interval for instructions %-change: -0.61% -0.54%
Instructions are helped.
total cycles in shared programs:
187079425 ->
187079437 (<.01%)
cycles in affected programs:
1088494 ->
1088506 (<.01%)
helped: 234
HURT: 124
helped stats (abs) min: 2 max: 282 x̄: 22.66 x̃: 16
helped stats (rel) min: 0.03% max: 7.88% x̄: 0.93% x̃: 0.75%
HURT stats (abs) min: 1 max: 276 x̄: 42.86 x̃: 20
HURT stats (rel) min: 0.03% max: 6.70% x̄: 0.99% x̃: 0.53%
95% mean confidence interval for cycles value: -5.54 5.61
95% mean confidence interval for cycles %-change: -0.41% -0.11%
Inconclusive result (value mean confidence interval includes 0).
total spills in shared programs: 7746 -> 7740 (-0.08%)
spills in affected programs: 6 -> 0
helped: 1
HURT: 0
total fills in shared programs: 6264 -> 6258 (-0.10%)
fills in affected programs: 6 -> 0
helped: 1
HURT: 0
Sandy Bridge
total instructions in shared programs:
10688576 ->
10688177 (<.01%)
instructions in affected programs: 137875 -> 137476 (-0.29%)
helped: 358
HURT: 0
helped stats (abs) min: 1 max: 9 x̄: 1.11 x̃: 1
helped stats (rel) min: 0.15% max: 1.43% x̄: 0.35% x̃: 0.28%
95% mean confidence interval for instructions value: -1.18 -1.05
95% mean confidence interval for instructions %-change: -0.37% -0.32%
Instructions are helped.
total cycles in shared programs:
153397144 ->
153393046 (<.01%)
cycles in affected programs:
1220713 ->
1216615 (-0.34%)
helped: 255
HURT: 31
helped stats (abs) min: 1 max: 304 x̄: 16.71 x̃: 16
helped stats (rel) min: <.01% max: 6.70% x̄: 0.41% x̃: 0.31%
HURT stats (abs) min: 1 max: 41 x̄: 5.29 x̃: 3
HURT stats (rel) min: 0.02% max: 0.65% x̄: 0.16% x̃: 0.11%
95% mean confidence interval for cycles value: -17.44 -11.22
95% mean confidence interval for cycles %-change: -0.40% -0.29%
Cycles are helped.
Iron Lake
total instructions in shared programs:
8106894 ->
8105529 (-0.02%)
instructions in affected programs: 287197 -> 285832 (-0.48%)
helped: 1099
HURT: 0
helped stats (abs) min: 1 max: 10 x̄: 1.24 x̃: 1
helped stats (rel) min: 0.16% max: 4.55% x̄: 0.67% x̃: 0.61%
95% mean confidence interval for instructions value: -1.29 -1.19
95% mean confidence interval for instructions %-change: -0.70% -0.64%
Instructions are helped.
total cycles in shared programs:
188347022 ->
188344266 (<.01%)
cycles in affected programs:
3740632 ->
3737876 (-0.07%)
helped: 758
HURT: 10
helped stats (abs) min: 2 max: 38 x̄: 3.68 x̃: 2
helped stats (rel) min: <.01% max: 1.00% x̄: 0.12% x̃: 0.08%
HURT stats (abs) min: 2 max: 4 x̄: 3.20 x̃: 4
HURT stats (rel) min: 0.03% max: 0.07% x̄: 0.06% x̃: 0.07%
95% mean confidence interval for cycles value: -3.82 -3.35
95% mean confidence interval for cycles %-change: -0.13% -0.11%
Cycles are helped.
GM45
total instructions in shared programs:
4985449 ->
4984768 (-0.01%)
instructions in affected programs: 145154 -> 144473 (-0.47%)
helped: 547
HURT: 0
helped stats (abs) min: 1 max: 10 x̄: 1.24 x̃: 1
helped stats (rel) min: 0.16% max: 2.86% x̄: 0.66% x̃: 0.61%
95% mean confidence interval for instructions value: -1.31 -1.18
95% mean confidence interval for instructions %-change: -0.69% -0.62%
Instructions are helped.
total cycles in shared programs:
128835062 ->
128833144 (<.01%)
cycles in affected programs:
2720650 ->
2718732 (-0.07%)
helped: 517
HURT: 1
helped stats (abs) min: 2 max: 38 x̄: 3.71 x̃: 2
helped stats (rel) min: <.01% max: 0.89% x̄: 0.11% x̃: 0.07%
HURT stats (abs) min: 2 max: 2 x̄: 2.00 x̃: 2
HURT stats (rel) min: 0.04% max: 0.04% x̄: 0.04% x̃: 0.04%
95% mean confidence interval for cycles value: -4.02 -3.39
95% mean confidence interval for cycles %-change: -0.12% -0.10%
Cycles are helped.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3965>
Eric Engestrom [Mon, 9 Mar 2020 22:40:40 +0000 (23:40 +0100)]
docs: update calendar, add news item, and link releases notes for 19.3.5
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4121>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4121>
Eric Engestrom [Mon, 9 Mar 2020 18:49:32 +0000 (19:49 +0100)]
docs: add release notes for 19.3.5
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4121>
Vinson Lee [Mon, 2 Mar 2020 05:38:18 +0000 (21:38 -0800)]
st/nine: Fix incompatible-pointer-types-discards-qualifiers errors.
../src/gallium/state_trackers/nine/nine_ff.c:129:28: error: initializing 'struct nine_ff_vs_key *' with an expression of type 'const void *' discards qualifiers [-Werror,-Wincompatible-pointer-types-discards-qualifiers]
struct nine_ff_vs_key *vs = key;
^ ~~~
../src/gallium/state_trackers/nine/nine_ff.c:145:28: error: initializing 'struct nine_ff_ps_key *' with an expression of type 'const void *' discards qualifiers [-Werror,-Wincompatible-pointer-types-discards-qualifiers]
struct nine_ff_ps_key *ps = key;
^ ~~~
Fixes: fdd96578ef2d ("nine: Add state tracker nine for Direct3D9 (v3)")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Andre Heider <a.heider@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4015>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4015>
Marek Olšák [Thu, 27 Feb 2020 03:48:41 +0000 (22:48 -0500)]
radeonsi: determine uses_bindless_samplers correctly
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4079>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4079>
Marek Olšák [Wed, 4 Mar 2020 00:01:17 +0000 (19:01 -0500)]
ac: add a bug workaround for the 100% NGG culling case
Fixes: 8db00a51f85 - radeonsi/gfx10: implement NGG culling for 4x wave32 subgroups
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4079>
Marek Olšák [Tue, 3 Mar 2020 23:40:50 +0000 (18:40 -0500)]
radeonsi: add a bug workaround for NGG - LATE_ALLOC_GS
Cc: 19.3 20.0 <mesa-stable@lists.freedesktop.org>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4079>
Sonny Jiang [Wed, 8 Jan 2020 22:18:40 +0000 (17:18 -0500)]
radeonsi: enable EXT_texture_shadow_lod
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4079>
Chia-I Wu [Thu, 7 Feb 2019 23:14:19 +0000 (15:14 -0800)]
egl/android: require ANDROID_native_fence_sync for buffer age
Querying buffer age requires a buffer to be dequeued. But dequeuing
without ANDROID_native_fence_sync might imply eglClientWaitSync,
which results in a deadlock as the display lock is already held by
eglQuerySurface.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/221>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/221>
Edmondo Tommasina [Mon, 9 Mar 2020 15:25:03 +0000 (16:25 +0100)]
radv/sqtt: fix RADV_THREAD_TRACE_BUFFER_SIZE spelling
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4116>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4116>
Eric Engestrom [Mon, 9 Mar 2020 11:23:00 +0000 (12:23 +0100)]
docs/releasing: add missing </li> tags
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4094>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4094>
Eric Engestrom [Fri, 6 Mar 2020 22:07:16 +0000 (23:07 +0100)]
docs: trivial fix for html structure
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4094>
Neil Roberts [Fri, 7 Jun 2019 06:52:14 +0000 (08:52 +0200)]
glsl/opt_minmax: Add support for float16
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
Kristian H. Kristensen [Wed, 4 Mar 2020 19:58:58 +0000 (11:58 -0800)]
glsl/lower_instructions: Handle fp16 for FDIV_TO_MUL_RCP
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
Hyunjun Ko [Mon, 3 Jun 2019 08:44:14 +0000 (08:44 +0000)]
glsl/lower_instructions: Handle fp16 for MOD_TO_FLOOR
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
Neil Roberts [Sun, 26 May 2019 13:32:49 +0000 (15:32 +0200)]
glsl/lower_instructions: Use float16 constants when appropriate
When lowering instructions that involve floating-point constants, pick
the appropriate type for the constant so that it will also work with
float16 parameters.
v2: Use float16_t constructor instead of helper function.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
Neil Roberts [Thu, 16 May 2019 15:01:06 +0000 (17:01 +0200)]
glsl/validate: Allow float16 in the expression tree
v2. [Hyunjun Ko (zzoon@igalia.com)] squashed 3 commits
into one commit.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
Kristian H. Kristensen [Wed, 4 Mar 2020 21:57:33 +0000 (13:57 -0800)]
glsl: Add type queries for fp16+float and fp16+float+double
Following the is_integer_32_64() convention, add is_float_16_32() and
float_16_32_64() for these commonly tested combinations.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
Hyunjun Ko [Tue, 7 May 2019 06:20:28 +0000 (06:20 +0000)]
glsl: Handle fp16 unary operations when lowering matrix operations
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
Neil Roberts [Wed, 9 Oct 2019 11:07:40 +0000 (13:07 +0200)]
glsl: Add ir_unop_f2fmp
This is the same as ir_unop_f2f16 except that it comes with a promise
that it is safe to optimise it out if the result is immediately
converted back to float32 again. Normally this would be a lossy
operation but it is safe to do if the conversion was generated as part
of the precision lowering pass.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
Neil Roberts [Thu, 16 May 2019 11:25:28 +0000 (13:25 +0200)]
glsl: Add b2f16 and f162b conversion operations
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
Neil Roberts [Fri, 19 Apr 2019 13:36:00 +0000 (15:36 +0200)]
glsl: Add IR conversion ops for 16-bit float types
Adds ir_unop_f162f and ir_unop_f2f16.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
Kristian H. Kristensen [Tue, 25 Feb 2020 21:43:39 +0000 (13:43 -0800)]
glsl: Expand fp16 to float before constant expression evaluation
This way the generated constant folding code doesn't need to
understand fp16. All operations have to be expanded to full float for
evaulation on the CPU, so we might as well do it up front. As far as
GLSL is concerned, fp16 isn't a separate type from float, so
everything we're supposed to support for float we need to do for fp16.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
Kristian H. Kristensen [Tue, 4 Feb 2020 23:50:25 +0000 (15:50 -0800)]
glsl: Implement constant propagation for fp16
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
Kristian H. Kristensen [Thu, 16 Jan 2020 22:58:57 +0000 (14:58 -0800)]
glsl: Add fp16 case for ir_triop_lrp optimization
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
Neil Roberts [Sun, 21 Apr 2019 10:42:21 +0000 (12:42 +0200)]
glsl: Add support for float16 types in the IR tree
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
Kristian H. Kristensen [Thu, 16 Jan 2020 22:56:53 +0000 (14:56 -0800)]
glsl: Add ir_constant constructor for fp16
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
Kristian H. Kristensen [Tue, 25 Feb 2020 21:38:11 +0000 (13:38 -0800)]
freedreno/ir3: Don't fold conversions into sign
Not supported.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
Pierre-Eric Pelloux-Prayer [Wed, 30 Oct 2019 19:39:08 +0000 (20:39 +0100)]
gitlab-ci: rules:changes to test on tested drivers changes
For now tests only use these drivers:
* llvmpipe
* softpipe
* freedreno
* lima
* etnaviv
* panfrost
So using rules:changes gitlab feature to run the tests when the changes
made are potentially affecting these drivers.
A few notes:
* the following code:
.piglit-test:
extends:
- .test-gl
- .llvmpipe-rules
makes gitlab replace .test-gl "rules:changes" values by the one from
".llvmpipe-rules".
* rules:changes always matches for non-MR new branches so jobs will always be
created (and they'll be run if their dependencies are run). For pushes to
existing branches the files changed by the push are used to match the
rules:changes path.
* the same gitlab feature could be used for some build jobs
Acked-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2569>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2569>
Daniel Schürmann [Wed, 4 Mar 2020 16:49:06 +0000 (17:49 +0100)]
amd: join emit_kill() from radv and radeonsi in ac_nir_to_llvm
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4047>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4047>
Daniel Schürmann [Wed, 4 Mar 2020 16:35:26 +0000 (17:35 +0100)]
radv: use nir_lower_discard_to_demote to work around game bugs
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4047>
Daniel Schürmann [Wed, 4 Mar 2020 16:22:36 +0000 (17:22 +0100)]
radeonsi: lower discard to demote when FS_CORRECT_DERIVS_AFTER_KILL is enabled
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4047>
Daniel Schürmann [Wed, 4 Mar 2020 15:48:44 +0000 (16:48 +0100)]
amd/llvm: implement nir_intrinsic_demote(_if) and nir_intrinsic_is_helper_invocation
The current implementation uses a temporary helper variable
to ensure correct behavior until LLVM provides an intrinsic.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4047>
Daniel Schürmann [Wed, 4 Mar 2020 15:55:13 +0000 (16:55 +0100)]
nir: add pass to lower discard() to demote()
This pass is intended to work around game bugs, only!
It also lowers nir_intrinsic_load_helper_invocation to
nir_intrinsic_is_helper_invocation for consistency.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4047>
Daniel Schürmann [Wed, 4 Mar 2020 15:43:15 +0000 (16:43 +0100)]
nir: gather info whether a shader uses demote_to_helper
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4047>
Eli Schwartz [Sun, 8 Mar 2020 16:58:57 +0000 (12:58 -0400)]
docs: fix typo in v20 release notes
It makes no sense to wait for it to stabilize on a version released
months previously in the previous major release cycle.
This was probably intended to be recommending the first bugfix release
of the current major.minor release cycle.
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4106>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4106>
Eric Engestrom [Mon, 9 Mar 2020 11:41:59 +0000 (11:41 +0000)]
Revert "docs/relnotes/19.3: fix vulkan version reported"
This reverts commit
5ff443b8aa9650f907bd9b5524bab21febe42ec9
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4112>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4112>
Tapani Pälli [Mon, 9 Mar 2020 08:35:20 +0000 (10:35 +0200)]
nir: fix compilation warning on glsl_get_internal_ifc_packing
Removes following warning:
warning: 'const' type qualifier on return type has no effect
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4111>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4111>
Krzysztof Raszkowski [Fri, 6 Mar 2020 15:09:24 +0000 (16:09 +0100)]
gallium/swr: Fix vcvtph2ps llvm intrinsic compile error
Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4090>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4090>
Pierre-Eric Pelloux-Prayer [Thu, 5 Mar 2020 10:00:28 +0000 (11:00 +0100)]
meson: enable -fno-common by default
This flag is enabled by default starting with gcc 10.
All the compilation issues have been fixed, so use it by default
to make sure we're not introducing regressions.
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4058>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4058>
Pierre-Eric Pelloux-Prayer [Thu, 5 Mar 2020 08:37:58 +0000 (09:37 +0100)]
omx: fix build with gcc 10
bellagio/omx header files reference a global variable without the
extern keyworkd.
Now that gcc-10 enables the '-fno-common' by default the build fails.
Since these are external headers we can't easily fix them, so for
now build the omx module with the '-fcommon' flag to keep the
previous behavior.
See https://gitlab.freedesktop.org/mesa/mesa/issues/2385
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4058>
Matt Turner [Thu, 27 Feb 2020 18:48:37 +0000 (10:48 -0800)]
intel/compiler: Discount NOPs from instruction counts
Scheduler changes can cause changes in the number of instructions due to
this workaround, so just don't include NOPs in the instruction counts to
prevent shader-db noise.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4093>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4093>
Matt Turner [Thu, 5 Mar 2020 00:24:25 +0000 (16:24 -0800)]
intel/compiler: Pass shader_stats for each SIMD mode
Passing shader_stats to the fs_generator constructor means that the
SIMD8 shader stats from the visitor (such as the scheduler mode) will be
reported out for the SIMD16/SIMD32 versions as well.
As you can see, we are now passing 'shader_stats' and 'stats' to
generate_code(), which is obviously odd looking. Ian rebased and
committed an old patch of mine which added the shader_stats struct on
July 30 in commit
dabb5d4bee07 (i965/fs: Add a shader_stats struct.) and
shortly after on August 12 Jason added the brw_compile_stats struct in
commit
134607760ac2 (intel/compiler: Fill a compiler statistics struct).
I'd like to combine the two, but I'm not sure how. shader_stats is an
input to generate_code() while brw_compile_stats is an output and is
only used by the Vulkan driver. Leave it as is for now...
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4093>
Matt Turner [Fri, 6 Mar 2020 21:34:13 +0000 (13:34 -0800)]
intel/compiler: Pass backend_shader * to cfg_t()
As you can see, not having a pointer to the backend_shader from within
the class makes for some weird looking code.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4093>
Matt Turner [Fri, 28 Feb 2020 03:49:35 +0000 (19:49 -0800)]
intel/compiler: Mark visitor parameters to scheduler const
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4093>
Matt Turner [Fri, 23 Sep 2016 12:15:33 +0000 (15:15 +0300)]
intel/compiler: Mark some methods and parameters const
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4093>
Matt Turner [Thu, 28 Apr 2016 22:19:28 +0000 (15:19 -0700)]
intel/compiler: Make instructions_to_schedule a local variable
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4093>
Matt Turner [Sun, 1 Mar 2020 00:12:25 +0000 (16:12 -0800)]
intel/compiler: Remove unnecessary local variables
These are already provided in the fs_reg_alloc class.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4093>
Matt Turner [Fri, 28 Feb 2020 00:46:52 +0000 (16:46 -0800)]
intel/vec4: Make implied_mrf_writes() a vec4_instruction method
Same as commit
c20dc9b8363b (intel/fs: Make implied_mrf_writes() an
fs_inst method.)
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4093>
Christian Gmeiner [Tue, 4 Feb 2020 10:12:15 +0000 (11:12 +0100)]
etnaviv: implement emit_string_marker
Writes string to cmdstream in payload of a nop command.
Could be useful for internal driver debugging too.
Here is how it looks decoded:
0x18000000, /* NOP (3) OP=NOP */
0x65736572, /* rese */
0x18000000, /* NOP (3) OP=NOP */
0x00000074, /* t */
0x00000000, /* GL.API_MODE := OPENGL */
or
0x00000705, /* GL.STALL_TOKEN := FROM=RA,TO=PE,FLIP0=0,FLIP1=0 */
0x00000001, /* TS.FLUSH_CACHE := FLUSH=1 */
0x18000000, /* NOP (3) OP=NOP */
0x616e7465, /* etna */
0x18000000, /* NOP (3) OP=NOP */
0x6275735f, /* _sub */
0x18000000, /* NOP (3) OP=NOP */
0x5f74696d, /* mit_ */
0x18000000, /* NOP (3) OP=NOP */
0x735f7372, /* rs_s */
0x18000000, /* NOP (3) OP=NOP */
0x65746174, /* tate */
0x00004606, /* RS.CONFIG := SOURCE_FORMAT=A8R8G8B8
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3744>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3744>
Christian Gmeiner [Fri, 14 Feb 2020 10:43:11 +0000 (11:43 +0100)]
etnaviv: increase number of supported varyings to 16
No deqp regressions.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3827>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3827>
Christian Gmeiner [Fri, 14 Feb 2020 10:46:28 +0000 (11:46 +0100)]
etnaviv: update headers from rnndb
Update to etna_viv commit
fd2e2cfd.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3827>
Christian Gmeiner [Fri, 14 Feb 2020 12:24:07 +0000 (13:24 +0100)]
etnaviv: ask kernel for max number of supported varyings
The inital etnaviv kernel driver in 4.5 has support for this param.
See kernel commit
602eb48966d7b7f7e64dca8d9ea2842d83bfae73
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3827>
Michel Dänzer [Fri, 6 Mar 2020 11:35:17 +0000 (12:35 +0100)]
gitlab-ci: Always name artifacts archive after the job producing it
This will help determine which artifacts generate how much traffic.
v2:
* Add "mesa_" prefix to make it obvious which project the artifacts are
from.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4085>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4085>
Lionel Landwerlin [Wed, 22 Jan 2020 14:53:54 +0000 (16:53 +0200)]
anv: stop storing prog param data into shader blobs
We have no use for this data in Anv.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason EKstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3517>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3517>
Jason Ekstrand [Fri, 7 Feb 2020 13:13:12 +0000 (07:13 -0600)]
anv: Bounds-check pushed UBOs when robustBufferAccess = true
We also have to add nir_intrinsic_load_push_constant to the list of
intrinsics which use push constants in brw_nir_analyze_ubo_ranges
because we're moving the loop where we rewrite the intrinsics to after
we've analyzed UBO loads.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3777>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3777>
Jason Ekstrand [Fri, 7 Feb 2020 10:33:19 +0000 (04:33 -0600)]
anv: Add an align_down_u32 helper
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3777>
Jason Ekstrand [Tue, 11 Feb 2020 16:12:06 +0000 (10:12 -0600)]
anv: Align UBO sizes to 32B
This makes all of our bounds checking consistent with the block loads we
do for constant offset UBO accesses.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3777>
Jason Ekstrand [Tue, 11 Feb 2020 14:02:12 +0000 (08:02 -0600)]
anv: Delete some pointless break statements
They immediately follow returns.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3777>
Jason Ekstrand [Tue, 11 Feb 2020 13:40:05 +0000 (07:40 -0600)]
anv: Pass buffer addresses into emit_push_constant*
While we're here, we add an assert that bind_map::push_ranges is tightly
packed. If it isn't, it breaks assumptions in the emit_push_constant*
functions.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3777>
Jason Ekstrand [Tue, 11 Feb 2020 13:52:17 +0000 (07:52 -0600)]
anv: Mark max_push_range UNUSED and simplify the code
The compiler should be smart enough to figure out that it's unused on
Gen11 and earlier and delete the code which calculates. Us adding an
`if (GEN_GEN >= 12)` check is unnecessary and just dirties the code.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3777>
Jason Ekstrand [Thu, 13 Feb 2020 20:46:25 +0000 (14:46 -0600)]
anv: Parse VkPhysicalDeviceFeatures2 in CreateDevice
The client may enable robustBufferAccess2 via either
pCreateInfo->pEnabledFeatures or via a chained-in
VkPhysicalDeviceFeatures2 struct. We need to parse both.
Fixes: 022e5c7e5a5 "anv: Implement VK_KHR_get_physical_device_properties2"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3777>
Eric Engestrom [Fri, 6 Mar 2020 19:22:40 +0000 (20:22 +0100)]
docs/relnotes/20.0: fix vulkan version reported
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4092>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4092>
Eric Engestrom [Fri, 6 Mar 2020 19:22:28 +0000 (20:22 +0100)]
docs/relnotes/19.3: fix vulkan version reported
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4092>
Eric Engestrom [Fri, 6 Mar 2020 18:12:26 +0000 (19:12 +0100)]
gen_release_notes: fix vulkan version reported
Fixes: 4ef3f7e3d37ece7b4339 ("anv: Enable Vulkan 1.2 support")
Fixes: 7f5462e349a3f082e294 ("radv: enable Vulkan 1.2")
Fixes: 75755e0eba17f8500367 ("turnip: Pretend to support Vulkan 1.2")
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4092>
Alyssa Rosenzweig [Sat, 7 Mar 2020 00:31:49 +0000 (19:31 -0500)]
pan/bi: Fix Android.mk
Files listed in Makefile.sources did not exist, this affects the android
build for other drivers as well.
[Patch by Tapani manually cherrypicked into this branch]
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
Alyssa Rosenzweig [Sat, 7 Mar 2020 00:27:25 +0000 (19:27 -0500)]
pan/bi: Rename next-wait to simply 'wait'
next-wait is from a quirk of packing that the dependency indices are
"off by one"; we don't emulate this quirk in the IR since it's easy
enough to patch over in the disassembler. Let's not confuse anybody with
it.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
Alyssa Rosenzweig [Sat, 7 Mar 2020 00:25:00 +0000 (19:25 -0500)]
pan/bi: Add dummy scheduler
Do the absolute simplest possible thing -- create a clause for every
instruction, and just pick whichever slot we can, nopping the other,
copying whatever constant we have whether it's used or not.
To be clear - this is not to be used in a production compiler. But this
lets actual bundles and clauses show up in the BIR, which unblocks work
on final code generation and packing (which can happen more or less in
parallel to NIR->BIR, optimization, register allocation, and writing an
actual scheduling).
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
Alyssa Rosenzweig [Fri, 6 Mar 2020 21:29:35 +0000 (16:29 -0500)]
pan/bi: Implement load_const
In the laziest possible way... We can just emit worst case moves which
DCE will eat for breakfast anyway, and inline constants on instructions
where that is supported directly. This approach eliminates a lot of
nasty corner cases that Midgard's crazy cache scheme has hit, at the
expense of slightly more work for DCE (but it's only a single iteration
of an O(N) pass that has to run anyway..)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
Alyssa Rosenzweig [Fri, 6 Mar 2020 14:52:09 +0000 (09:52 -0500)]
pan/bi: Add preliminary LOAD_UNIFORM implementation
Lots of things are missing (indirect access, UBOs) but we have this
stubbed out for now.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
Alyssa Rosenzweig [Fri, 6 Mar 2020 14:44:19 +0000 (09:44 -0500)]
pan/bi: Implement store_vary for vertex shaders
As far as I/O goes, these four should hold us over for a while.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
Alyssa Rosenzweig [Fri, 6 Mar 2020 14:43:43 +0000 (09:43 -0500)]
pan/bi: Add helpers for creating temporaries
Also from Midgard, adapted to our addressing scheme.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
Alyssa Rosenzweig [Fri, 6 Mar 2020 14:33:52 +0000 (09:33 -0500)]
pan/bi: Implement load_input for vertex shaders
Corresponds to a single LD_ATTR instruction, easy enough.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
Alyssa Rosenzweig [Fri, 6 Mar 2020 14:26:44 +0000 (09:26 -0500)]
pan/bi: Implement store_output for fragment shaders
Corresponds to a BLEND instruction, possibly preceded by an ATEST
instruction.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
Alyssa Rosenzweig [Fri, 6 Mar 2020 14:26:20 +0000 (09:26 -0500)]
pan/bi: Add bi_schedule_barrier helper
Copypaste from Midgard.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
Alyssa Rosenzweig [Fri, 6 Mar 2020 14:25:58 +0000 (09:25 -0500)]
pan/bi: Add blend_location to IR for BI_BLEND
To specify which render target is being written.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
Alyssa Rosenzweig [Thu, 5 Mar 2020 22:50:18 +0000 (17:50 -0500)]
pan/bi: Implement nir_intrsinic_load_interpolated_input
Enough for basic varying reads.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
Alyssa Rosenzweig [Thu, 5 Mar 2020 22:49:45 +0000 (17:49 -0500)]
pan/bi: Fix destination printing
It should get the same treatment as sources to handle SSA/reg/etc.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
Alyssa Rosenzweig [Thu, 5 Mar 2020 22:10:46 +0000 (17:10 -0500)]
pan/bi: Handle jumps (breaks, continues)
Loops should behave reasonably now.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
Alyssa Rosenzweig [Thu, 5 Mar 2020 22:03:53 +0000 (17:03 -0500)]
pan/bi: Handle loops when ingesting CFG
Not very useful without also handling breaks and continues, of course.
We use the strategy from v3d (vir_to_nir) instead of Midgard's, since
the latter is mildly insane. I mean, it passes deqp but...
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
Alyssa Rosenzweig [Thu, 5 Mar 2020 21:45:16 +0000 (16:45 -0500)]
pan/bi: Add support for if-else blocks
Branch lowering code lifted from Midgard as usual.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
Alyssa Rosenzweig [Thu, 5 Mar 2020 21:52:29 +0000 (16:52 -0500)]
pan/bi: Call nir_lower_io_to_temporaries in cmdline
Normally mesa/st would do this for us, but we're using the standalone
compiler (in advance of having the hardware) and need this pass
particularly for fragment writeout.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
Alyssa Rosenzweig [Thu, 5 Mar 2020 21:44:49 +0000 (16:44 -0500)]
pan/bi: Add instruction emit/remove helpers
As we start descending into code generation these will be of interest.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
Alyssa Rosenzweig [Thu, 5 Mar 2020 21:33:09 +0000 (16:33 -0500)]
pan/bi: Print branch target
...if it's present, anyway.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
Alyssa Rosenzweig [Thu, 5 Mar 2020 21:30:58 +0000 (16:30 -0500)]
pan/bi: Don't print types for unconditional branches
There's nothing to type!
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
Alyssa Rosenzweig [Thu, 5 Mar 2020 15:28:13 +0000 (10:28 -0500)]
pan/bi: Improve block printing
Skip predecessor printing if there are none and match a missing brace,
also fixup the spacing.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
Alyssa Rosenzweig [Thu, 5 Mar 2020 15:25:19 +0000 (10:25 -0500)]
pan/bi: Walk through the NIR control flow graph
Copypaste from Midgard with some cleanups. That seems to be a trend
these days. Hopefully boilerplate will come to a close soon.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
Alyssa Rosenzweig [Thu, 5 Mar 2020 15:11:39 +0000 (10:11 -0500)]
pan/bi: Lower and optimize NIR
Pretty much a copypaste from Midgard except where architectural
decisions diverge around vectorization. On that note, we will need our
own ALU scalarization pass at some point (or rather we'll need to extend
nir_lower_alu_scalar) to allow partial lowering for 8/16-bit ops. I.e.
we'll approximately need to lower
vec4 16 ssa_2 = fadd ssa_0, ssa_1
to
vec2 16 ssa_2 = fadd ssa_0.xy, ssa_1.xy
vec2 16 ssa_3 = fadd ssa_0.zw, ssa_1.zw
vec4 16 ssa_4 = vec4 ssa_2.x, ssa_2.y, ssa_3.x, ssa_4
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4097>
Chad Versace [Wed, 12 Feb 2020 22:31:52 +0000 (14:31 -0800)]
anv: Flatten the logic add_aux_surface_if_supported (v3)
Reduces the function's max indentation level from 5 to 3 inside the big
'if' tree. And enables more comments to be attached to the condition
they describe.
v2:
- Add missing DEBUG_NO_RBC check.
v3:
- Return early on DISABLE_AUX_BIT.
- Restore original order of gen7 hiz check.
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4096>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4096>
Chad Versace [Wed, 12 Feb 2020 19:50:52 +0000 (11:50 -0800)]
anv: Refactor creation of aux surfaces (v2)
make_surface() contained a giant if-tree for creation of aux surfaces.
Move the if-tree into its own function, add_aux_surface_if_supported().
This will simplify future changes for VK_EXT_image_drm_format_modifier.
This patch merely moves the code verbatim, then extracts duplicate
assertions to the top.
v2: Rename func to add_aux_surface_if_supported [for jekstrand].
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4096>
Chad Versace [Fri, 1 Nov 2019 23:04:26 +0000 (16:04 -0700)]
anv: Add anv_image_plane_needs_shadow_surface() (v2)
The function returns true if hardware limitations require the image
plane to use a shadow surface. It replaces equivalent code in
make_surface().
Refactor only. No intended change in behavior.
Why extract this code out of vkCreateImage? If an image requires
a shadow surface, then that may impact its support for DRM format
modifiers, which must be evaluated during
vkGetPhysicalDeviceImageFormatProperties2.
v2:
- Use early return. [for jekstrand]
- Unexport function.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4096>
Timothy Arceri [Thu, 30 Jan 2020 01:05:14 +0000 (12:05 +1100)]
glsl: add subroutine support to nir linker
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4050>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4050>
Timothy Arceri [Tue, 28 Jan 2020 04:18:14 +0000 (15:18 +1100)]
glsl: dont try to assign uniform storage for uniform blocks
Fixes a crash in some shaders.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4050>
Timothy Arceri [Mon, 27 Jan 2020 05:46:25 +0000 (16:46 +1100)]
glsl: add support for builtins to the nir uniform linker
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4050>
Timothy Arceri [Mon, 27 Jan 2020 02:29:51 +0000 (13:29 +1100)]
glsl: set ShaderStorageBlocksWriteAccess in the nir linker
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4050>
Timothy Arceri [Mon, 3 Feb 2020 23:22:22 +0000 (10:22 +1100)]
glsl: nir linker fix setting of ssbo top level array
This helps correcly set it for each top level member and correctly
handle unsized arrays.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4050>
Timothy Arceri [Fri, 17 Jan 2020 01:07:11 +0000 (12:07 +1100)]
glsl: find the base offset for block members from unnamed blocks
These block member have been split into individual vars so we need
to set the correct offsets for each member in the new glsl nir
linker. We also take this opportunity to set the correct location
for the variable.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4050>
Timothy Arceri [Tue, 21 Jan 2020 03:57:37 +0000 (14:57 +1100)]
glsl: correctly set explicit offsets for struct members
This correctly sets offsets set in glsl when using the nir linker.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4050>
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