Cole Poirier [Sun, 13 Sep 2020 22:34:35 +0000 (15:34 -0700)]
icache.py copy simulation code from dcache.py, fix syntax
Cole Poirier [Sun, 13 Sep 2020 22:06:32 +0000 (15:06 -0700)]
icache.py fix syntax, move all constants and Array/type creation
functions to top of file
Cole Poirier [Sun, 13 Sep 2020 21:26:13 +0000 (14:26 -0700)]
icache.py fix syntax errors that occured when running python3 icache.py
Luke Kenneth Casson Leighton [Sun, 13 Sep 2020 19:11:40 +0000 (20:11 +0100)]
dcache truncate wishbone address, store real_addr in alternative
Luke Kenneth Casson Leighton [Sun, 13 Sep 2020 17:42:36 +0000 (18:42 +0100)]
last mmu get seems ok
Luke Kenneth Casson Leighton [Sun, 13 Sep 2020 17:37:07 +0000 (18:37 +0100)]
whoops recursion error v.shift calculated from v.shift
Luke Kenneth Casson Leighton [Sun, 13 Sep 2020 16:57:34 +0000 (17:57 +0100)]
more experimenting with mmu READ_WAIT state
Luke Kenneth Casson Leighton [Sun, 13 Sep 2020 16:40:39 +0000 (17:40 +0100)]
radix tree wait error, investigating
Luke Kenneth Casson Leighton [Sun, 13 Sep 2020 15:57:04 +0000 (16:57 +0100)]
mmu test starting to make sense
Luke Kenneth Casson Leighton [Sun, 13 Sep 2020 14:40:51 +0000 (15:40 +0100)]
floundering around with MMU unit test, no idea what to do
Luke Kenneth Casson Leighton [Sun, 13 Sep 2020 14:18:17 +0000 (15:18 +0100)]
mmu code-morph
Luke Kenneth Casson Leighton [Sun, 13 Sep 2020 13:43:07 +0000 (14:43 +0100)]
code-morph, add masked function
Luke Kenneth Casson Leighton [Sun, 13 Sep 2020 13:30:33 +0000 (14:30 +0100)]
move code to mmu_0
Luke Kenneth Casson Leighton [Sun, 13 Sep 2020 13:22:34 +0000 (14:22 +0100)]
add example radix walk from power-gem5
Luke Kenneth Casson Leighton [Sun, 13 Sep 2020 13:16:18 +0000 (14:16 +0100)]
MMU test
Luke Kenneth Casson Leighton [Sun, 13 Sep 2020 12:55:46 +0000 (13:55 +0100)]
submodule update
Luke Kenneth Casson Leighton [Sun, 13 Sep 2020 11:39:33 +0000 (12:39 +0100)]
clarify
Luke Kenneth Casson Leighton [Sun, 13 Sep 2020 11:25:24 +0000 (12:25 +0100)]
sort out ariane PLRU, rename/clarify
Luke Kenneth Casson Leighton [Sun, 13 Sep 2020 10:36:59 +0000 (11:36 +0100)]
minor error in plru
Luke Kenneth Casson Leighton [Sun, 13 Sep 2020 10:17:06 +0000 (11:17 +0100)]
rename cache_valid_bits to cache_validsg
Luke Kenneth Casson Leighton [Sun, 13 Sep 2020 10:16:10 +0000 (11:16 +0100)]
cache_valid_idx too large in dcache
Luke Kenneth Casson Leighton [Sun, 13 Sep 2020 09:59:33 +0000 (10:59 +0100)]
whoops, cache valid array too small in dcache
Luke Kenneth Casson Leighton [Sat, 12 Sep 2020 23:07:02 +0000 (00:07 +0100)]
more dcache debugging
Luke Kenneth Casson Leighton [Sat, 12 Sep 2020 22:21:22 +0000 (23:21 +0100)]
missing reservation address comparison
Luke Kenneth Casson Leighton [Sat, 12 Sep 2020 22:17:17 +0000 (23:17 +0100)]
dcache tidyup
Luke Kenneth Casson Leighton [Sat, 12 Sep 2020 20:09:50 +0000 (21:09 +0100)]
more dcache debugging
Luke Kenneth Casson Leighton [Sat, 12 Sep 2020 15:16:03 +0000 (16:16 +0100)]
add random dcache mem test
Luke Kenneth Casson Leighton [Sat, 12 Sep 2020 13:09:43 +0000 (14:09 +0100)]
cache valid corrupted: fixed
Luke Kenneth Casson Leighton [Sat, 12 Sep 2020 10:44:46 +0000 (11:44 +0100)]
adding names to array signals
Luke Kenneth Casson Leighton [Sat, 12 Sep 2020 10:14:38 +0000 (11:14 +0100)]
whoops, indentation error
Luke Kenneth Casson Leighton [Sat, 12 Sep 2020 10:14:22 +0000 (11:14 +0100)]
enable Display debugs
Luke Kenneth Casson Leighton [Sat, 12 Sep 2020 08:36:13 +0000 (09:36 +0100)]
set bytesel in dcache store
Luke Kenneth Casson Leighton [Fri, 11 Sep 2020 20:46:42 +0000 (21:46 +0100)]
separat stbs_done into ld/st
Luke Kenneth Casson Leighton [Fri, 11 Sep 2020 20:15:01 +0000 (21:15 +0100)]
dcache load/store test
Luke Kenneth Casson Leighton [Fri, 11 Sep 2020 18:09:34 +0000 (19:09 +0100)]
debugging dcache
Luke Kenneth Casson Leighton [Fri, 11 Sep 2020 17:55:18 +0000 (18:55 +0100)]
wrong width for data / addr
Luke Kenneth Casson Leighton [Fri, 11 Sep 2020 16:54:50 +0000 (17:54 +0100)]
connect up WB SRAM to dcache test
Luke Kenneth Casson Leighton [Fri, 11 Sep 2020 15:46:35 +0000 (16:46 +0100)]
start on dcache test
Luke Kenneth Casson Leighton [Fri, 11 Sep 2020 15:25:11 +0000 (16:25 +0100)]
missing comb +=
Luke Kenneth Casson Leighton [Fri, 11 Sep 2020 15:22:07 +0000 (16:22 +0100)]
missing maybe_tlb_plrus
Luke Kenneth Casson Leighton [Fri, 11 Sep 2020 14:23:57 +0000 (15:23 +0100)]
WAY_BITS not TLB_WAY_BITS
Luke Kenneth Casson Leighton [Fri, 11 Sep 2020 14:21:05 +0000 (15:21 +0100)]
whoops new node not to be calculated at end
Luke Kenneth Casson Leighton [Fri, 11 Sep 2020 14:14:21 +0000 (15:14 +0100)]
try to get better DTLBUpdate
Luke Kenneth Casson Leighton [Fri, 11 Sep 2020 13:36:13 +0000 (14:36 +0100)]
simplify dcache pending
Luke Kenneth Casson Leighton [Fri, 11 Sep 2020 13:28:47 +0000 (14:28 +0100)]
move dcache pending test to separate module
Luke Kenneth Casson Leighton [Fri, 11 Sep 2020 12:55:51 +0000 (13:55 +0100)]
more error correction in dcache
Luke Kenneth Casson Leighton [Fri, 11 Sep 2020 11:36:47 +0000 (12:36 +0100)]
use module for TLBUpdate
Luke Kenneth Casson Leighton [Fri, 11 Sep 2020 10:26:23 +0000 (11:26 +0100)]
add brackets round if & in dcache
Cole Poirier [Fri, 11 Sep 2020 00:46:49 +0000 (17:46 -0700)]
icache.py add test_icache and icache_sim derived from icache_tb.vhdl
Cole Poirier [Fri, 11 Sep 2020 00:15:50 +0000 (17:15 -0700)]
Merge branch 'master' of git.libre-soc.org:soc
Cole Poirier [Fri, 11 Sep 2020 00:15:20 +0000 (17:15 -0700)]
icache.py fix spelling, syntax
Luke Kenneth Casson Leighton [Thu, 10 Sep 2020 23:48:51 +0000 (00:48 +0100)]
simplify read/write pte
Luke Kenneth Casson Leighton [Thu, 10 Sep 2020 23:38:22 +0000 (00:38 +0100)]
eek, big sort-out of syntax errors in dcache.py, now generates .il
Cole Poirier [Thu, 10 Sep 2020 23:30:23 +0000 (16:30 -0700)]
icache.py rearrange the code within the base class ICache
Luke Kenneth Casson Leighton [Thu, 10 Sep 2020 22:49:19 +0000 (23:49 +0100)]
starting on dcache syntax errors
Luke Kenneth Casson Leighton [Thu, 10 Sep 2020 22:21:47 +0000 (23:21 +0100)]
add PLRU microwatt conversion
Luke Kenneth Casson Leighton [Thu, 10 Sep 2020 16:34:38 +0000 (17:34 +0100)]
add function calls to construct dcache
Luke Kenneth Casson Leighton [Thu, 10 Sep 2020 16:13:13 +0000 (17:13 +0100)]
correct some errors introduced in dcache.py
Luke Kenneth Casson Leighton [Thu, 10 Sep 2020 15:50:43 +0000 (16:50 +0100)]
add docstring for PowerOp class
Luke Kenneth Casson Leighton [Wed, 9 Sep 2020 19:40:27 +0000 (20:40 +0100)]
more laborious line-by-line checking of dcache.py conversion
a subtype integer range 0 to NNN needs a Signal to be declared of
*log2_int(NNN)* not Signal(NNN)
Cole Poirier [Wed, 9 Sep 2020 15:05:59 +0000 (08:05 -0700)]
icache.py complete first translation pass of icache.vhdl
Luke Kenneth Casson Leighton [Tue, 8 Sep 2020 20:10:27 +0000 (21:10 +0100)]
add PowerDecoder explanation
Luke Kenneth Casson Leighton [Tue, 8 Sep 2020 18:12:26 +0000 (19:12 +0100)]
bit of a mess, trying to get PowerDecode to not create empty subdecoders
Luke Kenneth Casson Leighton [Tue, 8 Sep 2020 15:02:03 +0000 (16:02 +0100)]
subset columns for PowerDecoder - bit of a mess (done by hand)
Luke Kenneth Casson Leighton [Tue, 8 Sep 2020 13:46:14 +0000 (14:46 +0100)]
create a special subset of Decoder Record for storing "main" decoder info
this has to store Trap info however everything else is optional
Luke Kenneth Casson Leighton [Tue, 8 Sep 2020 13:09:35 +0000 (14:09 +0100)]
pass in state into PowerDecode2, save on eqs and wires
Luke Kenneth Casson Leighton [Tue, 8 Sep 2020 13:09:06 +0000 (14:09 +0100)]
give Decode2Execute1Type in core a name
Luke Kenneth Casson Leighton [Tue, 8 Sep 2020 13:05:13 +0000 (14:05 +0100)]
argh, somehow EINT check got moved out of if/elif block
Luke Kenneth Casson Leighton [Tue, 8 Sep 2020 12:37:27 +0000 (13:37 +0100)]
capture trap / irq conditions in flags for debug purposes
Luke Kenneth Casson Leighton [Tue, 8 Sep 2020 12:16:21 +0000 (13:16 +0100)]
pass in CoreState to PowerDecoder rather than eq a copy of it
Luke Kenneth Casson Leighton [Tue, 8 Sep 2020 09:52:37 +0000 (10:52 +0100)]
whoops trap address being set in wrong Decode2ExecuteType object
Luke Kenneth Casson Leighton [Tue, 8 Sep 2020 08:06:11 +0000 (09:06 +0100)]
add cxxsim option
Luke Kenneth Casson Leighton [Mon, 7 Sep 2020 21:31:34 +0000 (22:31 +0100)]
use PowerDecoderSubsets for FUs, except for TRAP which uses the main one
this because the TRAP gets rewritten
Luke Kenneth Casson Leighton [Mon, 7 Sep 2020 21:14:36 +0000 (22:14 +0100)]
add per-FU PowerDecoders. should now be subsettable
Luke Kenneth Casson Leighton [Mon, 7 Sep 2020 21:01:01 +0000 (22:01 +0100)]
create eq_from function based on eq_from_execute1
Luke Kenneth Casson Leighton [Mon, 7 Sep 2020 18:24:53 +0000 (19:24 +0100)]
debug print statement in eq_from_execute
Luke Kenneth Casson Leighton [Mon, 7 Sep 2020 18:24:34 +0000 (19:24 +0100)]
oe_ok renamed to oe, needed in regspec_decode_read
Luke Kenneth Casson Leighton [Mon, 7 Sep 2020 18:24:08 +0000 (19:24 +0100)]
add insn and fn_unit to CompLDSTOpSubset
Luke Kenneth Casson Leighton [Mon, 7 Sep 2020 18:23:50 +0000 (19:23 +0100)]
add pspec and opsubsetkls to CompUnits
Cole Poirier [Mon, 7 Sep 2020 19:38:56 +0000 (12:38 -0700)]
icache.py commit translation progress, about one third left
Luke Kenneth Casson Leighton [Mon, 7 Sep 2020 17:14:25 +0000 (18:14 +0100)]
make immediate decoding optional on-demand
Luke Kenneth Casson Leighton [Mon, 7 Sep 2020 17:13:33 +0000 (18:13 +0100)]
whoops spelling mistake outOut_carry not outPut_carry
Luke Kenneth Casson Leighton [Mon, 7 Sep 2020 16:22:52 +0000 (17:22 +0100)]
convert mul test to use Power Decode subset
Luke Kenneth Casson Leighton [Mon, 7 Sep 2020 16:18:25 +0000 (17:18 +0100)]
convert shift_rot to subset decoder
Luke Kenneth Casson Leighton [Mon, 7 Sep 2020 16:16:27 +0000 (17:16 +0100)]
convert branch test to PowerDecodeSubset form
Luke Kenneth Casson Leighton [Mon, 7 Sep 2020 16:13:09 +0000 (17:13 +0100)]
convert CR to PowerDecodeSubset format
Luke Kenneth Casson Leighton [Mon, 7 Sep 2020 15:59:40 +0000 (16:59 +0100)]
bit of a big reorg of data structures
ALU test_pipe_caller.py is now testing with a subset PowerDecoder2
and the field names need to change to match up.
Luke Kenneth Casson Leighton [Mon, 7 Sep 2020 15:14:11 +0000 (16:14 +0100)]
split out PowerDecode2 into PowerDecodeSubset
Luke Kenneth Casson Leighton [Mon, 7 Sep 2020 13:40:25 +0000 (14:40 +0100)]
large stack of moving stuff around in dcache
Luke Kenneth Casson Leighton [Mon, 7 Sep 2020 13:11:32 +0000 (14:11 +0100)]
adjust indentation of dcache_slow
Luke Kenneth Casson Leighton [Mon, 7 Sep 2020 13:01:22 +0000 (14:01 +0100)]
more dcache translation
Luke Kenneth Casson Leighton [Mon, 7 Sep 2020 12:24:42 +0000 (13:24 +0100)]
add start on cache_ram.vhdl to nmigen conversion
Luke Kenneth Casson Leighton [Mon, 7 Sep 2020 12:22:45 +0000 (13:22 +0100)]
more dcache translation
Luke Kenneth Casson Leighton [Mon, 7 Sep 2020 11:00:36 +0000 (12:00 +0100)]
allow Decode2ToExecute1Type to take an opkls argument
Luke Kenneth Casson Leighton [Mon, 7 Sep 2020 10:58:30 +0000 (11:58 +0100)]
whoops truncated the mb and me fields
Luke Kenneth Casson Leighton [Mon, 7 Sep 2020 00:01:39 +0000 (01:01 +0100)]
minor reorg on PowerDecoder
Luke Kenneth Casson Leighton [Sun, 6 Sep 2020 21:31:17 +0000 (22:31 +0100)]
comment, nothing unusual when Trap Type is DEC
Luke Kenneth Casson Leighton [Sun, 6 Sep 2020 21:21:09 +0000 (22:21 +0100)]
decoder immediate b split out to DecodeBImm
Luke Kenneth Casson Leighton [Sun, 6 Sep 2020 21:16:00 +0000 (22:16 +0100)]
decoder immediate a split out to DecodeAImm
Luke Kenneth Casson Leighton [Sun, 6 Sep 2020 20:42:51 +0000 (21:42 +0100)]
add row subset selector for PowerDecode.
allows functions to be used to create subset decoders