mesa: Remove __SSE4_1__ guards from sse_minmax.c.

See commit e07c9a288.

Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/vec4: Do separate copy followed by constant propagation after opt_vector_float().

total instructions in shared programs: 5877012 -> 5876617 (-0.01%)
instructions in affected programs:     33140 -> 32745 (-1.19%)

From before the commit that allows VF constant propagation (which hurt
some programs) to here, the results are:

total instructions in shared programs: 5877951 -> 5876617 (-0.02%)
instructions in affected programs:     123444 -> 122110 (-1.08%)

with no programs hurt.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965/vec4: Allow constant propagation of VF immediates.

total instructions in shared programs: 5877951 -> 5877012 (-0.02%)
instructions in affected programs:     155923 -> 154984 (-0.60%)

Helps 1233, hurts 156 shaders. The hurt shaders are addressed in the
next commit.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965/vec4: Add parameter to skip doing constant propagation.

After CSEing some MOV ..., VF instructions we have code like

   mov tmp, [1F, 2F, 3F, 4F]VF
   mov r10, tmp
   mov r11, tmp
   ...
   use r10
   use r11

We want to copy propagate tmp into the uses of r10 and r11, but *not*
constant propagate the VF immediate into the uses of tmp.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965/vec4: Do CSE, copy propagation, and DCE after opt_vector_float().

total instructions in shared programs: 5869005 -> 5868220 (-0.01%)
instructions in affected programs:     70208 -> 69423 (-1.12%)

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965/vec4: Perform CSE on MOV ..., VF instructions.

Port of commit a28ad9d4 from the fs backend.

No shader-db changes since we don't emit MOV ..., VF instructions yet.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965/vec4: Add pass to gather constants into a vector-float MOV.

Currently only handles consecutive instructions with the same
destination that collectively write all channels.

total instructions in shared programs: 5879798 -> 5869011 (-0.18%)
instructions in affected programs:     465236 -> 454449 (-2.32%)

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965: Add support for saturating immediates.

I don't feel great about assert(!"unimplemented: ...") but these
cases do only seem possible under some currently impossible circumstances.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965: Add fs_reg/src_reg constructors that take vf[4].

Sometimes it's easier to generate 4x values into an array, and the
memcpy is 1 instruction, rather than 11 to piece 4 arguments together.

I'd forgotten to remove the prototype from fs_reg from a previous patch,
so it's already there for us here.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

gallium/target: Drop no longer needed Haiku viewport override

* Drop no longer needed mesa headers
* Haiku LLVM pipe working with LLVM 3.5.0 on x86_64

gallium/st: Clean up Haiku depth mapping, fix colorspace errors

vc4: Handle unaligned accesses in CL emits.

As of 229bf4475ff0a5dbeb9bc95250f7a40a983c2e28 we started getting SIBGUS
from unaligned accesses on the hardware, for reasons I haven't figured
out.  However, we should be avoiding unaligned accesses anyway, and our CL
setup certainly would have produced them.

vc4: Don't bother zero-initializing the shader reloc indices.

They should all be set to real values by the time they're read, and
ideally if you used valgrind you'd see uninitialized value uses.

vc4: Fix the argument type for cl_u16().

It doesn't matter, since it just got truncated to 16 inside, anyway.

egl: Fix non-dri SCons builds re #87657

* Revert change to egl main producing Shared Libraries
* Check for dri before including dri code

radeonsi: Don't modify PA_SC_RASTER_CONFIG register value if rb_mask == 0

E.g. this could happen on older kernels which don't support the
RADEON_INFO_SI_BACKEND_ENABLED_MASK query yet. The code in
si_write_harvested_raster_configs() doesn't deal with this correctly and
would probably mangle the value badly.

Cc: "10.4 10.3" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

vc4: Optimize CL emits by doing size checks up front.

The optimizer obviously doesn't have the ability to rewrite these to skip
the size checks per call, so we have to do it manually.

Improves a norast benchmark on simulation by 0.779706% +/- 0.405838%
(n=6087).

vc4: Avoid repeated hindex lookups in the loop over tiles.

Improves norast performance of a microbenchmark by 11.1865% +/- 2.37673%
(n=20).

i965: Add missing BRW_NEW_*_PROG_DATA to texture/renderbuffer atoms.

This was probably missed when moving from a fixed binding table layout
to a dynamic one that changes based on the shader.

Fixes newly proposed Piglit test fbo-mrt-new-bind.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=87619
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Mike Stroyan <mike@LunarG.com>
Cc: "10.4 10.3" <mesa-stable@lists.freedesktop.org>

i965: Cache register write capability checks.

Our ability to perform register writes depends on the hardware and
kernel version.  It shouldn't ever change on a per-context basis,
so we only need to check once.

Checking introduces a synchronization point between the CPU and GPU:
even though we submit very few GPU commands, the GPU might be busy doing
other work, which could cause us to stall for a while.

On an idle i7 4750HQ, this improves performance in OglDrvCtx (a context
creation microbenchmark) by 6.14748% +/- 1.6837% (n=20).  With Unigine
Valley running in the background (to keep the GPU busy), it improves
performance in OglDrvCtx by 2290.92% +/- 29.5274% (n=5).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

freedreno/ir3: split out legalize pass

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/ir3: ra debug

Some compile time RA debug

Signed-off-by: Rob Clark <robclark@freedesktop.org>

egl/haiku: Clean up SConscript whitespace

egl/dri2: Fix build of dri2 egl driver with SCons

* egl/dri2 was missing a SConscript
* Problem caught by Adrián Arroyo Calle

egl: Clean up Haiku visual creation

* Only create one struct
* 'final' also is a language conflict
* Some style cleanup

egl: Add Haiku code and support

* This is the cleaned up work of the Haiku GCI student
  Adrián Arroyo Calle adrian.arroyocalle@gmail.com
* Several patches were consolidated to prevent
  unnecessary touching of non-related code

glsl: check if implicitly sized arrays match explicitly sized arrays across the same stage

V2: Improve error message.

Signed-off-by: Timothy Arceri <t_arceri@yahoo.com.au>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

i965: Use safer pointer arithmetic in gather_oa_results()

This patch reduces the likelihood of pointer arithmetic overflow bugs in
gather_oa_results(), like the one fixed by b69c7c5dac.

I haven't yet encountered any overflow bugs in the wild along this
patch's codepath. But I get nervous when I see code patterns like this:

   (void*) + (int) * (int)

I smell 32-bit overflow all over this code.

This patch retypes 'snapshot_size' to 'ptrdiff_t', which should fix any
potential overflow.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>

i965: Use safer pointer arithmetic in intel_texsubimage_tiled_memcpy()

This patch reduces the likelihood of pointer arithmetic overflow bugs in
intel_texsubimage_tiled_memcpy() , like the one fixed by b69c7c5dac.

I haven't yet encountered any overflow bugs in the wild along this
patch's codepath. But I recently solved, in commit b69c7c5dac, an overflow
bug in a line of code that looks very similar to pointer arithmetic in
this function.

This patch conceptually applies the same fix as in b69c7c5dac. Instead
of retyping the variables, though, this patch adds some casts. (I tried
to retype the variables as ptrdiff_t, but it quickly got very messy. The
casts are cleaner).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>

i965: Fix intel_miptree_map() signature to be more 64-bit safe

This patch should diminish the likelihood of pointer arithmetic overflow
bugs, like the one fixed by b69c7c5dac.

Change the type of parameter 'out_stride' from int to ptrdiff_t. The
logic is that if you call intel_miptree_map() and use the value of
'out_stride', then you must be doing pointer arithmetic on 'out_ptr'.
Using ptrdiff_t instead of int should make a little bit harder to hit
overflow bugs.

As a side-effect, some function-scope variables needed to be retyped to
avoid compilation errors.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>

i965: Remove spurious casts in copy_image_with_memcpy()

If a pointer points to raw, untyped memory and is never dereferenced,
then declare it as 'void*' instead of casting it to 'void*'.

Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

radeonsi: force NaNs to 0

This fixes incorrect rendering in Unreal Engine demos.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83510

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

st/nine: fix DBG typo (trivial)

Signed-off-by: David Heidelberg <david@ixit.cz>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

r300g: implement ARR opcode

Same as ARL, just has extra rounding.
Useful for st/nine.

Tested-by: Pavel Ondračka <pavel.ondracka@email.cz>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

freedreno/a4xx: blend-color

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/a4xx: alpha-test

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno: update generated headers

freedreno/ir3: trans_kill cleanup

trans_kill() only handles the single opcode.  Drop the remnant of a time
when both KILL and KILL_IF were handled by the same fxn.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/ir3: hack for standalone compiler

Standalone compiler doesn't have screen or context.  We need to come up
with a better way to control the target arch (ie. something that we can
control from cmdline w/ standalone compiler) but for now this hack keeps
it from segfault'ing.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

i965/fs: Add missing const qualifier.

vc4: Coalesce MOVs into VPM with the instructions generating the values.

total instructions in shared programs: 41168 -> 40976 (-0.47%)
instructions in affected programs:     18156 -> 17964 (-1.06%)

vc4: Redefine VPM writes as a (destination) QIR register file.

This will let me coalesce the VPM writes into the instructions generating
the values.

docs: note change in minimum GCC version to 4.2.0

Signed-off-by: Timothy Arceri <t_arceri@yahoo.com.au>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Matt Turner <mattst88@gmail.com>

gallium: remove support for GCC older than 4.2.0

Signed-off-by: Timothy Arceri <t_arceri@yahoo.com.au>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: bump required GCC version to 4.2.0

It turns out Mesa hasn't compiled on less then 4.2 for a while
 so update conf to reflect this.

Signed-off-by: Timothy Arceri <t_arceri@yahoo.com.au>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

vc4: Add support for turning constant uniforms into small immediates.

Small immediates have the downside of taking over the raddr B field, so
you might have less chance to pack instructions together thanks to raddr B
conflicts.  However, it also reduces some register pressure since it lets
you load 2 "uniform" values in one instruction (avoiding a previous load
of the constant value to a register), and increases some pairing for the
same reason.

total uniforms in shared programs: 16231 -> 13374 (-17.60%)
uniforms in affected programs:     10280 -> 7423 (-27.79%)
total instructions in shared programs: 40795 -> 41168 (0.91%)
instructions in affected programs:     25551 -> 25924 (1.46%)

In a previous version of this patch I had a reduction in instruction count
by forcing the other args alongside a SMALL_IMM to be in the A file or
accumulators, but that increases register pressure and had a bug in
handling FRAG_Z.  In this patch is I just use raddr conflict resolution,
which is more expensive.  I think I'd rather tweak allocation to have some
way to slightly prefer good choices for files in general, rather than risk
failing to register allocate by forcing things into register classes.

vc4: Move follow_movs() to common QIR code.

I want this from other passes.

vc4: Fix missing newline for load immediate instruction disasm.

mesa: Remove unnecessary -f from $(RM).

$(RM) includes -f.

mesa: Remove tarballs/checksum rules.

gallium: Add egl and gbm to distribution.

mesa: Set DISTCHECK_CONFIGURE_FLAGS.

Enable some non-default options that distros are likely to use.

targets/xvmc: Add uninstall hooks to handle megadriver hardlinks.

targets/vdpau: Add uninstall hooks to handle megadriver hardlinks.

targets/vdpau: Add clean-local rule to remove .lib links.

vc4: Add a userspace BO cache.

Since our kernel BOs require CMA allocation, and the use of them requires
new mmaps, it's pretty expensive and we should avoid it if possible.
Copying my original design for Intel, make a userspace cache that reuses
BOs that haven't been shared to other processes but frees BOs that have
sat in the cache for over a second.

Improves glxgears framerate on RPi by around 30%.

vc4: Add dmabuf support.

This gets DRI3 working on modesetting with glamor.  It's not enabled under
simulation, because it looks like handing our dumb-allocated buffers off
to the server doesn't actually work for the server's rendering.

vc4: Drop a weird argument in the BOs-from-handles API.

draw: revert using correct order for prim decomposition.

This reverts db3dfcfe90a3d27e6020e0d3642f8ab0330e57be.
The commit was correct but we've got some precision problems later in
llvmpipe (or possibly in draw clip) due to the vertices coming in in
different order, causing some internal test failures. So revert for now.
(Will only affect drivers which actually support constant-interpolated
attributes and not just flatshading.)

util: Silence signed-unsigned comparison warnings

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

i965: Require pixel alignment for GPU copy blit

The blitter will start at a pixel's natural alignment. For PBOs, if the
provided offset if not aligned, bits will get dropped.

This change adds offset alignment check for src and dst, kicking back if
the requirements are not met.

The change is based on following verbiage from BSPEC:
 Color pixel sizes supported are 8, 16, and 32 bits per pixel (bpp).
 All pixels are naturally aligned.

Found in the following locations:
page 35 of intel-gfx-prm-osrc-hsw-blitter.pdf
page 29 of ivb_ihd_os_vol1_part4.pdf
page 29 of snb_ihd_os_vol1_part5.pdf

This behavior was observed with Steam Big Picture rendering incorrect
icon colors.  The fix has been tested on Ubuntu and SteamOS on Haswell.

Signed-off-by: Cody Northrop <cody@lunarg.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83908
Reviewed-by: Neil Roberts <neil@linux.intel.com>

i965: remove includes of sampler.h from extern "C" blocks

C linkage was removed from functions in program/sampler.cpp.  However,
some cpp files include program/sampler.h within extern "C" blocks,
causing link errors for test_vec4_copy_propagation.

Reviewed-by: Brian Paul <brianp@vmware.com>
Tested-by: Ian Romanick <ian.d.romanick@intel.com>

i965/query: Cache whether the batch references the query BO.

Chris Wilson noted that repeated calls to CheckQuery() would call
drm_intel_bo_references(brw->batch.bo, query->bo) on each invocation,
which is expensive.  Once we've flushed, we know that future batches
won't reference query->bo, so there's no point in asking more than once.

This patch adds a brw_query_object::flushed flag, which is a
conservative estimate of whether the batch has been flushed.

On the first call to CheckQuery() or WaitQuery(), we check if the
batch references query->bo.  If not, it must have been flushed for
some reason (such as being full).  We record that it was flushed.
If it does reference query->bo, we explicitly flush, and record that
we did so.

Any subsequent checks will simply see that query->flushed is set,
and skip the drm_intel_bo_references() call.

Inspired by a patch from Chris Wilson.

According to Eero, this does not affect the performance of Witcher 2
on Haswell, but approximately halves the userspace CPU usage.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86969
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965/query: Use brw_bo_map to handle stall warnings.

This is less code and also measures the duration of the stall for us.

Our old code predates the existance of brw_bo_map().

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965/query: Remove redundant drm_intel_bo_references call in CheckQuery.

CheckQuery calls drm_intel_bo_references to see if the batch references
the query BO, and if so, flushes.  It then checks if the query BO is
busy, and if not, calls gen6_queryobj_get_results().

Stupidly, gen6_queryobj_get_results() immediately did a second redundant
drm_intel_bo_references check, even though we know the buffer is not
referenced and in fact idle.

This patch moves the batch-flush check out of gen6_queryobj_get_results
and into WaitQuery() (the other caller).  That way, both callers do a
single batch-flush check.

This should only be a minor improvement, since it would only affect
the first CheckQuery call where the result is actually available.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86969
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965/query: Add query->bo == NULL early return in CheckQuery hook.

If query->bo == NULL, this is a redundant CheckQuery call, and we
should simply return.  We didn't do anything anyway - we skipped the
batch flushing block, and although we called get_results(), it has an
early return and does nothing.  Why bother?

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965/query: Set Ready flag in gen6_queryobj_get_results().

q->Ready means that the results are in, and core Mesa is free to return
them to the application.  gen6_queryobj_get_results() is a natural place
to set that flag; doing so means callers don't have to.

The older non-hardware-context aware code couldn't do this, because we
had to call brw_queryobj_get_results() to gather intermediate results
when we ran out of space for snapshots in the query buffer.  We only
gather complete results in the Gen6+ code, however.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

vc4: Add support for turning add-based MOVs to muls for pairing.

total instructions in shared programs: 43053 -> 40795 (-5.24%)
instructions in affected programs:     37996 -> 35738 (-5.94%)

vc4: Add a helper for changing a field in an instruction.

vc4: Fix the name of qpu_waddr_ignores_ws().

We're deciding about the WS bit, not PM.

docs: note change in minimum GCC version to 4.1.0

Signed-off-by: Timothy Arceri <t_arceri@yahoo.com.au>
Reviewed-by: Matt Turner <mattst88@gmail.com>

util: remove support for GCC older than 4.1.0

Signed-off-by: Timothy Arceri <t_arceri@yahoo.com.au>
Reviewed-By: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: remove support for GCC older than 4.1.0

Signed-off-by: Timothy Arceri <t_arceri@yahoo.com.au>
Reviewed-By: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

gbm: remove support for GCC older than 4.1.0

Signed-off-by: Timothy Arceri <t_arceri@yahoo.com.au>
Reviewed-By: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

gallium: remove support for GCC older than 4.1.0

Signed-off-by: Timothy Arceri <t_arceri@yahoo.com.au>
Reviewed-By: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

egl: remove support for GCC older than 4.1.0

Signed-off-by: Timothy Arceri <t_arceri@yahoo.com.au>
Reviewed-By: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: bump required GCC version to 4.1.0

Signed-off-by: Timothy Arceri <t_arceri@yahoo.com.au>
Reviewed-By: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: remove support for GCC older than 3.3.0

GCC >=3.3 has been required since 9aa3aa71386394725ce88df463d6183f62777ee5

Signed-off-by: Timothy Arceri <t_arceri@yahoo.com.au>
Reviewed-By: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/fs: Add a comment explaining what saturate propagation does.

vc4: Add support for enabling early Z discards.

This is the same basic logic from the original Broadcom driver.

st/mesa: remove extern "C" around #includes in st_glsl_to_tgsi.cpp

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

program: remove extern "C" usage in sampler.cpp

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

program: remove extern "C" around #includes

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

glsl: remove extern "C" around #includes

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

st/mesa: add extern "C" to st_context.h

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

st/mesa: add extern "C" to st_program.h

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

main: remove extern C around #includes in ff_fragment_shader.cpp

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

mesa: move #include of mtypes.h outside __cplusplus check

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

program: add #ifndef SAMPLER_H wrapper

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

mesa: put extern "C" in src/mesa/program/*h header files

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

mesa: put extern "C" in header files

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

mapi: add glapi-test and shared-glapi-test to .gitignore

On the same go remove src/mapi/shared-glapi/tests/.gitignore
and src/mapi/glapi/tests/.gitignore as useless.

Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

util: add u_atomic_test to .gitignore

Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

glx: remove __glXstrdup()

I didn't find this being used anywhere

Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: add test_vf_float_conversions to .gitignore

Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Make validate_reg tables constant

Declare local tables constant.

Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

glsl: remove commented out code

MaxGeometryOutputComponents is used as the value
for gl_MaxGeometryVaryingComponents

Acked-by: Matt Turner <mattst88@gmail.com>

i965: remove commented out code

Acked-by: Matt Turner <mattst88@gmail.com>

nvc0: add missed PIPE_CAP_VERTEXID_NOBASE

Commit ade8b26bf missed adding this cap to nvc0.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

st/mesa: use vertex id lowering according to pipe cap bit.

Tested with llvmpipe by setting the cap bit temporarily, seems to work,
though no driver requests it for now.