Luke Kenneth Casson Leighton [Tue, 9 Jun 2020 22:38:39 +0000 (23:38 +0100)]
experimenting with CR/LR/XER etc in qemu
Luke Kenneth Casson Leighton [Tue, 9 Jun 2020 22:12:58 +0000 (23:12 +0100)]
add means to get pc and other qemu registers
Luke Kenneth Casson Leighton [Tue, 9 Jun 2020 17:53:35 +0000 (18:53 +0100)]
rename truncaddr to splitaddr, return LSBs and MSBs
Luke Kenneth Casson Leighton [Tue, 9 Jun 2020 17:53:09 +0000 (18:53 +0100)]
add len-expander to L0CacheBuffer, so as to be able to mask the LD/ST data
Luke Kenneth Casson Leighton [Tue, 9 Jun 2020 17:33:22 +0000 (18:33 +0100)]
allow LenExpand to output both byte- and bit- mask expansion
Tobias Platen [Tue, 9 Jun 2020 13:05:10 +0000 (15:05 +0200)]
Luke Kenneth Casson Leighton [Tue, 9 Jun 2020 13:01:06 +0000 (14:01 +0100)]
expand LenExpand (haha) to cover bytes, with an argument "cover"
all puns intentional
Tobias Platen [Tue, 9 Jun 2020 12:34:34 +0000 (14:34 +0200)]
elaborate function for DualPortSplitter
Cesar Strauss [Tue, 9 Jun 2020 11:57:31 +0000 (08:57 -0300)]
Avoid a combinatorial loop on valid_o
The path was:
all_rd (1) -> all_rd_pulse (1) -> alui_l.s (1) ->
-> alu.p.valid_i (1) -> ALU (zero-delay) -> alu.n.valid_o (1) ->
-> rok_l.r (1) -> all_rd (0)
Decided to break the loop on the reset of the read-done, write proceed
latch (rok_l.r), with no ill effects on performance.
Added a test case for this, using the zero-delay ALU (OP_NOP).
Tobias Platen [Tue, 9 Jun 2020 12:00:50 +0000 (14:00 +0200)]
fixes for DualPortSplitter
Luke Kenneth Casson Leighton [Tue, 9 Jun 2020 11:09:11 +0000 (12:09 +0100)]
make DataMerger record reset_less
Luke Kenneth Casson Leighton [Tue, 9 Jun 2020 11:08:32 +0000 (12:08 +0100)]
add truncaddr function to L0CacheBuffer test class
Luke Kenneth Casson Leighton [Tue, 9 Jun 2020 11:08:12 +0000 (12:08 +0100)]
add convenience variables in TestMemory
Luke Kenneth Casson Leighton [Tue, 9 Jun 2020 10:50:51 +0000 (11:50 +0100)]
map LDST len directly, rather than go through a switch statement
Luke Kenneth Casson Leighton [Tue, 9 Jun 2020 10:49:07 +0000 (11:49 +0100)]
correct local variable references
Luke Kenneth Casson Leighton [Tue, 9 Jun 2020 10:48:23 +0000 (11:48 +0100)]
bit more on TRAP handling (preparing priv instruction)
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 22:52:54 +0000 (23:52 +0100)]
add traptype and trapaddr to PowerDecoder2. idea is to actually *change*
the instruction depending on conditions detected by the decoder
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 22:51:44 +0000 (23:51 +0100)]
add traptype and trapaddr to trap_input_data.py
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 22:30:57 +0000 (23:30 +0100)]
add "instr_is_privileged" to power_decoder2 (untested)
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 22:20:22 +0000 (23:20 +0100)]
use 2nd shortened convenience variable in PowerDecoder2
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 22:18:48 +0000 (23:18 +0100)]
use shortened convenience variable in PowerDecoder2
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 19:04:45 +0000 (20:04 +0100)]
re-add unit tests back in
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 18:26:51 +0000 (19:26 +0100)]
add comment docstring about POWER9 simulator
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 17:52:42 +0000 (18:52 +0100)]
more verbose debug information tracking down SO/OV/OV32
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 17:51:23 +0000 (18:51 +0100)]
whoops, overflow-decode (handle_overflow) needed to check e.oe.ok
*and* e.oe.oe to decide whether to set SO/OV/OV32
Michael Nolan [Mon, 8 Jun 2020 17:45:59 +0000 (13:45 -0400)]
Add register assertions, fix broken tests
Michael Nolan [Mon, 8 Jun 2020 17:45:50 +0000 (13:45 -0400)]
Update to latest wiki version
Michael Nolan [Mon, 8 Jun 2020 17:36:57 +0000 (13:36 -0400)]
Restore test_sim.py, begin modifying it for testing against qemu
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 14:59:31 +0000 (15:59 +0100)]
add CA/CA32 to write regs fields in parser
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 14:58:53 +0000 (15:58 +0100)]
check that carry has already been done or not by the actual instruction
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 14:44:58 +0000 (15:44 +0100)]
code-morph test_core for XER bit clarity
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 14:44:33 +0000 (15:44 +0100)]
set only the SO bit as sticky, not the OV flags as sticky
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 14:28:02 +0000 (15:28 +0100)]
copy 64-bit OV, try creating 32-bit OV32 in
simulator caller.py
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 14:08:58 +0000 (15:08 +0100)]
clarify using microwatt calc_ov function.
found bug where part of the comparison was not using carry
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 13:50:35 +0000 (14:50 +0100)]
added check which shows that OV32 in "adde." is not correct
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 12:55:34 +0000 (13:55 +0100)]
found section in 3.0B PDF that refers to "Program Interrupts"
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 12:33:31 +0000 (13:33 +0100)]
move datamerger proof into standard directory location (formal/),
update comments
Luke Kenneth Casson Leighton [Mon, 8 Jun 2020 02:08:03 +0000 (03:08 +0100)]
copy MSR into SRR1 in trap function
colepoirier [Mon, 8 Jun 2020 01:17:43 +0000 (18:17 -0700)]
Fix spelling
Luke Kenneth Casson Leighton [Sun, 7 Jun 2020 21:18:16 +0000 (22:18 +0100)]
update trap with comments
Luke Kenneth Casson Leighton [Sun, 7 Jun 2020 21:11:48 +0000 (22:11 +0100)]
update comments
colepoirier [Sun, 7 Jun 2020 21:09:17 +0000 (14:09 -0700)]
Add TrapMainStage.trap() convenience function to set trap address and PC
to begin from on return
Cesar Strauss [Sun, 7 Jun 2020 20:47:10 +0000 (17:47 -0300)]
Assign the one-clock delay operation from ADD to SHR
This keeps the ADD delay as it was, originally.
Luke Kenneth Casson Leighton [Sun, 7 Jun 2020 20:48:20 +0000 (21:48 +0100)]
assert XER SO/OV/CA registers, check these are ok (fail at the moment)
Luke Kenneth Casson Leighton [Sun, 7 Jun 2020 20:20:37 +0000 (21:20 +0100)]
add debug print statements, re-enable all tests in simple core
Luke Kenneth Casson Leighton [Sun, 7 Jun 2020 20:15:58 +0000 (21:15 +0100)]
resolved CR mfcr lookup bug (was in power_decoder. ??)
https://bugs.libre-soc.org/show_bug.cgi?id=363
Cesar Strauss [Sun, 7 Jun 2020 19:40:44 +0000 (16:40 -0300)]
Try responding with ready_i on the same cycle as valid_o
Cesar Strauss [Sun, 7 Jun 2020 19:37:32 +0000 (16:37 -0300)]
Assert valid_o one clock early, as alu_done is asserted
Cesar Strauss [Sun, 7 Jun 2020 19:32:11 +0000 (16:32 -0300)]
Make the test ALU conform to the valid/ready protocol
Adjust the test case accordingly.
colepoirier [Sun, 7 Jun 2020 01:50:42 +0000 (18:50 -0700)]
Add back test cases to cookie-cut from for fu/trap/test/test_pipe_caller
Luke Kenneth Casson Leighton [Sun, 7 Jun 2020 19:43:56 +0000 (20:43 +0100)]
add extra tests for mcrf: shows bug is not directly related to core.py
Luke Kenneth Casson Leighton [Sun, 7 Jun 2020 18:58:45 +0000 (19:58 +0100)]
how odd. just adding CA32 to self.namespace seems to work
Luke Kenneth Casson Leighton [Sun, 7 Jun 2020 18:31:05 +0000 (19:31 +0100)]
add extra args to ISA in branch test_pipe_caller
Luke Kenneth Casson Leighton [Sun, 7 Jun 2020 15:03:12 +0000 (16:03 +0100)]
add msr to ISA in test_core.py
Luke Kenneth Casson Leighton [Sun, 7 Jun 2020 14:30:02 +0000 (15:30 +0100)]
wark-wark, do not & rs[0] into carry-out from rotator
Luke Kenneth Casson Leighton [Sun, 7 Jun 2020 14:27:38 +0000 (15:27 +0100)]
ha! set XER CA/CA32 in simulator from output.value, not using eq
Luke Kenneth Casson Leighton [Sun, 7 Jun 2020 14:23:20 +0000 (15:23 +0100)]
update rotator.py to match microwatt rotator.vhdl
Luke Kenneth Casson Leighton [Sun, 7 Jun 2020 13:46:56 +0000 (14:46 +0100)]
add carry test to shift_rot test_pipe_caller: it fails just as with the compunit test
Luke Kenneth Casson Leighton [Sun, 7 Jun 2020 13:42:26 +0000 (14:42 +0100)]
add extra args to ISA in test_pipe_caller.py
Luke Kenneth Casson Leighton [Sun, 7 Jun 2020 13:22:50 +0000 (14:22 +0100)]
add make clean target to qemu_test Makefile
Luke Kenneth Casson Leighton [Sun, 7 Jun 2020 13:04:09 +0000 (14:04 +0100)]
optionally writing out CA/CA32 to XER
Luke Kenneth Casson Leighton [Sun, 7 Jun 2020 12:58:08 +0000 (13:58 +0100)]
add handling of CA/CA32 in simulator, generated from sraw/srad
Luke Kenneth Casson Leighton [Sun, 7 Jun 2020 12:37:17 +0000 (13:37 +0100)]
add CA/CA32 to list of special regs
Luke Kenneth Casson Leighton [Sun, 7 Jun 2020 12:26:58 +0000 (13:26 +0100)]
add missing arg to ISA in test_compunit
Luke Kenneth Casson Leighton [Sun, 7 Jun 2020 12:24:29 +0000 (13:24 +0100)]
Revert "if referred to through GPR (GPR[RA]), add to read_regs in parser"
This reverts commit
18db92ba0f33dfcd036eeddbc42c54eb3cf06ce3.
Luke Kenneth Casson Leighton [Sun, 7 Jun 2020 12:22:46 +0000 (13:22 +0100)]
Revert "remove fixedlogical.patch - added gprs to PowerParser p_atom_name"
This reverts commit
f61f93dcd82ef64a82fae8e2ee94987ba9794ce8.
Luke Kenneth Casson Leighton [Sun, 7 Jun 2020 12:22:23 +0000 (13:22 +0100)]
Revert "add gprs to PowerParser write_regs in p_atom_name"
This reverts commit
11134dd94c4a1d1c1cff15e75d12b50c19c80b36.
Luke Kenneth Casson Leighton [Sun, 7 Jun 2020 12:16:23 +0000 (13:16 +0100)]
add extra missing args to ISA setup in alu test_pipe_caller
Luke Kenneth Casson Leighton [Sun, 7 Jun 2020 12:12:19 +0000 (13:12 +0100)]
if referred to through GPR (GPR[RA]), add to read_regs in parser
Luke Kenneth Casson Leighton [Sun, 7 Jun 2020 11:55:41 +0000 (12:55 +0100)]
add gprs to PowerParser write_regs in p_atom_name
Luke Kenneth Casson Leighton [Sun, 7 Jun 2020 11:55:13 +0000 (12:55 +0100)]
add missing args to ISA
Luke Kenneth Casson Leighton [Sun, 7 Jun 2020 11:52:24 +0000 (12:52 +0100)]
remove fixedlogical.patch - added gprs to PowerParser p_atom_name
Luke Kenneth Casson Leighton [Sun, 7 Jun 2020 06:34:09 +0000 (07:34 +0100)]
docstring on caller.py inject() decorator
Luke Kenneth Casson Leighton [Sun, 7 Jun 2020 06:33:47 +0000 (07:33 +0100)]
add TRAP function, stub
Luke Kenneth Casson Leighton [Sun, 7 Jun 2020 06:05:09 +0000 (07:05 +0100)]
update submodule for sprset.mdwn
Luke Kenneth Casson Leighton [Sun, 7 Jun 2020 06:03:58 +0000 (07:03 +0100)]
add MSR to simulator context
Luke Kenneth Casson Leighton [Sun, 7 Jun 2020 00:36:20 +0000 (01:36 +0100)]
move MSR_PR checking to separate functiong
colepoirier [Sun, 7 Jun 2020 00:30:46 +0000 (17:30 -0700)]
Fix missing 'comb +='
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 23:04:30 +0000 (00:04 +0100)]
add python3 env-var if not set in Makefile
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 19:36:07 +0000 (20:36 +0100)]
experimenting with setting up and testing memory
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 18:59:30 +0000 (19:59 +0100)]
expand regwid to 64 in l0_cache test
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 18:46:41 +0000 (19:46 +0100)]
work out how to initialise memory directly
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 18:34:16 +0000 (19:34 +0100)]
initialise L0 Memory from simulator memory
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 18:11:54 +0000 (19:11 +0100)]
wait a little for wr.rel to activate if wrmask is active
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 17:31:02 +0000 (18:31 +0100)]
missing test.mem arg for ISA in test_core
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 17:28:36 +0000 (18:28 +0100)]
allow Mem initialisation in ISACaller
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 17:28:00 +0000 (18:28 +0100)]
shift-mask in Simulator Mem class not quite right
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 17:09:17 +0000 (18:09 +0100)]
write-mask made from LD and Update mode (for data_o and addr_o output)
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 16:13:50 +0000 (17:13 +0100)]
allow Mem in Simulator to be initialised
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 15:36:58 +0000 (16:36 +0100)]
use name of unit to write simulator/vcd file
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 15:33:53 +0000 (16:33 +0100)]
LDSTCompUnit test data structures linked up, starting debugging
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 14:45:14 +0000 (15:45 +0100)]
allow CompLDSTOpSubset to be passed through to LDSTCompUnit
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 14:19:19 +0000 (15:19 +0100)]
set up LDSTCompUnit using regspec
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 14:07:39 +0000 (15:07 +0100)]
add extra bugreport link
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 14:05:42 +0000 (15:05 +0100)]
whitespace
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 14:04:11 +0000 (15:04 +0100)]
whitespace indentation
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 12:40:28 +0000 (13:40 +0100)]
add special-case LDSTFunctionUnit
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 12:40:11 +0000 (13:40 +0100)]
whoops dest%d_o not dest%d_i
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 12:28:02 +0000 (13:28 +0100)]
add beginnings of LDST compunit test
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 05:02:26 +0000 (06:02 +0100)]
whitespace