mesa.git
6 years agointel/fs: shuffle_from_32bit_read at load_per_vertex_input at TCS/TES
Jose Maria Casanova Crespo [Sat, 9 Jun 2018 09:46:07 +0000 (11:46 +0200)]
intel/fs: shuffle_from_32bit_read at load_per_vertex_input at TCS/TES

Previously, the shuffle function had a source/destination overlap that
needs to be avoided to use shuffle_from_32bit_read. As we can use for
the shuffle destination the destination of removed MOVs.

This change also avoids the internal MOVs done by the previous shuffle
to deal with possible overlaps.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agointel/fs: Use shuffle_from_32bit_read at VS load_input
Jose Maria Casanova Crespo [Sat, 9 Jun 2018 09:46:04 +0000 (11:46 +0200)]
intel/fs: Use shuffle_from_32bit_read at VS load_input

shuffle_from_32bit_read manages 32-bit reads to 32-bit destination
in the same way that the previous loop so now we just call the new
function for all bitsizes, simplifying also the 64-bit load_input.

v2: Add comment about future 16-bit support (Jason Ekstrand)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agointel/fs: Use shuffle_from_32bit_read for 64-bit gs_input_load
Jose Maria Casanova Crespo [Sat, 9 Jun 2018 09:46:01 +0000 (11:46 +0200)]
intel/fs: Use shuffle_from_32bit_read for 64-bit gs_input_load

This implementation avoids two unneeded MOVs for each 64-bit
component. One was done in the old shuffle, to avoid cases of
src/dst overlap but this is not the case. And the removed MOV
was already being being done in the shuffle.

Copy propagation wasn't able to remove them because shuffle
destination values are defined with partial writes because they
have stride == 2.

v2: Reword commit log summary (Jason Ekstrand)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agointel/fs: shuffle_from_32bit_read for 64-bit do_untyped_vector_read
Jose Maria Casanova Crespo [Sat, 9 Jun 2018 09:45:57 +0000 (11:45 +0200)]
intel/fs: shuffle_from_32bit_read for 64-bit do_untyped_vector_read

do_untyped_vector_read is used at load_ssbo and load_shared.

The previous MOVs are removed because shuffle_from_32bit_read
can handle storing the shuffle results in the expected destination
just using the proper offset.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agointel/fs: Remove old 16-bit shuffle/unshuffle functions
Jose Maria Casanova Crespo [Sat, 9 Jun 2018 09:45:54 +0000 (11:45 +0200)]
intel/fs: Remove old 16-bit shuffle/unshuffle functions

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agointel/fs: Use shuffle_for_32bit_write for 16-bits store_ssbo
Jose Maria Casanova Crespo [Sat, 9 Jun 2018 09:45:50 +0000 (11:45 +0200)]
intel/fs: Use shuffle_for_32bit_write for 16-bits store_ssbo

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agointel/fs: Use shuffle_from_32bit_read to read 16-bit SSBO
Jose Maria Casanova Crespo [Sat, 9 Jun 2018 09:45:47 +0000 (11:45 +0200)]
intel/fs: Use shuffle_from_32bit_read to read 16-bit SSBO

Using shuffle_from_32bit_read instead of 16-bit shuffle functions
avoids the need of retype. At the same time new function are
ready for 8-bit type SSBO reads.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agointel/fs: Use shuffle_from_32bit_read at VARYING_PULL_CONSTANT_LOAD
Jose Maria Casanova Crespo [Sat, 9 Jun 2018 09:45:42 +0000 (11:45 +0200)]
intel/fs: Use shuffle_from_32bit_read at VARYING_PULL_CONSTANT_LOAD

shuffle_from_32bit_read can manage the shuffle/unshuffle needed
for different 8/16/32/64 bit-sizes at VARYING PULL CONSTANT LOAD.
To get the specific component the first_component parameter is used.

In the case of the previous 16-bit shuffle, the shuffle operation was
generating not needed MOVs where its results where never used. This
behaviour passed unnoticed on SIMD16 because dead_code_eliminate
pass removed the generated instructions but for SIMD8 they cound't be
removed because of being partial writes.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agointel/fs: New shuffle_for_32bit_write and shuffle_from_32bit_read
Jose Maria Casanova Crespo [Sat, 9 Jun 2018 09:45:22 +0000 (11:45 +0200)]
intel/fs: New shuffle_for_32bit_write and shuffle_from_32bit_read

These new shuffle functions deal with the shuffle/unshuffle operations
needed for read/write operations using 32-bit components when the
read/written components have a different bit-size (8, 16, 64-bits).
Shuffle from 32-bit to 32-bit becomes a simple MOV.

shuffle_src_to_dst takes care of doing a shuffle when source type is
smaller than destination type and an unshuffle when source type is
bigger than destination. So this new read/write functions just need
to call shuffle_src_to_dst assuming that writes use a 32-bit
destination and reads use a 32-bit source.

As shuffle_for_32bit_write/from_32bit_read components take components
in unit of source/destination types and shuffle_src_to_dst takes units
of the smallest type component, we adjust components and first_component
parameters.

To enable this new functions it is needed than there is no
source/destination overlap in the case of shuffle_from_32bit_read.
That never happens on shuffle_for_32bit_write as it allocates a new
destination register as it was at shuffle_64bit_data_for_32bit_write.

v2: Reword commit log and add comments to explain why first_component
    and components parameters are adjusted. (Jason Ekstrand)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agointel/fs: general 8/16/32/64-bit shuffle_src_to_dst function
Jose Maria Casanova Crespo [Sat, 9 Jun 2018 09:45:01 +0000 (11:45 +0200)]
intel/fs: general 8/16/32/64-bit shuffle_src_to_dst function

This new function takes care of shuffle/unshuffle components of a
particular bit-size in components with a different bit-size.

If source type size is smaller than destination type size the operation
needed is a component shuffle. The opposite case would be an unshuffle.

Component units are measured in terms of the smaller type between
source and destination. As we are un/shuffling the smaller components
from/into a bigger one.

The operation allows to skip first_component number of components from
the source.

Shuffle MOVs are retyped using integer types avoiding problems with
denorms and float types if source and destination bitsize is different.
This allows to simplify uses of shuffle functions that are dealing with
these retypes individually.

Now there is a new restriction so source and destination can not overlap
anymore when calling this shuffle function. Following patches that migrate
to use this new function will take care individually of avoiding source
and destination overlaps.

v2: (Jason Ekstrand)
    - Rewrite overlap asserts.
    - Manage type_sz(src.type) == type_sz(dst.type) case using MOVs
      from source to dest. This works for 64-bit to 64-bits
      operation that on Gen7 as it doesn't support Q registers.
    - Explain that components units are based in the smallest type.
v3: - Fix unshuffle overlap assert (Jason Ekstrand)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agoappveyor: Consume LLVM 5.0.1.
Jose Fonseca [Sat, 16 Jun 2018 09:02:15 +0000 (10:02 +0100)]
appveyor: Consume LLVM 5.0.1.

https://ci.appveyor.com/project/jrfonseca/mesa/build/47

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
6 years agoac: Clear meminfo to avoid valgrind warning.
Bas Nieuwenhuizen [Thu, 14 Jun 2018 22:01:43 +0000 (00:01 +0200)]
ac: Clear meminfo to avoid valgrind warning.

Somehow valgrind misses that the value is initialized by the ioctl.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
6 years agoradv: fix emitting the TCS regs on GFX9
Samuel Pitoiset [Fri, 15 Jun 2018 15:50:35 +0000 (17:50 +0200)]
radv: fix emitting the TCS regs on GFX9

The primitive ID is NULL and this generates an invalid
select instruction which crashes because one operand is NULL.

This fixes crashes in The Long Journey Home, Quantum Break
and Just Cause 3 with DXVK.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106756
CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
6 years agonir: Document a couple instances of parent_instr
Ian Romanick [Wed, 6 Jun 2018 02:00:42 +0000 (19:00 -0700)]
nir: Document a couple instances of parent_instr

nir_ssa_def::parent_instr and nir_src::parent_instr have the same name,
but they mean really different things.  I choose to save the next person
the hour+ that I just spent figuring that out.  Even now that I know, I
doubt I'd notice in code review that someone typed foo->parent_instr
when they actually meant foo->ssa->parent_instr.

v2: Minor wording tweak in nir_ssa_def::parent_instr.  Suggested by
Jason.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agoi965/fs: Propagate conditional modifiers from not instructions
Ian Romanick [Wed, 13 Jun 2018 17:36:42 +0000 (10:36 -0700)]
i965/fs: Propagate conditional modifiers from not instructions

Skylake
total instructions in shared programs: 14399081 -> 14399010 (<.01%)
instructions in affected programs: 26961 -> 26890 (-0.26%)
helped: 57
HURT: 0
helped stats (abs) min: 1 max: 6 x̄: 1.25 x̃: 1
helped stats (rel) min: 0.16% max: 0.80% x̄: 0.30% x̃: 0.18%
95% mean confidence interval for instructions value: -1.50 -0.99
95% mean confidence interval for instructions %-change: -0.35% -0.25%
Instructions are helped.

total cycles in shared programs: 532978307 -> 532976050 (<.01%)
cycles in affected programs: 468629 -> 466372 (-0.48%)
helped: 33
HURT: 20
helped stats (abs) min: 3 max: 360 x̄: 116.52 x̃: 98
helped stats (rel) min: 0.06% max: 3.63% x̄: 1.66% x̃: 1.27%
HURT stats (abs)   min: 2 max: 172 x̄: 79.40 x̃: 43
HURT stats (rel)   min: 0.04% max: 3.02% x̄: 1.48% x̃: 0.44%
95% mean confidence interval for cycles value: -81.29 -3.88
95% mean confidence interval for cycles %-change: -1.07% 0.12%
Inconclusive result (%-change mean confidence interval includes 0).

All Gen6+ platforms, except Ivy Bridge, had similar results. (Haswell shown)
total instructions in shared programs: 12973897 -> 12973838 (<.01%)
instructions in affected programs: 25970 -> 25911 (-0.23%)
helped: 55
HURT: 0
helped stats (abs) min: 1 max: 2 x̄: 1.07 x̃: 1
helped stats (rel) min: 0.16% max: 0.62% x̄: 0.28% x̃: 0.18%
95% mean confidence interval for instructions value: -1.14 -1.00
95% mean confidence interval for instructions %-change: -0.32% -0.24%
Instructions are helped.

total cycles in shared programs: 410355841 -> 410352067 (<.01%)
cycles in affected programs: 578454 -> 574680 (-0.65%)
helped: 47
HURT: 5
helped stats (abs) min: 3 max: 360 x̄: 85.74 x̃: 18
helped stats (rel) min: 0.05% max: 3.68% x̄: 1.18% x̃: 0.38%
HURT stats (abs)   min: 2 max: 242 x̄: 51.20 x̃: 4
HURT stats (rel)   min: <.01% max: 0.45% x̄: 0.15% x̃: 0.11%
95% mean confidence interval for cycles value: -104.89 -40.27
95% mean confidence interval for cycles %-change: -1.45% -0.66%
Cycles are helped.

Ivy Bridge
total instructions in shared programs: 11679351 -> 11679301 (<.01%)
instructions in affected programs: 28208 -> 28158 (-0.18%)
helped: 50
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.12% max: 0.54% x̄: 0.23% x̃: 0.16%
95% mean confidence interval for instructions value: -1.00 -1.00
95% mean confidence interval for instructions %-change: -0.27% -0.19%
Instructions are helped.

total cycles in shared programs: 257445362 -> 257444662 (<.01%)
cycles in affected programs: 419338 -> 418638 (-0.17%)
helped: 40
HURT: 3
helped stats (abs) min: 1 max: 170 x̄: 65.05 x̃: 24
helped stats (rel) min: 0.02% max: 3.51% x̄: 1.26% x̃: 0.41%
HURT stats (abs)   min: 2 max: 1588 x̄: 634.00 x̃: 312
HURT stats (rel)   min: 0.05% max: 2.97% x̄: 1.21% x̃: 0.62%
95% mean confidence interval for cycles value: -97.96 65.41
95% mean confidence interval for cycles %-change: -1.56% -0.62%
Inconclusive result (value mean confidence interval includes 0).

No changes on Iron Lake or GM45.

v2: Move 'if (cond != BRW_CONDITIONAL_Z && cond != BRW_CONDITIONAL_NZ)'
check outside the loop.  Suggested by Iago.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
6 years agoi965/fs: Rearrange code to remove most of the gotos
Ian Romanick [Wed, 13 Jun 2018 17:11:31 +0000 (10:11 -0700)]
i965/fs: Rearrange code to remove most of the gotos

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
6 years agoi965/fs: Refactor propagation of conditional modifiers from compares to adds
Ian Romanick [Wed, 13 Jun 2018 17:04:55 +0000 (10:04 -0700)]
i965/fs: Refactor propagation of conditional modifiers from compares to adds

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
6 years agoi965/vec4: Optimize OR with 0 into a MOV
Ian Romanick [Wed, 13 Jun 2018 22:07:41 +0000 (15:07 -0700)]
i965/vec4: Optimize OR with 0 into a MOV

All of the affected shaders are geometry shaders... the same ones from
the similar fs changes.

The "No changes on any other platforms" comment below is not quite
right.  Without the previous change to register coalescing, this
optimization caused quite a few regressions in tests that either used
gl_ClipVertex or used different interpolation modes.  I observed that
with both patches applied,
glsl-1.10/execution/interpolation/interpolation-none-gl_BackSecondaryColor-smooth-vertex.shader_test
was one instruction shorter.  I suspect other shaders would be similarly
affected.  Since this is all based on NOS, shader-db does not reflect
it.

Haswell
total instructions in shared programs: 12954955 -> 12954918 (<.01%)
instructions in affected programs: 3603 -> 3566 (-1.03%)
helped: 37
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.21% max: 2.50% x̄: 1.99% x̃: 2.50%
95% mean confidence interval for instructions value: -1.00 -1.00
95% mean confidence interval for instructions %-change: -2.30% -1.69%
Instructions are helped.

total cycles in shared programs: 410012108 -> 410012098 (<.01%)
cycles in affected programs: 3540 -> 3530 (-0.28%)
helped: 5
HURT: 0
helped stats (abs) min: 2 max: 2 x̄: 2.00 x̃: 2
helped stats (rel) min: 0.28% max: 0.28% x̄: 0.28% x̃: 0.28%
95% mean confidence interval for cycles value: -2.00 -2.00
95% mean confidence interval for cycles %-change: -0.28% -0.28%
Cycles are helped.

Ivy Bridge
total instructions in shared programs: 11679387 -> 11679351 (<.01%)
instructions in affected programs: 3292 -> 3256 (-1.09%)
helped: 36
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.21% max: 2.50% x̄: 2.04% x̃: 2.50%
95% mean confidence interval for instructions value: -1.00 -1.00
95% mean confidence interval for instructions %-change: -2.34% -1.74%
Instructions are helped.

No changes on any other platforms.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
6 years agoi965/vec4: Don't register coalesce into source of VS_OPCODE_UNPACK_FLAGS_SIMD4X2
Ian Romanick [Thu, 14 Jun 2018 22:26:58 +0000 (15:26 -0700)]
i965/vec4: Don't register coalesce into source of VS_OPCODE_UNPACK_FLAGS_SIMD4X2

This prevents regressions in a bunch of clipping and interpolation tests
caused by the next patch (i965/vec4: Optimize OR with 0 into a MOV).

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
6 years agoi965/fs: Optimize OR with 0 into a MOV
Ian Romanick [Wed, 13 Jun 2018 19:32:27 +0000 (12:32 -0700)]
i965/fs: Optimize OR with 0 into a MOV

fs_visitor::set_gs_stream_control_data_bits generates some code like
"control_data_bits | stream_id << ((2 * (vertex_count - 1)) % 32)" as
part of EmitVertex.  The first time this (dynamically) occurs in the
shader, control_data_bits is zero.  Many times we can determine this
statically and various optimizations will collaborate to make one of the
OR operands literal zero.

Converting the OR to a MOV usually allows it to be copy-propagated away.
However, this does not happen in at least some shaders (in the assembly
output of shaders/closed/UnrealEngine4/EffectsCaveDemo/301.shader_test,
search for shl).

All of the affected shaders are geometry shaders.

Broadwell and Skylake had similar results. (Skylake shown)
total instructions in shared programs: 14375452 -> 14375413 (<.01%)
instructions in affected programs: 6422 -> 6383 (-0.61%)
helped: 39
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.14% max: 2.56% x̄: 1.91% x̃: 2.56%
95% mean confidence interval for instructions value: -1.00 -1.00
95% mean confidence interval for instructions %-change: -2.26% -1.57%
Instructions are helped.

total cycles in shared programs: 531981179 -> 531980555 (<.01%)
cycles in affected programs: 27493 -> 26869 (-2.27%)
helped: 39
HURT: 0
helped stats (abs) min: 16 max: 16 x̄: 16.00 x̃: 16
helped stats (rel) min: 0.60% max: 7.92% x̄: 5.94% x̃: 7.92%
95% mean confidence interval for cycles value: -16.00 -16.00
95% mean confidence interval for cycles %-change: -6.98% -4.90%
Cycles are helped.

No changes on earlier platforms.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
6 years agov3d: Handle a no-intersection scissor even if it's outside of the VP.
Eric Anholt [Fri, 15 Jun 2018 01:05:50 +0000 (18:05 -0700)]
v3d: Handle a no-intersection scissor even if it's outside of the VP.

The min/maxes ended up producing a negative clip width/height for
dEQP-GLES3.functional.fragment_ops.scissor.outside_render_line.  Just make
sure they stay at 0 (or v3d 3.x's workaround) if that happens.

6 years agov3d: Use the proper depth texture type for sampling.
Eric Anholt [Thu, 14 Jun 2018 18:32:37 +0000 (11:32 -0700)]
v3d: Use the proper depth texture type for sampling.

Fixes failing tests in dEQP-GLES3.functional.texture.shadow

6 years agov3d: Limit shader threading according to our maximum TMU fifo usage.
Eric Anholt [Thu, 14 Jun 2018 18:17:11 +0000 (11:17 -0700)]
v3d: Limit shader threading according to our maximum TMU fifo usage.

Fixes simulator assertion failures in
dEQP-GLES3.functional.shaders.texture_functions.texture.samplercubeshadow_bias_fragment
and similar complicated cases.

6 years agov3d: Fix shaders using pixel center W but no varyings.
Eric Anholt [Thu, 14 Jun 2018 18:04:05 +0000 (11:04 -0700)]
v3d: Fix shaders using pixel center W but no varyings.

The docs called this field "uses both center W and centroid W", but
actually it's "do you need center W even if varyings don't obviously call
for it?"

Fixes dEQP-GLES3.functional.shaders.builtin_variable.fragcoord_w

6 years agodocs: Update release-notes and calendar
Dylan Baker [Fri, 15 Jun 2018 20:53:25 +0000 (13:53 -0700)]
docs: Update release-notes and calendar

6 years agodocs: Add release notes for 18.1.2
Dylan Baker [Fri, 15 Jun 2018 20:45:10 +0000 (13:45 -0700)]
docs: Add release notes for 18.1.2

6 years agointel/aubinator: Use int to store getopt_long flags.
Rafael Antognolli [Tue, 12 Jun 2018 19:18:19 +0000 (12:18 -0700)]
intel/aubinator: Use int to store getopt_long flags.

getopt_long flag parameter is an int pointer, so if we use bool to store
those values, when getopt_long writes to one of them, it might end up
overwriting the next one.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
6 years agoRevert "radv: always set/load both depth and stencil clear values"
Samuel Pitoiset [Fri, 15 Jun 2018 14:50:11 +0000 (16:50 +0200)]
Revert "radv: always set/load both depth and stencil clear values"

This fixes a rendering regression with RoTR.

This reverts commit 4bdad9faddc82a4560603936ce5ade5707ecb254.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
6 years agoradv: don't check for linear images in emit_fast_color_clear()
Samuel Pitoiset [Fri, 15 Jun 2018 13:53:23 +0000 (15:53 +0200)]
radv: don't check for linear images in emit_fast_color_clear()

We don't enable CMASK for linear surfaces and addrlib only
enables DCC for tiling surfaces.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
6 years agoradv: allow RADV_PERFTEST=dccmsaa on GFX9
Samuel Pitoiset [Thu, 14 Jun 2018 09:06:02 +0000 (11:06 +0200)]
radv: allow RADV_PERFTEST=dccmsaa on GFX9

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
6 years agoradv: add RADV_DEBUG=checkir
Samuel Pitoiset [Thu, 14 Jun 2018 12:28:58 +0000 (14:28 +0200)]
radv: add RADV_DEBUG=checkir

This allows to run the LLVM verifier pass.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
6 years agoradv: update ZRANGE_PRECISION in radv_update_bound_fast_clear_ds()
Samuel Pitoiset [Thu, 14 Jun 2018 11:26:23 +0000 (13:26 +0200)]
radv: update ZRANGE_PRECISION in radv_update_bound_fast_clear_ds()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
6 years agoradv: clean up radv_{set,load}_depth_clear_regs() helpers
Samuel Pitoiset [Thu, 14 Jun 2018 11:26:22 +0000 (13:26 +0200)]
radv: clean up radv_{set,load}_depth_clear_regs() helpers

And replace _regs by _metadata because it makes more sense.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
6 years agoradv: always set/load both depth and stencil clear values
Samuel Pitoiset [Thu, 14 Jun 2018 11:26:21 +0000 (13:26 +0200)]
radv: always set/load both depth and stencil clear values

I don't think that matter much to emit both values and that
makes the code a bit simpler.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
6 years agoradv: update the fast ds clear values only if the image is bound
Samuel Pitoiset [Thu, 14 Jun 2018 11:26:20 +0000 (13:26 +0200)]
radv: update the fast ds clear values only if the image is bound

It's unnecessary to update the fast depth/stencil clear values
if the fast cleared depth/stencil image isn't currently bound.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
6 years agoradv: clean up radv_{set,load}_color_clear_regs() helpers
Samuel Pitoiset [Thu, 14 Jun 2018 11:26:19 +0000 (13:26 +0200)]
radv: clean up radv_{set,load}_color_clear_regs() helpers

And replace _regs by _metadata because it makes more sense.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
6 years agoradv: update the fast color clear values only if the image is bound
Samuel Pitoiset [Thu, 14 Jun 2018 11:26:18 +0000 (13:26 +0200)]
radv: update the fast color clear values only if the image is bound

It's unnecessary to update the fast color clear values if the
fast cleared color image isn't currently bound.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
6 years agoutil/bitset: include util/macro.h
Christian Gmeiner [Fri, 15 Jun 2018 10:18:56 +0000 (12:18 +0200)]
util/bitset: include util/macro.h

BITSET_FFS(x) macro makes use of ARRAY_SIZE(x) macro which is
defined in util/macro.h. Include it directy to make usage more
straightforward.

Fixes: 692bd4a1ab9 ("util: replace Elements() with ARRAY_SIZE()")
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
6 years agomeson: fix private libs when building without glx
Lukas Rusak [Mon, 4 Jun 2018 19:38:41 +0000 (12:38 -0700)]
meson: fix private libs when building without glx

I noticed that the generated pkg-config files will include
glx and x11 dependencies even when x11 isn't a selected platform.

This fixes the private libs and was tested by building kmscube

V2:
  - check if gallium-xlib is being used for glx

Fixes: 108d257a16859898f5ce0 "meson: build libEGL"
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
6 years agodocs: document addition of GL_ARB_sample_locations for nvc0
Rhys Perry [Fri, 15 Jun 2018 01:56:28 +0000 (19:56 -0600)]
docs: document addition of GL_ARB_sample_locations for nvc0

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com> (v2)
6 years agonvc0: add support for programmable sample locations
Rhys Perry [Fri, 15 Jun 2018 01:56:28 +0000 (19:56 -0600)]
nvc0: add support for programmable sample locations

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
6 years agost/mesa: add support for ARB_sample_locations
Rhys Perry [Fri, 15 Jun 2018 01:56:28 +0000 (19:56 -0600)]
st/mesa: add support for ARB_sample_locations

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com> (v2)
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v2)
6 years agogallium: add support for programmable sample locations
Rhys Perry [Fri, 15 Jun 2018 01:56:28 +0000 (19:56 -0600)]
gallium: add support for programmable sample locations

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com> (v2)
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v2)
6 years agomesa: add support for ARB_sample_locations
Rhys Perry [Fri, 15 Jun 2018 01:56:28 +0000 (19:56 -0600)]
mesa: add support for ARB_sample_locations

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com> (v2)
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v2)
6 years agov3d: Fix polygon offset for Z16 buffers.
Eric Anholt [Wed, 13 Jun 2018 20:44:01 +0000 (13:44 -0700)]
v3d: Fix polygon offset for Z16 buffers.

Fixes:
dEQP-GLES3.functional.polygon_offset.fixed16_displacement_with_units
dEQP-GLES3.functional.polygon_offset.fixed16_render_with_units

6 years agov3d: Fix configuration setup of mixed f32 and f16 render targets.
Eric Anholt [Wed, 13 Jun 2018 20:38:33 +0000 (13:38 -0700)]
v3d: Fix configuration setup of mixed f32 and f16 render targets.

Fixes dEQP-GLES3.functional.fragment_out.random.26 and 6 others.

6 years agov3d: Don't set the first_ez_state to DISABLED if after only UNDECIDED draws.
Eric Anholt [Wed, 13 Jun 2018 19:58:22 +0000 (12:58 -0700)]
v3d: Don't set the first_ez_state to DISABLED if after only UNDECIDED draws.

We need to have the RCL start with EZ enabled, since those undecided draws
had EZ enabled.  But we do need to update from UNDECIDED to LT or GT as
necessary still.

Fixes many simulator assertion fails in deqp
fragment_ops/interaction/basic_shader/*

6 years agov3d: Use the right size for v3d 4.x TEXTURE_SHADER_STATE BO.
Eric Anholt [Fri, 8 Jun 2018 15:35:50 +0000 (08:35 -0700)]
v3d: Use the right size for v3d 4.x TEXTURE_SHADER_STATE BO.

This doesn't really matter, since they both get rounded up to 4096.

6 years agov3d: Add static asserts for other packed packet sizes.
Eric Anholt [Fri, 8 Jun 2018 15:31:58 +0000 (08:31 -0700)]
v3d: Add static asserts for other packed packet sizes.

6 years agov3d: Fix the size of the packed attribute state.
Eric Anholt [Fri, 8 Jun 2018 15:31:30 +0000 (08:31 -0700)]
v3d: Fix the size of the packed attribute state.

Fixes segfaults in dEQP-GLES3.functional.vertex_array_objects.all_attributes.

6 years agov3d: Remove some unused context fields from vc4.
Eric Anholt [Fri, 8 Jun 2018 15:04:00 +0000 (08:04 -0700)]
v3d: Remove some unused context fields from vc4.

6 years agov3d: Remove unused QUNIFORM_STENCIL left over from vc4.
Eric Anholt [Fri, 8 Jun 2018 15:32:34 +0000 (08:32 -0700)]
v3d: Remove unused QUNIFORM_STENCIL left over from vc4.

6 years agov3d: Use our #define for max attributes in shader caps.
Eric Anholt [Fri, 8 Jun 2018 15:00:31 +0000 (08:00 -0700)]
v3d: Use our #define for max attributes in shader caps.

6 years agov3d: Fix undefined results for a swap_color_rb RT from a float shader output.
Eric Anholt [Thu, 7 Jun 2018 04:06:44 +0000 (21:06 -0700)]
v3d: Fix undefined results for a swap_color_rb RT from a float shader output.

Fixes segfaults and undefined behavior in
dEQP-GLES3.functional.fragment_out.basic.fixed.srgb8_alpha8_lowp_float

6 years agoradv: remove multisample bit from shader key.
Dave Airlie [Thu, 14 Jun 2018 22:48:54 +0000 (08:48 +1000)]
radv: remove multisample bit from shader key.

This wasn't being used anywhere inside the shader from what I can see.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
6 years agointel/compiler: Properly consider UBO loads that cross 32B boundaries.
Kenneth Graunke [Fri, 8 Jun 2018 21:24:16 +0000 (14:24 -0700)]
intel/compiler: Properly consider UBO loads that cross 32B boundaries.

The UBO push analysis pass incorrectly assumed that all values would fit
within a 32B chunk, and only recorded a bit for the 32B chunk containing
the starting offset.

For example, if a UBO contained the following, tightly packed:

   vec4 a;  // [0, 16)
   float b; // [16, 20)
   vec4 c;  // [20, 36)

then, c would start at offset 20 / 32 = 0 and end at 36 / 32 = 1,
which means that we ought to record two 32B chunks in the bitfield.

Similarly, dvec4s would suffer from the same problem.

v2: Rewrite the accounting, my calculations were wrong.
v3: Write a comment about partial values (requested by Jason).

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com> [v1]
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> [v3]
6 years agoglsl: Don't copy propagate elements from SSBO or shared variables either
Ian Romanick [Tue, 5 Jun 2018 23:02:25 +0000 (16:02 -0700)]
glsl: Don't copy propagate elements from SSBO or shared variables either

Since SSBOs can be written by a different GPU thread, copy propagating a
read can cause the value to magically change.  SSBO reads are also very
expensive, so doing it twice will be slower.

The same shader was helped by this patch and the previous.

Haswell, Broadwell, and Skylake had similar results. (Skylake shown)
total instructions in shared programs: 14399119 -> 14399113 (<.01%)
instructions in affected programs: 683 -> 677 (-0.88%)
helped: 1
HURT: 0

total cycles in shared programs: 532973113 -> 532971865 (<.01%)
cycles in affected programs: 524666 -> 523418 (-0.24%)
helped: 1
HURT: 0

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106774

6 years agoglsl: Don't copy propagate from SSBO or shared variables either
Ian Romanick [Tue, 5 Jun 2018 22:04:24 +0000 (15:04 -0700)]
glsl: Don't copy propagate from SSBO or shared variables either

Since SSBOs can be written by other GPU threads, copy propagating a read
can cause the value to magically change.  SSBO reads are also very
expensive, so doing it twice will be slower.

Haswell, Broadwell, and Skylake had similar results. (Skylake shown)
total instructions in shared programs: 14399120 -> 14399119 (<.01%)
instructions in affected programs: 684 -> 683 (-0.15%)
helped: 1
HURT: 0

total cycles in shared programs: 532978931 -> 532973113 (<.01%)
cycles in affected programs: 530484 -> 524666 (-1.10%)
helped: 1
HURT: 0

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106774

6 years agomeson: only build vl_winsys_dri.c when x11 platform is used
Lukas Rusak [Fri, 1 Jun 2018 21:09:42 +0000 (14:09 -0700)]
meson: only build vl_winsys_dri.c when x11 platform is used

This seems to have been missed in the move from autotools

This fixes the following build issue:

../src/gallium/auxiliary/vl/vl_winsys_dri.c:34:10: fatal error: X11/Xlib-xcb.h: No such file or directory
 #include <X11/Xlib-xcb.h>
          ^~~~~~~~~~~~~~~~

Fixes: b1b65397d0c4978e36a84c0a1c98a4bd6cb9588e
       ("meson: Build gallium auxiliary")
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
6 years agost/mesa: add missing switch cases in glsl_to_tgsi_visitor::visit()
Brian Paul [Thu, 14 Jun 2018 15:12:19 +0000 (09:12 -0600)]
st/mesa: add missing switch cases in glsl_to_tgsi_visitor::visit()

To silence compiler warning about unhandled switch cases.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
6 years agoradv: Fix output for sparse MRTs.
Bas Nieuwenhuizen [Wed, 13 Jun 2018 21:31:54 +0000 (23:31 +0200)]
radv: Fix output for sparse MRTs.

We need to init the cb_shader_format correctly with the changed
col_format, so this moves the col_format adjustment to before the
adjustment to before the cb_shader_mask gets generated.

Fixes: 06d3c650980 "radv: fix a GPU hang when MRTs are sparse"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106903
CC: 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
6 years agoradv: update the ZRANGE_PRECISION value for the TC-compat bug
Samuel Pitoiset [Wed, 13 Jun 2018 12:27:40 +0000 (14:27 +0200)]
radv: update the ZRANGE_PRECISION value for the TC-compat bug

On GFX8+, there is a bug that affects TC-compatible depth surfaces
when the ZRange is not reset after LateZ kills pixels.

The workaround is to always set DB_Z_INFO.ZRANGE_PRECISION to match
the last fast clear value. Because the value is set to 1 by default,
we only need to update it when clearing Z to 0.0.

We also need to set the depth clear regs and to update
ZRANGE_PRECISION when initializing a TC-compat depth image to 0.

Original patch from James Legg.

This fixes random CTS fails with
dEQP-VK.renderpass.suballocation.formats.d32_sfloat_s8_uint.input.*

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105396
CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
6 years agoanv: reduce maxFragmentInputComponents
Samuel Iglesias Gonsálvez [Mon, 28 May 2018 09:42:15 +0000 (11:42 +0200)]
anv: reduce maxFragmentInputComponents

If the application asks for the maximum number of fragment input
components (128), use all of them plus some builtins that are
passed in the VUE, then we exceed the maximum number of used VUE
slots (32) and we break one assert that checks this limit.

Also, with separate shader objects, we add CLIP_DIST0, CLIP_DIST1
builtins in brw_compute_vue_map() because we don't know if
gl_ClipDistance is going to be read/write by an adjacent stage.

Fixes VK-GL-CTS CL#2569.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agoradeonsi/gfx9: fix si_get_buffer_from_descriptors for 48-bit pointers
Marek Olšák [Fri, 1 Jun 2018 23:29:45 +0000 (19:29 -0400)]
radeonsi/gfx9: fix si_get_buffer_from_descriptors for 48-bit pointers

This fixes:
GL45-CTS.pipeline_statistics_query_tests_ARB.functional_compute_shader_invocations

Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
6 years agoradeonsi/gfx9: update & clean up a DPBB heuristic
Marek Olšák [Fri, 1 Jun 2018 04:33:57 +0000 (00:33 -0400)]
radeonsi/gfx9: update & clean up a DPBB heuristic

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
6 years agoradeonsi/gfx9: set POPS_DRAIN_PS_ON_OVERLAP due to a hw bug
Marek Olšák [Fri, 1 Jun 2018 04:21:49 +0000 (00:21 -0400)]
radeonsi/gfx9: set POPS_DRAIN_PS_ON_OVERLAP due to a hw bug

This may not be needed yet, but let's set it now.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
6 years agoradeonsi/gfx9: remove UINT_MAX array terminators in bin size tables
Marek Olšák [Fri, 1 Jun 2018 04:06:35 +0000 (00:06 -0400)]
radeonsi/gfx9: remove UINT_MAX array terminators in bin size tables

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
6 years agoradeonsi/gfx9: update bin sizes
Marek Olšák [Fri, 1 Jun 2018 03:48:03 +0000 (23:48 -0400)]
radeonsi/gfx9: update bin sizes

This is based on our docs (recently updated), not amdvlk.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
6 years agoradeonsi/gfx9: update primitive binning code for EQAA
Marek Olšák [Fri, 1 Jun 2018 03:47:17 +0000 (23:47 -0400)]
radeonsi/gfx9: update primitive binning code for EQAA

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
6 years agoradeonsi: assume that rasterizer state is non-NULL in draw_vbo
Marek Olšák [Thu, 31 May 2018 03:21:28 +0000 (23:21 -0400)]
radeonsi: assume that rasterizer state is non-NULL in draw_vbo

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
6 years agoradeonsi: micro-optimize prim checking and fix guardband with lines+adjacency
Marek Olšák [Thu, 31 May 2018 02:59:41 +0000 (22:59 -0400)]
radeonsi: micro-optimize prim checking and fix guardband with lines+adjacency

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
6 years agoradeonsi: move the guardband registers into a separate state atom
Marek Olšák [Thu, 31 May 2018 02:38:05 +0000 (22:38 -0400)]
radeonsi: move the guardband registers into a separate state atom

They have a different frequency of updates and don't change when scissors
change.

I think this even fixes something in si_update_vs_viewport_state.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
6 years agoradeonsi/gfx9: implement the scissor bug workaround without performance drop
Marek Olšák [Thu, 31 May 2018 02:02:00 +0000 (22:02 -0400)]
radeonsi/gfx9: implement the scissor bug workaround without performance drop

This might improve performance on Vega10 and Raven.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
6 years agoradeonsi: don't set VGT_LS_HS_CONFIG if it doesn't change
Marek Olšák [Thu, 31 May 2018 01:24:06 +0000 (21:24 -0400)]
radeonsi: don't set VGT_LS_HS_CONFIG if it doesn't change

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
6 years agoradeonsi: move VGT_GS_OUT_PRIM_TYPE into si_shader_gs
Marek Olšák [Thu, 31 May 2018 01:16:14 +0000 (21:16 -0400)]
radeonsi: move VGT_GS_OUT_PRIM_TYPE into si_shader_gs

same as amdvlk.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
6 years agoradeonsi: record CLIPVERTEX output usage properly for compatibility profiles
Marek Olšák [Fri, 25 May 2018 21:37:51 +0000 (17:37 -0400)]
radeonsi: record CLIPVERTEX output usage properly for compatibility profiles

This was missed when adding CLIPVERTEX support into GS & tess.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
6 years agoradeonsi: fix FBFETCH with 2D MSAA arrays
Marek Olšák [Fri, 18 May 2018 03:26:56 +0000 (23:26 -0400)]
radeonsi: fix FBFETCH with 2D MSAA arrays

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
6 years agoac: handle undefined EQAA samples in ac_apply_fmask_to_sample
Marek Olšák [Fri, 18 May 2018 03:23:24 +0000 (23:23 -0400)]
ac: handle undefined EQAA samples in ac_apply_fmask_to_sample

RADV might wanna use this helper too.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
6 years agoradeonsi: return real memory usage instead of per-process usage
Marek Olšák [Wed, 13 Jun 2018 01:13:44 +0000 (21:13 -0400)]
radeonsi: return real memory usage instead of per-process usage

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
6 years agoac/gpu_info: report real total memory sizes
Marek Olšák [Wed, 13 Jun 2018 00:59:42 +0000 (20:59 -0400)]
ac/gpu_info: report real total memory sizes

The change from MIN2 to MAX2 is intentional.

Cc: 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
6 years agodocs: mark virgl GL 4.0 features as complete.
Dave Airlie [Thu, 14 Jun 2018 00:37:28 +0000 (10:37 +1000)]
docs: mark virgl GL 4.0 features as complete.

virgl should now expose GL4.1 where it can.

6 years agovirgl: add ARB_tessellation_shader support. (v2)
Dave Airlie [Fri, 8 Jun 2018 04:38:14 +0000 (14:38 +1000)]
virgl: add ARB_tessellation_shader support. (v2)

This should add all the pieces to enable tess shaders on virgl.

v2: fixup transform to handle tess and strip out precise.
set default for max patch varyings to work around issue when
tess gets enabled from v1 caps but v2 caps aren't in place. (Elie)

Reviewed-by: Elie Tournier <elie.tournier@collabora.com>
6 years agoglsl: allow standalone semicolons outside main()
Dave Airlie [Wed, 13 Jun 2018 23:52:21 +0000 (09:52 +1000)]
glsl: allow standalone semicolons outside main()

GLSL 4.60 offically added this but games and older CTS suites actually
had shaders that did this, we may as well enable it everywhere.

Adding stable because it appears apps in the wild do this.

Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: <mesa-stable@lists.freedesktop.org>
6 years agoradv: don't fast clear HTILE for 16-bit depth surfaces on GFX8
Samuel Pitoiset [Wed, 13 Jun 2018 18:19:23 +0000 (20:19 +0200)]
radv: don't fast clear HTILE for 16-bit depth surfaces on GFX8

This causes rendering issues in Shadow Warrior 2 with DXVK.

Cc: mesa-stable@lists.freedesktop.org
Fixes: ccc64f3133 ("radv: enable TC-compat HTILE for 16-bit depth surfaces on GFX8")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106912
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
6 years agoconfigure.ac: Test for __atomic_add_fetch in atomic checks
Andrew Galante [Mon, 11 Jun 2018 22:05:25 +0000 (15:05 -0700)]
configure.ac: Test for __atomic_add_fetch in atomic checks

Some platforms have 64-bit __atomic_load_n but not 64-bit
__atomic_add_fetch, so test for both of them.

Bug: https://bugs.gentoo.org/655616
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
6 years agomeson: Test for __atomic_add_fetch in atomic checks
Andrew Galante [Mon, 11 Jun 2018 22:03:36 +0000 (15:03 -0700)]
meson: Test for __atomic_add_fetch in atomic checks

Some platforms have 64-bit __atomic_load_n but not 64-bit
__atomic_add_fetch, so test for both of them.

Bug: https://bugs.gentoo.org/655616
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
6 years agomeson: Fix -latomic check
Matt Turner [Mon, 11 Jun 2018 21:56:26 +0000 (14:56 -0700)]
meson: Fix -latomic check

Commit 54ba73ef102f (configure.ac/meson.build: Fix -latomic test) fixed
some checks for -latomic, and then commit 54bbe600ec26 (configure.ac:
rework -latomic check) further extended the fixes in configure.ac but
not in Meson. This commit extends those fixes to the Meson tests.

Fixes: 54bbe600ec26 (configure.ac: rework -latomic check)
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
6 years agomeson: Remove various completed todos
Dylan Baker [Tue, 12 Jun 2018 16:03:28 +0000 (09:03 -0700)]
meson: Remove various completed todos

v3: - Remove "won't do" todos, so only completed todo's are now removed.

Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com> (v2)
6 years agomeson: Make use of optional modules
Dylan Baker [Thu, 7 Jun 2018 18:22:48 +0000 (11:22 -0700)]
meson: Make use of optional modules

meson 0.43 gained support for optional modules, which clover wold like
to use. Since we require 0.44.1 now we can rely on them being available
for clover.

compile tested only.

Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
6 years agomeson: Add support for ppc assembly/optimizations
Dylan Baker [Thu, 7 Jun 2018 18:13:34 +0000 (11:13 -0700)]
meson: Add support for ppc assembly/optimizations

v2: - Use -mpower8-vector in compiler test for altivec
    - rename altivec option to power8
    - reword power8 option description to be more clear, originally I
      had made it a boolean, but replaced it with an auto option.

Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
6 years agomeson: Add support for SPARC assembly
Dylan Baker [Thu, 7 Jun 2018 17:58:06 +0000 (10:58 -0700)]
meson: Add support for SPARC assembly

This was blindly copied from autotools and tested by a helpful gentoo
user.

Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
6 years agomeson: Set include dirs for asm
Dylan Baker [Mon, 11 Jun 2018 17:12:46 +0000 (10:12 -0700)]
meson: Set include dirs for asm

v2: - split this from the next patch
    - Only include x86-64 and not x86 when buiding x86_64

Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
6 years agomeson: move cc and cpp definitions to top of main meson.build
Dylan Baker [Mon, 11 Jun 2018 17:15:15 +0000 (10:15 -0700)]
meson: move cc and cpp definitions to top of main meson.build

This just makes using cc and cpp easier.

v2: - Add this patch to fix altivec

Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
6 years agoRevert "intel/compiler: Properly consider UBO loads that cross 32B boundaries."
Jason Ekstrand [Wed, 13 Jun 2018 16:23:28 +0000 (09:23 -0700)]
Revert "intel/compiler: Properly consider UBO loads that cross 32B boundaries."

This reverts commit b8fa847c2ed9c7c743f31e57560a09fae3992f46.

This broke about 30k Vulkan CTS tests.

6 years agointel/compiler: Properly consider UBO loads that cross 32B boundaries.
Kenneth Graunke [Fri, 8 Jun 2018 21:24:16 +0000 (14:24 -0700)]
intel/compiler: Properly consider UBO loads that cross 32B boundaries.

The UBO push analysis pass incorrectly assumed that all values would fit
within a 32B chunk, and only recorded a bit for the 32B chunk containing
the starting offset.

For example, if a UBO contained the following, tightly packed:

   vec4 a;  // [0, 16)
   float b; // [16, 20)
   vec4 c;  // [20, 36)

then, c would start at offset 20 / 32 = 0 and end at 36 / 32 = 1,
which means that we ought to record two 32B chunks in the bitfield.

Similarly, dvec4s would suffer from the same problem.

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
6 years agodrivers/dri/i965: add missing #include
Ross Burton [Tue, 12 Jun 2018 10:59:01 +0000 (11:59 +0100)]
drivers/dri/i965: add missing #include

brw_bufmgr.h uses time_t without include time.h, so the build fails under musl.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
6 years agoanv/android: Use an address for each anv_image plane
Mauro Rossi [Sun, 3 Jun 2018 18:41:59 +0000 (20:41 +0200)]
anv/android: Use an address for each anv_image plane

Fixes to avoid building error after change in image->planes[] structure,
{bo,bo_offset} has to be replaced by address.{bo,offset}
and update is needed also in the assert() for debug builds.

external/mesa/src/intel/vulkan/anv_android.c:188:21:
error: no member named 'bo' in 'struct anv_image::(anonymous at external/mesa/src/intel/vulkan/anv_private.h:2647:4)'
   image->planes[0].bo = bo;
   ~~~~~~~~~~~~~~~~ ^
1 error generated.

Fixes: bf34ef16ac ("anv: Use an address for each anv_image plane")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agoanv/android: Set the BO flags in bo_cache_import (v2)
Mauro Rossi [Mon, 4 Jun 2018 00:48:09 +0000 (02:48 +0200)]
anv/android: Set the BO flags in bo_cache_import (v2)

Changes to avoid building error:

external/mesa/src/intel/vulkan/anv_android.c:131:72:
error: too few arguments to function call, expected 5, have 4
   result = anv_bo_cache_import(device, &device->bo_cache, dma_buf, &bo);
            ~~~~~~~~~~~~~~~~~~~                                        ^
1 error generated.

(v2) Set the correct bo_flags based on support of 48bit addresses and soft-pin

Fixes: b0d50247a7 ("anv/allocator: Set the BO flags in bo_cache_alloc/import")
Fixes: e7d0378bd9 ("anv: Soft-pin client-allocated memory")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agoanv: Disable __gen_validate_value if NDEBUG is set.
Kenneth Graunke [Thu, 7 Jun 2018 22:44:43 +0000 (15:44 -0700)]
anv: Disable __gen_validate_value if NDEBUG is set.

We were enabling undefined memory checking for genxml values based on
Valgrind being installed at build time, even for release builds.  This
generates piles and piles of assembly whenever you touch genxml.

With gcc 7.3.1 and -O3 and -march=native on a Kabylake with Valgrind
installed at build time:

      text    data    bss     dec    hex filename
   5978385  262884  13488 6254757 5f70a5 libvulkan_intel.so
   3799377  262884  13488 4075749 3e30e5 libvulkan_intel.so

That's a 36% reduction in text size.

Fixes: 047ed02723071d7eccbed3210b5be6ae73603a53 (vk/emit: Use valgrind to validate every packed field)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agoREADME: wording fix for previous commit
Eric Engestrom [Mon, 11 Jun 2018 17:34:42 +0000 (18:34 +0100)]
README: wording fix for previous commit

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>