soc.git
5 years agoinclude hazard line to swap rd/wr dependencies
Luke Kenneth Casson Leighton [Mon, 20 May 2019 07:49:48 +0000 (08:49 +0100)]
include hazard line to swap rd/wr dependencies

5 years agonon-overlapping instructions ok
Luke Kenneth Casson Leighton [Sun, 19 May 2019 16:43:05 +0000 (17:43 +0100)]
non-overlapping instructions ok

5 years agosync ok on simple add
Luke Kenneth Casson Leighton [Sun, 19 May 2019 15:34:50 +0000 (16:34 +0100)]
sync ok on simple add

5 years agoadd reg clearing and read-request release
Luke Kenneth Casson Leighton [Sun, 19 May 2019 15:11:51 +0000 (16:11 +0100)]
add reg clearing and read-request release

5 years agouse register-based DepCell
Luke Kenneth Casson Leighton [Sun, 19 May 2019 09:34:02 +0000 (10:34 +0100)]
use register-based DepCell

5 years agocreating separate dependency cell which can be used for all 3 src1/src2/dest
Luke Kenneth Casson Leighton [Sun, 19 May 2019 08:19:40 +0000 (09:19 +0100)]
creating separate dependency cell which can be used for all 3 src1/src2/dest

5 years agoexperiment switching over fwd and rsel in dependency cell
Luke Kenneth Casson Leighton [Sun, 19 May 2019 06:15:39 +0000 (07:15 +0100)]
experiment switching over fwd and rsel in dependency cell

5 years agoadd individual dependency cell (sync mode)
Luke Kenneth Casson Leighton [Sun, 19 May 2019 06:15:12 +0000 (07:15 +0100)]
add individual dependency cell (sync mode)

5 years agoscoreboard 6600 experimentation
Luke Kenneth Casson Leighton [Sun, 19 May 2019 06:14:31 +0000 (07:14 +0100)]
scoreboard 6600 experimentation

5 years agowhoops bug where rsel lists were being re-initialised to empty
Luke Kenneth Casson Leighton [Sat, 18 May 2019 14:53:57 +0000 (15:53 +0100)]
whoops bug where rsel lists were being re-initialised to empty

5 years agoreduce length of vectors (per-row only single bit)
Luke Kenneth Casson Leighton [Sat, 18 May 2019 11:38:56 +0000 (12:38 +0100)]
reduce length of vectors (per-row only single bit)

5 years agoconnect up vectors direct
Luke Kenneth Casson Leighton [Sat, 18 May 2019 09:12:23 +0000 (10:12 +0100)]
connect up vectors direct

5 years agoconnect dependency row outputs
Luke Kenneth Casson Leighton [Sat, 18 May 2019 09:03:46 +0000 (10:03 +0100)]
connect dependency row outputs

5 years agocompress dependency matrix outputs into a row
Luke Kenneth Casson Leighton [Sat, 18 May 2019 08:53:10 +0000 (09:53 +0100)]
compress dependency matrix outputs into a row

5 years agomove dependency cells to row class
Luke Kenneth Casson Leighton [Sat, 18 May 2019 08:43:27 +0000 (09:43 +0100)]
move dependency cells to row class

5 years agoRevert "whoops use global vector correctly"
Luke Kenneth Casson Leighton [Sat, 18 May 2019 08:19:54 +0000 (09:19 +0100)]
Revert "whoops use global vector correctly"

This reverts commit d6723d9007b9fb5b9f56290e26af3e6bfa4f69f1.

5 years agowhoops use global vector correctly
Luke Kenneth Casson Leighton [Sat, 18 May 2019 08:18:03 +0000 (09:18 +0100)]
whoops use global vector correctly

5 years agowhoops use global vector correctly
Luke Kenneth Casson Leighton [Sat, 18 May 2019 07:47:29 +0000 (08:47 +0100)]
whoops use global vector correctly

5 years agoreduce syncs, get FU-FU and FU on same clock cycle
Luke Kenneth Casson Leighton [Sat, 18 May 2019 07:00:03 +0000 (08:00 +0100)]
reduce syncs, get FU-FU and FU on same clock cycle

5 years agonow using readable/writable from fu-fu matrix, seems to be working
Luke Kenneth Casson Leighton [Sat, 18 May 2019 06:50:36 +0000 (07:50 +0100)]
now using readable/writable from fu-fu matrix, seems to be working

5 years agouse FU-FU matrix, seems to be working, still have to resolve dependencies
Luke Kenneth Casson Leighton [Sat, 18 May 2019 05:29:08 +0000 (06:29 +0100)]
use FU-FU matrix, seems to be working, still have to resolve dependencies

5 years agouse FU-FU matrix, seems to be working, still have to resolve dependencies
Luke Kenneth Casson Leighton [Sat, 18 May 2019 05:29:01 +0000 (06:29 +0100)]
use FU-FU matrix, seems to be working, still have to resolve dependencies

5 years agoreorg instr test issue
Luke Kenneth Casson Leighton [Thu, 16 May 2019 15:41:53 +0000 (16:41 +0100)]
reorg instr test issue

5 years agoadd back in rd-flag qualification into fn unit
Luke Kenneth Casson Leighton [Thu, 16 May 2019 11:34:31 +0000 (12:34 +0100)]
add back in rd-flag qualification into fn unit

5 years agobring in go_rd_i into 6600 scoreboard, on 1-clock delay
Luke Kenneth Casson Leighton [Thu, 16 May 2019 11:07:43 +0000 (12:07 +0100)]
bring in go_rd_i into 6600 scoreboard, on 1-clock delay

5 years agoand in go_rd_i into group picker read
Luke Kenneth Casson Leighton [Thu, 16 May 2019 11:07:02 +0000 (12:07 +0100)]
and in go_rd_i into group picker read

5 years agoremove & rd_l.q, is now in group picker
Luke Kenneth Casson Leighton [Thu, 16 May 2019 11:06:45 +0000 (12:06 +0100)]
remove & rd_l.q, is now in group picker

5 years agoadd in go_rd
Luke Kenneth Casson Leighton [Thu, 16 May 2019 11:02:36 +0000 (12:02 +0100)]
add in go_rd

5 years agoexperiment lock out of registers in read vector
Luke Kenneth Casson Leighton [Thu, 16 May 2019 06:58:48 +0000 (07:58 +0100)]
experiment lock out of registers in read vector

5 years agosync function unit src/dest
Luke Kenneth Casson Leighton [Thu, 16 May 2019 04:22:07 +0000 (05:22 +0100)]
sync function unit src/dest

5 years agogetting there with instruction overlapping
Luke Kenneth Casson Leighton [Thu, 16 May 2019 04:02:23 +0000 (05:02 +0100)]
getting there with instruction overlapping

5 years agotry random inputs
Luke Kenneth Casson Leighton [Wed, 15 May 2019 17:13:01 +0000 (18:13 +0100)]
try random inputs

5 years agowrite-after-read hazard working
Luke Kenneth Casson Leighton [Wed, 15 May 2019 15:23:43 +0000 (16:23 +0100)]
write-after-read hazard working

5 years agomake global pending sync-delayed
Luke Kenneth Casson Leighton [Wed, 15 May 2019 15:11:46 +0000 (16:11 +0100)]
make global pending sync-delayed

5 years agomake fn unit invert readable, however qualify with rd latch
Luke Kenneth Casson Leighton [Wed, 15 May 2019 15:06:47 +0000 (16:06 +0100)]
make fn unit invert readable, however qualify with rd latch

5 years agoincrease counter, experiment with longer completion times
Luke Kenneth Casson Leighton [Wed, 15 May 2019 07:29:00 +0000 (08:29 +0100)]
increase counter, experiment with longer completion times

5 years agovery weird: invert readable vector, cscore works
Luke Kenneth Casson Leighton [Wed, 15 May 2019 06:48:51 +0000 (07:48 +0100)]
very weird: invert readable vector, cscore works

5 years agoexperimenting with cscore, overlapping instructions
Luke Kenneth Casson Leighton [Tue, 14 May 2019 09:35:41 +0000 (10:35 +0100)]
experimenting with cscore, overlapping instructions

5 years agoinverted global write pend vector, on creation of readable signal,
Luke Kenneth Casson Leighton [Tue, 14 May 2019 09:02:54 +0000 (10:02 +0100)]
inverted global write pend vector, on creation of readable signal,
seems to work

5 years agoexperimenting with score6600
Luke Kenneth Casson Leighton [Tue, 14 May 2019 09:02:18 +0000 (10:02 +0100)]
experimenting with score6600

5 years agoexperimenting with cscore
Luke Kenneth Casson Leighton [Tue, 14 May 2019 04:37:09 +0000 (05:37 +0100)]
experimenting with cscore

5 years agolatch Function Unit registers based on "issue" signal
Luke Kenneth Casson Leighton [Tue, 14 May 2019 04:27:09 +0000 (05:27 +0100)]
latch Function Unit registers based on "issue" signal

5 years agocomb on intpick
Luke Kenneth Casson Leighton [Mon, 13 May 2019 22:24:07 +0000 (23:24 +0100)]
comb on intpick

5 years agoscore6600 working without FunctionUnit (using dep matrices)
Luke Kenneth Casson Leighton [Mon, 13 May 2019 22:08:16 +0000 (23:08 +0100)]
score6600 working without FunctionUnit (using dep matrices)

5 years agosync on req_rel
Luke Kenneth Casson Leighton [Mon, 13 May 2019 21:07:54 +0000 (22:07 +0100)]
sync on req_rel

5 years agoreturn to latch on src for oper
Luke Kenneth Casson Leighton [Mon, 13 May 2019 21:07:38 +0000 (22:07 +0100)]
return to latch on src for oper

5 years agorename intermediate signals to wr_wait/rd_wait
Luke Kenneth Casson Leighton [Mon, 13 May 2019 19:03:23 +0000 (20:03 +0100)]
rename intermediate signals to wr_wait/rd_wait

5 years agosplit out readable/writable setup
Luke Kenneth Casson Leighton [Mon, 13 May 2019 19:01:29 +0000 (20:01 +0100)]
split out readable/writable setup

5 years agogo_rd/go_wr not arrays any more
Luke Kenneth Casson Leighton [Mon, 13 May 2019 14:32:18 +0000 (15:32 +0100)]
go_rd/go_wr not arrays any more

5 years agouse operand latch, seems to work (6600 not cscore)
Luke Kenneth Casson Leighton [Mon, 13 May 2019 13:38:15 +0000 (14:38 +0100)]
use operand latch, seems to work (6600 not cscore)

5 years agoadd fn-unit src/dest latch registers
Luke Kenneth Casson Leighton [Mon, 13 May 2019 13:20:41 +0000 (14:20 +0100)]
add fn-unit src/dest latch registers

5 years agomake read/write-pending syncd
Luke Kenneth Casson Leighton [Mon, 13 May 2019 07:38:58 +0000 (08:38 +0100)]
make read/write-pending syncd

5 years agouse signals instead of arrays
Luke Kenneth Casson Leighton [Mon, 13 May 2019 07:30:01 +0000 (08:30 +0100)]
use signals instead of arrays

5 years agomake insn_i a signal of length n_insns instead of Array
Luke Kenneth Casson Leighton [Mon, 13 May 2019 06:30:10 +0000 (07:30 +0100)]
make insn_i a signal of length n_insns instead of Array

5 years agoscoreboard 6600 semi-working (sync/comb issue)
Luke Kenneth Casson Leighton [Sun, 12 May 2019 17:14:26 +0000 (18:14 +0100)]
scoreboard 6600 semi-working (sync/comb issue)

5 years agoremove unneeded imports
Luke Kenneth Casson Leighton [Sun, 12 May 2019 16:45:15 +0000 (17:45 +0100)]
remove unneeded imports

5 years agoexperimenting / debugging score6600
Luke Kenneth Casson Leighton [Sun, 12 May 2019 16:37:25 +0000 (17:37 +0100)]
experimenting / debugging score6600

5 years agosplit function units (and read/write pending vectors) to separate module
Luke Kenneth Casson Leighton [Sun, 12 May 2019 16:02:53 +0000 (17:02 +0100)]
split function units (and read/write pending vectors) to separate module

5 years agosplit computation units to separate class
Luke Kenneth Casson Leighton [Sun, 12 May 2019 14:55:18 +0000 (15:55 +0100)]
split computation units to separate class

5 years agoadd debug prints
Luke Kenneth Casson Leighton [Sun, 12 May 2019 14:23:01 +0000 (15:23 +0100)]
add debug prints

5 years agodebugging score6600 matrix
Luke Kenneth Casson Leighton [Sat, 11 May 2019 16:17:17 +0000 (17:17 +0100)]
debugging score6600 matrix

5 years agodebug score6600
Luke Kenneth Casson Leighton [Sat, 11 May 2019 11:50:41 +0000 (12:50 +0100)]
debug score6600

5 years agodependence cell, src2 is combinatorial (latch is already synchronous)
Luke Kenneth Casson Leighton [Sat, 11 May 2019 10:47:36 +0000 (11:47 +0100)]
dependence cell, src2 is combinatorial (latch is already synchronous)

5 years agotry removing some syncs
Luke Kenneth Casson Leighton [Sat, 11 May 2019 10:45:51 +0000 (11:45 +0100)]
try removing some syncs

5 years agoadd in function units to score6600
Luke Kenneth Casson Leighton [Sat, 11 May 2019 10:43:49 +0000 (11:43 +0100)]
add in function units to score6600

5 years agolink function units back in to score6600
Luke Kenneth Casson Leighton [Sat, 11 May 2019 09:51:56 +0000 (10:51 +0100)]
link function units back in to score6600

5 years agouse register latching in Computation Unit
Luke Kenneth Casson Leighton [Sat, 11 May 2019 07:18:42 +0000 (08:18 +0100)]
use register latching in Computation Unit

5 years agowhoops, readable/writable is inverted in fu picker vector
Luke Kenneth Casson Leighton [Sat, 11 May 2019 07:18:26 +0000 (08:18 +0100)]
whoops, readable/writable is inverted in fu picker vector

5 years agodependency cells enable on q not qn
Luke Kenneth Casson Leighton [Fri, 10 May 2019 12:19:04 +0000 (13:19 +0100)]
dependency cells enable on q not qn

5 years agostart connecting fu and reg dep matrices
Luke Kenneth Casson Leighton [Fri, 10 May 2019 11:47:51 +0000 (12:47 +0100)]
start connecting fu and reg dep matrices

5 years agoadd variant using original (ish) 6600 scoreboard
Luke Kenneth Casson Leighton [Fri, 10 May 2019 10:43:07 +0000 (11:43 +0100)]
add variant using original (ish) 6600 scoreboard

5 years agosplit out register decode from issue unit
Luke Kenneth Casson Leighton [Fri, 10 May 2019 05:43:01 +0000 (06:43 +0100)]
split out register decode from issue unit

5 years agoderive from Elaboratable
Luke Kenneth Casson Leighton [Fri, 10 May 2019 05:12:34 +0000 (06:12 +0100)]
derive from Elaboratable

5 years agoremove unneeded imports
Luke Kenneth Casson Leighton [Fri, 10 May 2019 05:09:10 +0000 (06:09 +0100)]
remove unneeded imports

5 years agomove code around to get set associative cache working
Luke Kenneth Casson Leighton [Fri, 10 May 2019 05:08:21 +0000 (06:08 +0100)]
move code around to get set associative cache working

5 years agoupdate cam test
Luke Kenneth Casson Leighton [Fri, 10 May 2019 05:02:50 +0000 (06:02 +0100)]
update cam test

5 years agoupdate pte test
Luke Kenneth Casson Leighton [Fri, 10 May 2019 05:01:42 +0000 (06:01 +0100)]
update pte test

5 years agoupdate perm validator test
Luke Kenneth Casson Leighton [Fri, 10 May 2019 05:00:46 +0000 (06:00 +0100)]
update perm validator test

5 years agoremove unneeded unit test
Luke Kenneth Casson Leighton [Fri, 10 May 2019 04:59:28 +0000 (05:59 +0100)]
remove unneeded unit test

5 years agofix imports in LFSR test
Luke Kenneth Casson Leighton [Fri, 10 May 2019 04:57:42 +0000 (05:57 +0100)]
fix imports in LFSR test

5 years agoupdate camentry unit test
Luke Kenneth Casson Leighton [Fri, 10 May 2019 04:56:51 +0000 (05:56 +0100)]
update camentry unit test

5 years agoadd src1/2 pending outputs
Luke Kenneth Casson Leighton [Fri, 10 May 2019 04:54:18 +0000 (05:54 +0100)]
add src1/2 pending outputs

5 years agoget scoreboard reasonably working
Luke Kenneth Casson Leighton [Thu, 9 May 2019 12:44:39 +0000 (13:44 +0100)]
get scoreboard reasonably working

5 years agodecode wrong way round on issue unit
Luke Kenneth Casson Leighton [Thu, 9 May 2019 11:20:32 +0000 (12:20 +0100)]
decode wrong way round on issue unit

5 years agoreduce ANDing chain (using NOR) in group picker
Luke Kenneth Casson Leighton [Thu, 9 May 2019 10:37:59 +0000 (11:37 +0100)]
reduce ANDing chain (using NOR) in group picker

5 years agofix logic-bug in group picker
Luke Kenneth Casson Leighton [Thu, 9 May 2019 08:26:48 +0000 (09:26 +0100)]
fix logic-bug in group picker

5 years agoadd python simulation of alu
Luke Kenneth Casson Leighton [Thu, 9 May 2019 01:34:28 +0000 (02:34 +0100)]
add python simulation of alu

5 years agomove sync from intpick to fn unit readable
Luke Kenneth Casson Leighton [Wed, 8 May 2019 16:41:20 +0000 (17:41 +0100)]
move sync from intpick to fn unit readable

5 years agomake readable_i sync, stops infinite loop
Luke Kenneth Casson Leighton [Wed, 8 May 2019 11:42:10 +0000 (12:42 +0100)]
make readable_i sync, stops infinite loop

5 years agoSRLatch not used in issue_unit
Luke Kenneth Casson Leighton [Wed, 8 May 2019 11:20:38 +0000 (12:20 +0100)]
SRLatch not used in issue_unit

5 years agoadd some more experimental instructions
Luke Kenneth Casson Leighton [Wed, 8 May 2019 11:12:22 +0000 (12:12 +0100)]
add some more experimental instructions

5 years agoadd some more experimental instructions
Luke Kenneth Casson Leighton [Wed, 8 May 2019 11:11:49 +0000 (12:11 +0100)]
add some more experimental instructions

5 years agodisable writethru for now
Luke Kenneth Casson Leighton [Wed, 8 May 2019 11:07:14 +0000 (12:07 +0100)]
disable writethru for now

5 years agodisable fpissue
Luke Kenneth Casson Leighton [Wed, 8 May 2019 11:06:55 +0000 (12:06 +0100)]
disable fpissue

5 years agomake SR Latch async again, make busy signal sync into issue unit
Luke Kenneth Casson Leighton [Wed, 8 May 2019 10:39:33 +0000 (11:39 +0100)]
make SR Latch async again, make busy signal sync into issue unit

5 years agorename variable wid -> dep
Luke Kenneth Casson Leighton [Wed, 8 May 2019 10:39:10 +0000 (11:39 +0100)]
rename variable wid -> dep

5 years agomake write latch sync in Function Unit
Luke Kenneth Casson Leighton [Wed, 8 May 2019 10:19:47 +0000 (11:19 +0100)]
make write latch sync in Function Unit

5 years agoadd decode out of src1 and src2 pending from FnUnit
Luke Kenneth Casson Leighton [Wed, 8 May 2019 09:52:19 +0000 (10:52 +0100)]
add decode out of src1 and src2 pending from FnUnit

5 years agoadd regfile array test
Luke Kenneth Casson Leighton [Wed, 8 May 2019 09:21:15 +0000 (10:21 +0100)]
add regfile array test

5 years agobegin debugging, temporary sync on issueunit
Luke Kenneth Casson Leighton [Wed, 8 May 2019 08:21:04 +0000 (09:21 +0100)]
begin debugging, temporary sync on issueunit