soc.git
2 years agoset separate "iside" signal in LoadStore1 to not confuse it
Luke Kenneth Casson Leighton [Tue, 7 Dec 2021 15:51:34 +0000 (15:51 +0000)]
set separate "iside" signal in LoadStore1 to not confuse it
with instr_fault (exception flag).  starting to experiment getting
instruction-side MMU requests to trigger

2 years agostart extending icache loadstore test
Luke Kenneth Casson Leighton [Tue, 7 Dec 2021 14:55:50 +0000 (14:55 +0000)]
start extending icache loadstore test

2 years agowhoops another serious error in the CacheTagArray
Luke Kenneth Casson Leighton [Tue, 7 Dec 2021 14:55:26 +0000 (14:55 +0000)]
whoops another serious error in the CacheTagArray
valid is of length NUM_WAYS not 1

2 years agoadd first i-cache fetch (non-virtual), no MMU lookup, copied unit
Luke Kenneth Casson Leighton [Tue, 7 Dec 2021 14:30:12 +0000 (14:30 +0000)]
add first i-cache fetch (non-virtual), no MMU lookup, copied unit
test from basic one in soc/experiment/icache.py

2 years agocode-comments
Luke Kenneth Casson Leighton [Tue, 7 Dec 2021 13:37:15 +0000 (13:37 +0000)]
code-comments

2 years agoadd in I-Cache into LoadStore1 - presently unused - so as to start on
Luke Kenneth Casson Leighton [Tue, 7 Dec 2021 13:32:16 +0000 (13:32 +0000)]
add in I-Cache into LoadStore1 - presently unused - so as to start on
a unit test (test_loadstore1.py).  this is not a normal place to start,
but I-Cache links cross-wise into so many other dependent areas that
it is quite tricky

2 years agoadd discussion links and bugreport
Luke Kenneth Casson Leighton [Tue, 7 Dec 2021 12:11:38 +0000 (12:11 +0000)]
add discussion links and bugreport

2 years agoinvert mmureq statements
Luke Kenneth Casson Leighton [Tue, 7 Dec 2021 01:12:33 +0000 (01:12 +0000)]
invert mmureq statements

2 years agosubmodule tidyup
Luke Kenneth Casson Leighton [Tue, 7 Dec 2021 01:06:04 +0000 (01:06 +0000)]
submodule tidyup

2 years agomake bitmanip operations conditional on pspec.draft_bitmanip
Jacob Lifshay [Tue, 7 Dec 2021 03:33:25 +0000 (19:33 -0800)]
make bitmanip operations conditional on pspec.draft_bitmanip

2 years agoformat code
Jacob Lifshay [Tue, 7 Dec 2021 03:26:40 +0000 (19:26 -0800)]
format code

2 years agomove rotator mode assignments as requested by lkcl
Jacob Lifshay [Tue, 7 Dec 2021 03:22:19 +0000 (19:22 -0800)]
move rotator mode assignments as requested by lkcl

2 years agoformat code
Jacob Lifshay [Tue, 7 Dec 2021 03:17:07 +0000 (19:17 -0800)]
format code

2 years agotidyup, comments
Luke Kenneth Casson Leighton [Tue, 7 Dec 2021 01:00:56 +0000 (01:00 +0000)]
tidyup, comments

2 years agodebug print
Luke Kenneth Casson Leighton [Tue, 7 Dec 2021 00:03:10 +0000 (00:03 +0000)]
debug print

2 years agoanother major bug, CacheTagArray valid was only 1 bit not NUM_WAYS
Luke Kenneth Casson Leighton [Mon, 6 Dec 2021 23:57:33 +0000 (23:57 +0000)]
another major bug, CacheTagArray valid was only 1 bit not NUM_WAYS

2 years agotidyup: move hit_set to DCachePendingHit in dcache.py
Luke Kenneth Casson Leighton [Mon, 6 Dec 2021 23:40:40 +0000 (23:40 +0000)]
tidyup: move hit_set to DCachePendingHit in dcache.py

2 years agodcache.py tidyup
Luke Kenneth Casson Leighton [Mon, 6 Dec 2021 23:35:44 +0000 (23:35 +0000)]
dcache.py tidyup

2 years agorename dtlb to dtlb_valid and tidyup
Luke Kenneth Casson Leighton [Mon, 6 Dec 2021 23:17:35 +0000 (23:17 +0000)]
rename dtlb to dtlb_valid and tidyup
remove dtlb argument (not needed) because dtlb_valid is now localised
to DTLBUpdate Module

also put in some code-comments

2 years agoconvert TLBArray to TLBValidArray
Luke Kenneth Casson Leighton [Mon, 6 Dec 2021 22:43:29 +0000 (22:43 +0000)]
convert TLBArray to TLBValidArray
(because PTE and TAG are now each in a Memory)

2 years agoconvert DTLBUpdate to use a pair of Memorys
Luke Kenneth Casson Leighton [Mon, 6 Dec 2021 22:41:58 +0000 (22:41 +0000)]
convert DTLBUpdate to use a pair of Memorys
one for PTEs and one for TAGs

2 years agomore signals local to DTLBUpdate
Luke Kenneth Casson Leighton [Mon, 6 Dec 2021 20:37:37 +0000 (20:37 +0000)]
more signals local to DTLBUpdate

2 years agomore signals local to DTLBUpdate
Luke Kenneth Casson Leighton [Mon, 6 Dec 2021 20:30:47 +0000 (20:30 +0000)]
more signals local to DTLBUpdate

2 years agoupdate DTLBUpdate to reflect internal API now
Luke Kenneth Casson Leighton [Mon, 6 Dec 2021 20:25:58 +0000 (20:25 +0000)]
update DTLBUpdate to reflect internal API now

2 years agoooo nasty bug. used tlb_hit.way instead of tlb_hit.valid
Luke Kenneth Casson Leighton [Mon, 6 Dec 2021 17:40:12 +0000 (17:40 +0000)]
ooo nasty bug.  used tlb_hit.way instead of tlb_hit.valid

2 years agomove DTLB Tags/Valids/PTEs into DTLBUpdate module
Luke Kenneth Casson Leighton [Mon, 6 Dec 2021 17:33:31 +0000 (17:33 +0000)]
move DTLB Tags/Valids/PTEs into DTLBUpdate module
drastically simplifies DCache graphviz and also makes it clear that
TLBs have to be a Memory SRAM

2 years agostart moving TLBArray into DTLBUpdate
Luke Kenneth Casson Leighton [Mon, 6 Dec 2021 17:14:45 +0000 (17:14 +0000)]
start moving TLBArray into DTLBUpdate

2 years agoPLRUs were selecting an output index, only one selected
Luke Kenneth Casson Leighton [Mon, 6 Dec 2021 17:00:29 +0000 (17:00 +0000)]
PLRUs were selecting an output index, only one selected
therefore move the selection from the PLRUs into the module.
simplified

2 years agorepeated copies of read/write addr/sel to Cache SRAMs
Luke Kenneth Casson Leighton [Mon, 6 Dec 2021 16:01:13 +0000 (16:01 +0000)]
repeated copies of read/write addr/sel to Cache SRAMs
moved rd/wr addr/sel outside of loops, only creates one MUX set now

2 years agomove bank of PLRUs to their own submodule in both dcache.py and icache.py
Luke Kenneth Casson Leighton [Mon, 6 Dec 2021 15:45:40 +0000 (15:45 +0000)]
move bank of PLRUs to their own submodule in both dcache.py and icache.py

2 years agocode-comments
Luke Kenneth Casson Leighton [Mon, 6 Dec 2021 14:49:20 +0000 (14:49 +0000)]
code-comments

2 years agouse binary-to-unary encoders in dcache.py
Luke Kenneth Casson Leighton [Mon, 6 Dec 2021 14:41:32 +0000 (14:41 +0000)]
use binary-to-unary encoders in dcache.py

2 years agoglobal (one) do_read signal in cache_rams dcache.py
Luke Kenneth Casson Leighton [Mon, 6 Dec 2021 14:11:45 +0000 (14:11 +0000)]
global (one) do_read signal in cache_rams dcache.py

2 years agouse one-hot binary-to-unary in dcache.py
Luke Kenneth Casson Leighton [Mon, 6 Dec 2021 14:01:56 +0000 (14:01 +0000)]
use one-hot binary-to-unary in dcache.py

2 years agouse i_in.req to gate hit_way via Decoder in icache.py
Luke Kenneth Casson Leighton [Mon, 6 Dec 2021 13:50:48 +0000 (13:50 +0000)]
use i_in.req to gate hit_way via Decoder in icache.py

2 years agouse Decoder (binary-to-unary) in icache.py to deal with CAM creation
Luke Kenneth Casson Leighton [Mon, 6 Dec 2021 13:36:04 +0000 (13:36 +0000)]
use Decoder (binary-to-unary) in icache.py to deal with CAM creation

2 years agouse unary encoding (one-hot) for replace_way hit_way etc.
Luke Kenneth Casson Leighton [Sun, 5 Dec 2021 23:16:28 +0000 (23:16 +0000)]
use unary encoding (one-hot) for replace_way hit_way etc.
otherwise it produces binary CAM-compares

2 years agocode-comments
Luke Kenneth Casson Leighton [Sun, 5 Dec 2021 22:02:49 +0000 (22:02 +0000)]
code-comments

2 years agowhitespace and minor cleanup of D-Cache
Luke Kenneth Casson Leighton [Sun, 5 Dec 2021 21:52:25 +0000 (21:52 +0000)]
whitespace and minor cleanup of D-Cache

2 years agomore use of TLBHit Record in D-Cache
Luke Kenneth Casson Leighton [Sun, 5 Dec 2021 21:41:41 +0000 (21:41 +0000)]
more use of TLBHit Record in D-Cache

2 years agocorrect tlb_hit_way and index sizes, use TLBHit Record in D-Cache
Luke Kenneth Casson Leighton [Sun, 5 Dec 2021 21:33:20 +0000 (21:33 +0000)]
correct tlb_hit_way and index sizes, use TLBHit Record in D-Cache

2 years agouse TLBRecord in D-Cache for which TLB is selected
Luke Kenneth Casson Leighton [Sun, 5 Dec 2021 21:11:27 +0000 (21:11 +0000)]
use TLBRecord in D-Cache for which TLB is selected

2 years agosplit out TLBRecord, correct number of valid bits
Luke Kenneth Casson Leighton [Sun, 5 Dec 2021 20:48:35 +0000 (20:48 +0000)]
split out TLBRecord, correct number of valid bits

2 years agouse Record in DCache for TLB
Luke Kenneth Casson Leighton [Sun, 5 Dec 2021 20:39:15 +0000 (20:39 +0000)]
use Record in DCache for TLB

2 years agouse Record in D-Cache Cache Tags
Luke Kenneth Casson Leighton [Sun, 5 Dec 2021 20:31:26 +0000 (20:31 +0000)]
use Record in D-Cache Cache Tags

2 years agowhitespace
Luke Kenneth Casson Leighton [Sun, 5 Dec 2021 20:20:27 +0000 (20:20 +0000)]
whitespace

2 years agouse Record for I-Cache Cache Tag/Valid
Luke Kenneth Casson Leighton [Sun, 5 Dec 2021 20:18:46 +0000 (20:18 +0000)]
use Record for I-Cache Cache Tag/Valid

2 years agowhitespace
Luke Kenneth Casson Leighton [Sun, 5 Dec 2021 20:05:47 +0000 (20:05 +0000)]
whitespace

2 years agouse Record for ICache TLB
Luke Kenneth Casson Leighton [Sun, 5 Dec 2021 20:02:18 +0000 (20:02 +0000)]
use Record for ICache TLB

2 years agosorting out test_mmu_dcache.py to use wb_get
Luke Kenneth Casson Leighton [Sun, 5 Dec 2021 14:24:48 +0000 (14:24 +0000)]
sorting out test_mmu_dcache.py to use wb_get

2 years agoconvert icache.py to standard wishbone Interface
Luke Kenneth Casson Leighton [Sun, 5 Dec 2021 14:19:27 +0000 (14:19 +0000)]
convert icache.py to standard wishbone Interface

2 years agofake up wishbone stall signal in icache.
Luke Kenneth Casson Leighton [Sun, 5 Dec 2021 13:38:37 +0000 (13:38 +0000)]
fake up wishbone stall signal in icache.
same thing is done in dcache

2 years agofix icache row store issue
Luke Kenneth Casson Leighton [Sun, 5 Dec 2021 13:38:19 +0000 (13:38 +0000)]
fix icache row store issue

2 years agousing same tag/row functions as in dcache.py
Luke Kenneth Casson Leighton [Sun, 5 Dec 2021 12:41:56 +0000 (12:41 +0000)]
using same tag/row functions as in dcache.py

2 years agomore signal sizes in icache.py
Luke Kenneth Casson Leighton [Sun, 5 Dec 2021 12:35:20 +0000 (12:35 +0000)]
more signal sizes in icache.py

2 years agoincorrect Signal sizes in icache.py,
Luke Kenneth Casson Leighton [Sun, 5 Dec 2021 12:26:43 +0000 (12:26 +0000)]
incorrect Signal sizes in icache.py,
e.g. using NUM_WAYS instead of WAY_BITS

2 years agosorting out icache.py, used to work
Luke Kenneth Casson Leighton [Sun, 5 Dec 2021 12:11:39 +0000 (12:11 +0000)]
sorting out icache.py, used to work

2 years agoremove redundant code
Luke Kenneth Casson Leighton [Sun, 5 Dec 2021 11:47:52 +0000 (11:47 +0000)]
remove redundant code

2 years agoadd I-Cache standard bus (not used yet)
Luke Kenneth Casson Leighton [Sun, 5 Dec 2021 11:46:53 +0000 (11:46 +0000)]
add I-Cache standard bus (not used yet)

2 years agoremove yet another duplicate copy of wb_get, possible (again) due to
Luke Kenneth Casson Leighton [Sun, 5 Dec 2021 11:25:10 +0000 (11:25 +0000)]
remove yet another duplicate copy of wb_get, possible (again) due to
adding wishbone standard interface to D-Cache

2 years agoreplace yet another duplicate copy of wb_get, possible after renaming
Luke Kenneth Casson Leighton [Sun, 5 Dec 2021 11:23:07 +0000 (11:23 +0000)]
replace yet another duplicate copy of wb_get, possible after renaming
the D-Cache wishbone bus

2 years agowishbone bus convert on dcache
Luke Kenneth Casson Leighton [Sun, 5 Dec 2021 01:29:58 +0000 (01:29 +0000)]
wishbone bus convert on dcache

2 years agocorrect import of wg_get function
Luke Kenneth Casson Leighton [Sun, 5 Dec 2021 00:26:50 +0000 (00:26 +0000)]
correct import of wg_get function

2 years agoremove yet another duplicated copy of wb_get and add some better
Luke Kenneth Casson Leighton [Sat, 4 Dec 2021 18:37:58 +0000 (18:37 +0000)]
remove yet another duplicated copy of wb_get and add some better
testing in misaligned mmu test

2 years agorename function which needs replacing
Luke Kenneth Casson Leighton [Sat, 4 Dec 2021 18:27:46 +0000 (18:27 +0000)]
rename function which needs replacing

2 years agoshould have been using common version of wb_get, not 8 duplicates
Luke Kenneth Casson Leighton [Sat, 4 Dec 2021 18:22:06 +0000 (18:22 +0000)]
should have been using common version of wb_get, not 8 duplicates

2 years agoshould not have been duplicating wb_get function in 5 places
Luke Kenneth Casson Leighton [Sat, 4 Dec 2021 18:17:13 +0000 (18:17 +0000)]
should not have been duplicating wb_get function in 5 places

2 years agoget test_mmu_dcache.py working again
Luke Kenneth Casson Leighton [Sat, 4 Dec 2021 18:15:11 +0000 (18:15 +0000)]
get test_mmu_dcache.py working again

2 years agoremove wb_get, should not have been duplicated
Luke Kenneth Casson Leighton [Sat, 4 Dec 2021 18:02:02 +0000 (18:02 +0000)]
remove wb_get, should not have been duplicated

2 years agoremove wb_get, should not have been massively duplicated. moved to openpower-isa
Luke Kenneth Casson Leighton [Sat, 4 Dec 2021 18:00:01 +0000 (18:00 +0000)]
remove wb_get, should not have been massively duplicated. moved to openpower-isa

2 years agofix return results from pi_ld
Luke Kenneth Casson Leighton [Sat, 4 Dec 2021 17:55:15 +0000 (17:55 +0000)]
fix return results from pi_ld

2 years agowark-wark, broke mmu with removing rin. reverted
Luke Kenneth Casson Leighton [Sat, 4 Dec 2021 15:27:42 +0000 (15:27 +0000)]
wark-wark, broke mmu with removing rin.  reverted

2 years agofixed wait_addr to exit immediately on exception
Tobias Platen [Sat, 4 Dec 2021 15:19:52 +0000 (16:19 +0100)]
fixed wait_addr to exit immediately on exception

2 years agotidyup, comments
Luke Kenneth Casson Leighton [Sat, 4 Dec 2021 15:11:07 +0000 (15:11 +0000)]
tidyup, comments

2 years agotidyup mmu
Luke Kenneth Casson Leighton [Sat, 4 Dec 2021 15:05:18 +0000 (15:05 +0000)]
tidyup mmu

2 years agosigh in MMU FSM use direct access to ldst.dar/dsisr for OP_MFSPR
Luke Kenneth Casson Leighton [Sat, 4 Dec 2021 14:59:52 +0000 (14:59 +0000)]
sigh in MMU FSM use direct access to ldst.dar/dsisr for OP_MFSPR
and likewise to mmu.

2 years agoremove DAR from PortInterface (where is the data going? there is no place
Luke Kenneth Casson Leighton [Sat, 4 Dec 2021 13:09:17 +0000 (13:09 +0000)]
remove DAR from PortInterface (where is the data going? there is no place
to put DAR if transmitted over PortInterface? what receives it? nothing

2 years agostop using dar_o from PortInterface, get DAR directly from LoadStore1
Luke Kenneth Casson Leighton [Sat, 4 Dec 2021 13:05:35 +0000 (13:05 +0000)]
stop using dar_o from PortInterface, get DAR directly from LoadStore1

2 years agoput DSISR and DAR publicly accessible in LoadStore1
Luke Kenneth Casson Leighton [Sat, 4 Dec 2021 13:05:05 +0000 (13:05 +0000)]
put DSISR and DAR publicly accessible in LoadStore1
these should ONLY be READ, NOT written to

2 years agowhoops fix up exception happened if alignment triggers from LoadStore1
Luke Kenneth Casson Leighton [Sat, 4 Dec 2021 13:01:26 +0000 (13:01 +0000)]
whoops fix up exception happened if alignment triggers from LoadStore1
set_wr_addr or set_rd_addr

2 years agofix pi_st which should not be trying to wait for the address
Luke Kenneth Casson Leighton [Sat, 4 Dec 2021 12:54:22 +0000 (12:54 +0000)]
fix pi_st which should not be trying to wait for the address
when an exception occurs.
TODO: fix wait_addr so that it exits if an exception occurs

2 years agofixing DAR updating from exceptions
Luke Kenneth Casson Leighton [Sat, 4 Dec 2021 12:03:07 +0000 (12:03 +0000)]
fixing DAR updating from exceptions

2 years agowhoops
Luke Kenneth Casson Leighton [Sat, 4 Dec 2021 11:46:57 +0000 (11:46 +0000)]
whoops

2 years agoMMU lookup DSISR load bit inverted in LoadStore1
Luke Kenneth Casson Leighton [Sat, 4 Dec 2021 11:46:34 +0000 (11:46 +0000)]
MMU lookup DSISR load bit inverted in LoadStore1

2 years agostore DAR in LoadStore1
Luke Kenneth Casson Leighton [Sat, 4 Dec 2021 11:45:59 +0000 (11:45 +0000)]
store DAR in LoadStore1

2 years agonot busy if excrption occurs on MMU_LOOKUP in loadstore.py
Luke Kenneth Casson Leighton [Sat, 4 Dec 2021 04:06:53 +0000 (04:06 +0000)]
not busy if excrption occurs on MMU_LOOKUP in loadstore.py

2 years agoadd means to update dsisr from MMU FSM. TODO: add a back-communication
Luke Kenneth Casson Leighton [Sat, 4 Dec 2021 01:25:05 +0000 (01:25 +0000)]
add means to update dsisr from MMU FSM. TODO: add a back-communication
to allow LoadStore1 to update a copy of dsisr in the MMU FSM

2 years agopriv_mode/virt_mode are set in the request, which is passed through
Luke Kenneth Casson Leighton [Fri, 3 Dec 2021 19:35:41 +0000 (19:35 +0000)]
priv_mode/virt_mode are set in the request, which is passed through
to the MMU, via the PortInterface "pr" parameter.

MMU should not itself be attempting to set d_in.priv_mode/virt_mode

this fixes case_5_ldst_exception

2 years agoin loadstore.py set align_intr from request which comes from PortInterface
Luke Kenneth Casson Leighton [Fri, 3 Dec 2021 19:19:36 +0000 (19:19 +0000)]
in loadstore.py set align_intr from request which comes from PortInterface
misalign, set it globally rather than from latched copy ldst_r

2 years agodriver conflict on priv_mode and virt_mode, do not understand right now,
Luke Kenneth Casson Leighton [Fri, 3 Dec 2021 19:17:11 +0000 (19:17 +0000)]
driver conflict on priv_mode and virt_mode, do not understand right now,
commenting them out in loadstore.py

2 years agofix up test_loadstore1.py
Luke Kenneth Casson Leighton [Fri, 3 Dec 2021 17:41:33 +0000 (17:41 +0000)]
fix up test_loadstore1.py

numerous things:
1) pi_ld and pi_st now return the exception information (full status)
   because pi_ld and pi_st both reset the PortInterface: once that
   happens the exception information is DESTROYED... therefore the
   exception information MUST be obtained INSIDE pi_ld and pi_st

2) cleanup of whitespace

3) added some (probably unnecessary) yields in between LD/ST in the
   exceptions test, to make the gtkwave output clearer

4) fixed the exceptions test and enabled it by default, now

2 years agoin loadstore.py, when an exception is done or if the FSM
Luke Kenneth Casson Leighton [Fri, 3 Dec 2021 17:38:26 +0000 (17:38 +0000)]
in loadstore.py, when an exception is done or if the FSM
is done, reset back to idle and indicate "not busy"

2 years agofix PortInterfaceBase
Luke Kenneth Casson Leighton [Fri, 3 Dec 2021 17:37:26 +0000 (17:37 +0000)]
fix PortInterfaceBase

* setting busy latch LOW on exception is not ok: this creates a
  combinatorial loop
* setting st_done permanently was a bug, it left st_done permanently HI
* setting st_done when an exception is raised was also a bug

2 years agofix up LDST test functions pi_ld and pi_st to respect timing
Luke Kenneth Casson Leighton [Fri, 3 Dec 2021 17:35:16 +0000 (17:35 +0000)]
fix up LDST test functions pi_ld and pi_st to respect timing
(combinatorial setting followed by test followed by immediate unsetting
is *not* ok.  it has to be set WAIT (yield one clock) and *then* clear)

added a simulation function get_exception_info() which returns a
LDSTExceptionTuple containing the yield()ed exception information
reason: at the time that the exception was raised, THAT is when
the exception information must be obtained.  by the time that
the LDST port is_ld_i/is_st_i is lowered, that is far too late

2 years agowhitespace
Luke Kenneth Casson Leighton [Fri, 3 Dec 2021 15:51:04 +0000 (15:51 +0000)]
whitespace

2 years agoadd misaligned ld/st to trigger an exception
Luke Kenneth Casson Leighton [Fri, 3 Dec 2021 15:22:10 +0000 (15:22 +0000)]
add misaligned ld/st to trigger an exception

2 years agocomment out dsisr and dar in mmu FSM for now
Luke Kenneth Casson Leighton [Fri, 3 Dec 2021 15:09:22 +0000 (15:09 +0000)]
comment out dsisr and dar in mmu FSM for now

2 years agoMerge branch 'master' of ssh://git.libre-riscv.org:922/soc
Tobias Platen [Thu, 2 Dec 2021 19:01:56 +0000 (20:01 +0100)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc

2 years agocleanup test_compldst_multi_mmu.py
Tobias Platen [Thu, 2 Dec 2021 18:57:43 +0000 (19:57 +0100)]
cleanup test_compldst_multi_mmu.py

2 years agoadd a bitvector remap function, the plan is to use it to reduce the size of
Luke Kenneth Casson Leighton [Thu, 2 Dec 2021 16:56:58 +0000 (16:56 +0000)]
add a bitvector remap function, the plan is to use it to reduce the size of
regfile bitvector hazards