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Luke Kenneth Casson Leighton [Tue, 27 Nov 2018 04:28:28 +0000 (04:28 +0000)]
move handle trap out to separate module, bit messy
Luke Kenneth Casson Leighton [Tue, 27 Nov 2018 04:08:38 +0000 (04:08 +0000)]
split out cpu handle_trap
Luke Kenneth Casson Leighton [Tue, 27 Nov 2018 02:40:34 +0000 (02:40 +0000)]
split out cpu_mip to separate module
Luke Kenneth Casson Leighton [Tue, 27 Nov 2018 02:29:12 +0000 (02:29 +0000)]
split out cpu_mie into separate module
Luke Kenneth Casson Leighton [Tue, 27 Nov 2018 02:14:16 +0000 (02:14 +0000)]
split out MStatus to separate module
Luke Kenneth Casson Leighton [Tue, 27 Nov 2018 00:20:06 +0000 (00:20 +0000)]
split cpu loadstore calc out
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 23:58:55 +0000 (23:58 +0000)]
break out cpu load/store calculation into separate module
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 12:33:35 +0000 (12:33 +0000)]
move get_fetch_action to separate verilog file
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 11:19:14 +0000 (11:19 +0000)]
prepare get_fetch_action for move to separate module
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 11:12:54 +0000 (11:12 +0000)]
whoops missed out branch_taken logic from fetch_action
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 09:38:51 +0000 (09:38 +0000)]
rename register varnames to regfile
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 09:35:25 +0000 (09:35 +0000)]
reorganise cpu regfile, to separate module, with 2R1W interface
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 07:41:29 +0000 (07:41 +0000)]
complete csrs
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 06:26:40 +0000 (06:26 +0000)]
add misa and mstatus csrs
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 05:44:42 +0000 (05:44 +0000)]
add clock domains doc to README
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 04:50:26 +0000 (04:50 +0000)]
start adding csrs
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 04:45:05 +0000 (04:45 +0000)]
move stuff to MInfo
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 04:21:55 +0000 (04:21 +0000)]
split CSR to separate class
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 04:10:18 +0000 (04:10 +0000)]
add handle_main
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 03:00:17 +0000 (03:00 +0000)]
add counters (TODO)
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 02:54:25 +0000 (02:54 +0000)]
add csr_is_valid
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 02:34:51 +0000 (02:34 +0000)]
start on csr op valid
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 02:30:38 +0000 (02:30 +0000)]
CSR decoding
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 02:24:46 +0000 (02:24 +0000)]
add handle_trap
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 02:19:23 +0000 (02:19 +0000)]
add handle_trap
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 01:37:58 +0000 (01:37 +0000)]
add handle trap
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 01:21:03 +0000 (01:21 +0000)]
complete get_fetch_action, move to class Fetch
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 01:01:03 +0000 (01:01 +0000)]
start converting get_fetch_action
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 00:50:59 +0000 (00:50 +0000)]
fetch output state class
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 00:48:34 +0000 (00:48 +0000)]
create Fetch class
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 00:41:06 +0000 (00:41 +0000)]
add get_fetch_action ready for conversion
Luke Kenneth Casson Leighton [Sun, 25 Nov 2018 23:54:06 +0000 (23:54 +0000)]
add to README
Luke Kenneth Casson Leighton [Sun, 25 Nov 2018 11:16:16 +0000 (11:16 +0000)]
class-ify fetch_action
Luke Kenneth Casson Leighton [Sun, 25 Nov 2018 11:07:19 +0000 (11:07 +0000)]
add mstatus, mip and vendor/arch/mimpl
Luke Kenneth Casson Leighton [Sun, 25 Nov 2018 10:20:49 +0000 (10:20 +0000)]
add MISA and MIE
Luke Kenneth Casson Leighton [Sun, 25 Nov 2018 08:17:02 +0000 (08:17 +0000)]
add more logic and mstatus
Luke Kenneth Casson Leighton [Sun, 25 Nov 2018 06:43:31 +0000 (06:43 +0000)]
calculate lui_auipc
Luke Kenneth Casson Leighton [Sun, 25 Nov 2018 06:23:36 +0000 (06:23 +0000)]
minor reorg, add alu
Luke Kenneth Casson Leighton [Sun, 25 Nov 2018 06:21:00 +0000 (06:21 +0000)]
minor reorg, add alu
Luke Kenneth Casson Leighton [Sun, 25 Nov 2018 05:42:46 +0000 (05:42 +0000)]
convert loaded value
Luke Kenneth Casson Leighton [Sun, 25 Nov 2018 04:31:19 +0000 (04:31 +0000)]
load value
Luke Kenneth Casson Leighton [Sun, 25 Nov 2018 03:15:58 +0000 (03:15 +0000)]
more cpu logic
Luke Kenneth Casson Leighton [Sun, 25 Nov 2018 02:18:20 +0000 (02:18 +0000)]
small cpu reorg
Luke Kenneth Casson Leighton [Sun, 25 Nov 2018 01:56:05 +0000 (01:56 +0000)]
add load/store misaligned
Luke Kenneth Casson Leighton [Sun, 25 Nov 2018 01:15:43 +0000 (01:15 +0000)]
add CPU decoder instance
Luke Kenneth Casson Leighton [Sun, 25 Nov 2018 00:56:47 +0000 (00:56 +0000)]
add cpuFetchStage instance
Luke Kenneth Casson Leighton [Sun, 25 Nov 2018 00:11:10 +0000 (00:11 +0000)]
adding call out to cpu_memory_interface verilog module in cpu.py
Luke Kenneth Casson Leighton [Sat, 24 Nov 2018 12:15:46 +0000 (12:15 +0000)]
stub cpu.py
Luke Kenneth Casson Leighton [Sat, 24 Nov 2018 01:37:16 +0000 (01:37 +0000)]
tidyup
Luke Kenneth Casson Leighton [Sat, 24 Nov 2018 01:36:42 +0000 (01:36 +0000)]
document decode functions
Luke Kenneth Casson Leighton [Sat, 24 Nov 2018 01:34:30 +0000 (01:34 +0000)]
tidyup
Luke Kenneth Casson Leighton [Sat, 24 Nov 2018 01:22:06 +0000 (01:22 +0000)]
no immediate constant, make 32-bit wide
Luke Kenneth Casson Leighton [Sat, 24 Nov 2018 01:20:35 +0000 (01:20 +0000)]
big reorg, class-ify constants
Luke Kenneth Casson Leighton [Sat, 24 Nov 2018 01:19:23 +0000 (01:19 +0000)]
big reorg, class-ify constants
Luke Kenneth Casson Leighton [Sat, 24 Nov 2018 00:01:26 +0000 (00:01 +0000)]
cleanup cpu_decode.py
Luke Kenneth Casson Leighton [Fri, 23 Nov 2018 23:44:51 +0000 (23:44 +0000)]
more cpu decode conversion
Luke Kenneth Casson Leighton [Fri, 23 Nov 2018 15:23:49 +0000 (15:23 +0000)]
add cpu decode cases
Luke Kenneth Casson Leighton [Fri, 23 Nov 2018 12:21:52 +0000 (12:21 +0000)]
add cpu_decoder.py
Luke Kenneth Casson Leighton [Fri, 23 Nov 2018 11:36:50 +0000 (11:36 +0000)]
add riscvdefs.py
Luke Kenneth Casson Leighton [Fri, 23 Nov 2018 10:31:26 +0000 (10:31 +0000)]
remove sync set output_state
Luke Kenneth Casson Leighton [Fri, 23 Nov 2018 07:55:23 +0000 (07:55 +0000)]
sort out memory_interface_fetch_address
Luke Kenneth Casson Leighton [Fri, 23 Nov 2018 03:56:49 +0000 (03:56 +0000)]
add some arbitrary math into example
Luke Kenneth Casson Leighton [Fri, 23 Nov 2018 03:52:20 +0000 (03:52 +0000)]
call value_bits_sign direct
Luke Kenneth Casson Leighton [Fri, 23 Nov 2018 03:45:44 +0000 (03:45 +0000)]
can`t stand list incomprehension
Luke Kenneth Casson Leighton [Fri, 23 Nov 2018 03:44:24 +0000 (03:44 +0000)]
add example pipeline.py
Luke Kenneth Casson Leighton [Fri, 23 Nov 2018 00:08:15 +0000 (00:08 +0000)]
corrections, clash fetch_action and self.fetch_action
Luke Kenneth Casson Leighton [Fri, 23 Nov 2018 00:01:27 +0000 (00:01 +0000)]
add conversion code, see what happens
Luke Kenneth Casson Leighton [Thu, 22 Nov 2018 22:35:59 +0000 (22:35 +0000)]
more cleanup
Luke Kenneth Casson Leighton [Thu, 22 Nov 2018 19:12:39 +0000 (19:12 +0000)]
cleanup, use sync instead of comb where appropriate
Luke Kenneth Casson Leighton [Thu, 22 Nov 2018 02:02:56 +0000 (02:02 +0000)]
add cpudefs.py
Luke Kenneth Casson Leighton [Thu, 22 Nov 2018 00:21:59 +0000 (00:21 +0000)]
reorg case statement
Luke Kenneth Casson Leighton [Wed, 21 Nov 2018 15:11:28 +0000 (15:11 +0000)]
convert case statement
Luke Kenneth Casson Leighton [Wed, 21 Nov 2018 14:38:42 +0000 (14:38 +0000)]
converting cpu_fetch_stage to migen
Jacob Lifshay [Wed, 21 Mar 2018 01:19:21 +0000 (18:19 -0700)]
add licenses and readme
projects / rv32.git / log