Cole Poirier [Mon, 10 Aug 2020 16:17:36 +0000 (09:17 -0700)]
fix bug 450 comments 8,9,10
Cole Poirier [Mon, 10 Aug 2020 16:10:51 +0000 (09:10 -0700)]
Fix bug 450 comment 7
Cole Poirier [Mon, 10 Aug 2020 16:05:53 +0000 (09:05 -0700)]
mmu.py add line I forgot to translate from mmu.vhdl
Cole Poirier [Mon, 10 Aug 2020 01:50:40 +0000 (18:50 -0700)]
Merge branch 'master' of git.libre-soc.org:soc
Cole Poirier [Mon, 10 Aug 2020 01:50:08 +0000 (18:50 -0700)]
mmu.vhdl translation to mmu.py 95 percent complete
Luke Kenneth Casson Leighton [Sun, 9 Aug 2020 21:33:50 +0000 (22:33 +0100)]
stop combinatorial loop in pi2ls
Luke Kenneth Casson Leighton [Sun, 9 Aug 2020 21:25:32 +0000 (22:25 +0100)]
write pulse in issuer
Luke Kenneth Casson Leighton [Sun, 9 Aug 2020 21:18:16 +0000 (22:18 +0100)]
fix combinatorial loop in ldst compunit
Luke Kenneth Casson Leighton [Sun, 9 Aug 2020 18:47:27 +0000 (19:47 +0100)]
use rising edge detection on st go_i/rel_o
Luke Kenneth Casson Leighton [Sun, 9 Aug 2020 15:43:48 +0000 (16:43 +0100)]
add logical test issuer case
Luke Kenneth Casson Leighton [Sun, 9 Aug 2020 15:25:24 +0000 (16:25 +0100)]
get rid of MSR read combinatorial loop
Luke Kenneth Casson Leighton [Sun, 9 Aug 2020 15:08:58 +0000 (16:08 +0100)]
delay go_st by one cycle, break combinatorial loop
Luke Kenneth Casson Leighton [Sun, 9 Aug 2020 14:20:11 +0000 (15:20 +0100)]
divwo case makes test_issuer stay busy!
Luke Kenneth Casson Leighton [Sun, 9 Aug 2020 14:01:23 +0000 (15:01 +0100)]
add extra divwo regression test
Luke Kenneth Casson Leighton [Sun, 9 Aug 2020 09:57:58 +0000 (10:57 +0100)]
compalu combinatorial loop detected
Cole Poirier [Sat, 8 Aug 2020 17:58:00 +0000 (10:58 -0700)]
Merge branch 'master' of git.libre-soc.org:soc
Cole Poirier [Sat, 8 Aug 2020 17:57:37 +0000 (10:57 -0700)]
Update test case_mulli
Tobias Platen [Sat, 8 Aug 2020 11:54:42 +0000 (13:54 +0200)]
addr_split.py: shift bytes not bits
Cole Poirier [Fri, 7 Aug 2020 23:50:24 +0000 (16:50 -0700)]
Update test case_mulli
Cole Poirier [Fri, 7 Aug 2020 01:05:10 +0000 (18:05 -0700)]
Update test case_mulli, I think it now works correctly
Cole Poirier [Fri, 7 Aug 2020 00:19:49 +0000 (17:19 -0700)]
Update mulli to try to use immediates not registers
Cole Poirier [Thu, 6 Aug 2020 19:21:09 +0000 (12:21 -0700)]
Fix mmu.py formatting
Cole Poirier [Thu, 6 Aug 2020 18:18:20 +0000 (11:18 -0700)]
Fix formatting
Cole Poirier [Thu, 6 Aug 2020 17:53:26 +0000 (10:53 -0700)]
Initial commit of translation of microwatt mmu.vhdl into nmigen
Cole Poirier [Thu, 6 Aug 2020 17:49:56 +0000 (10:49 -0700)]
Merge branch 'master' of git.libre-soc.org:soc
Cole Poirier [Thu, 6 Aug 2020 17:49:30 +0000 (10:49 -0700)]
Update test case_all_rb_close_to_ov
Cole Poirier [Thu, 6 Aug 2020 17:28:48 +0000 (10:28 -0700)]
Update test case_all_rb_close_to_ov
Luke Kenneth Casson Leighton [Thu, 6 Aug 2020 15:38:47 +0000 (16:38 +0100)]
fix LDST PortInterface FSM interaction
when the WB Bus delayed "ack", the LDST PI FSM was not "listening" and
assumed that the operation had completed. a bit of a rewrite was required
to get it to wait until LD/ST operations had actually fully completed
Luke Kenneth Casson Leighton [Wed, 5 Aug 2020 18:46:51 +0000 (19:46 +0100)]
MULS on parameter b needed to check whether it was sign-extended
Cole Poirier [Thu, 6 Aug 2020 00:38:33 +0000 (17:38 -0700)]
Add special test for case_mulli, apply autopep8
Cole Poirier [Wed, 5 Aug 2020 21:58:07 +0000 (14:58 -0700)]
Add test case_all_rb_close_to_ov
Cole Poirier [Wed, 5 Aug 2020 21:21:19 +0000 (14:21 -0700)]
Remove mulli from instrs in test case_all*, add TODO for mulli special
test case
Cole Poirier [Wed, 5 Aug 2020 21:02:47 +0000 (14:02 -0700)]
Add new test_values to tests case_all and case_all_rb_randint
Cole Poirier [Wed, 5 Aug 2020 20:56:11 +0000 (13:56 -0700)]
Add second case_all test where rb is randint
Tobias Platen [Wed, 5 Aug 2020 18:45:45 +0000 (20:45 +0200)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc
Tobias Platen [Wed, 5 Aug 2020 18:45:40 +0000 (20:45 +0200)]
undo changes that fix unit test, but do not solve anything
Luke Kenneth Casson Leighton [Wed, 5 Aug 2020 18:19:58 +0000 (19:19 +0100)]
rename ibus/dbus (shorten)
Luke Kenneth Casson Leighton [Wed, 5 Aug 2020 18:13:06 +0000 (19:13 +0100)]
clear sel on loadstore
Tobias Platen [Wed, 5 Aug 2020 18:15:09 +0000 (20:15 +0200)]
fix LDSTSplitter
Cole Poirier [Wed, 5 Aug 2020 17:18:22 +0000 (10:18 -0700)]
Remove madd* isns, added madd* isns test TODO
Cole Poirier [Wed, 5 Aug 2020 16:56:09 +0000 (09:56 -0700)]
Merge branch 'master' of git.libre-soc.org:soc
Luke Kenneth Casson Leighton [Wed, 5 Aug 2020 13:31:38 +0000 (14:31 +0100)]
adding bus data width of 64 in litex sim doesnt work
Luke Kenneth Casson Leighton [Wed, 5 Aug 2020 11:32:45 +0000 (12:32 +0100)]
add div test cases into test_issuer.py
Luke Kenneth Casson Leighton [Wed, 5 Aug 2020 09:29:44 +0000 (10:29 +0100)]
add div FSM as default for test_issuer in verilog and ilang gen
Cole Poirier [Wed, 5 Aug 2020 04:42:56 +0000 (21:42 -0700)]
Merge branch 'master' of git.libre-soc.org:soc
Jacob Lifshay [Wed, 5 Aug 2020 03:44:44 +0000 (20:44 -0700)]
Fixed div pipe with FSM
FU unit test was checking the output one cycle too late
See also https://bugs.libre-soc.org/show_bug.cgi?id=449
Cole Poirier [Wed, 5 Aug 2020 00:12:55 +0000 (17:12 -0700)]
Fix pysim deprecation warning
Cole Poirier [Wed, 5 Aug 2020 00:09:09 +0000 (17:09 -0700)]
Add case_all to MUL unit tests, remove duplicate test case_4_mullw_rand
Luke Kenneth Casson Leighton [Tue, 4 Aug 2020 21:57:00 +0000 (22:57 +0100)]
read/set pc outside of FSM so that DMI interface can get at it
Luke Kenneth Casson Leighton [Tue, 4 Aug 2020 18:18:24 +0000 (19:18 +0100)]
swap over byte-reverse if/else in LDSTCompUnit
Luke Kenneth Casson Leighton [Tue, 4 Aug 2020 16:56:12 +0000 (17:56 +0100)]
tracked down byte-reversal in LDST ISACaller and LDSTCompUnit
Luke Kenneth Casson Leighton [Tue, 4 Aug 2020 15:53:59 +0000 (16:53 +0100)]
whitespace after autopep8 messed up
Luke Kenneth Casson Leighton [Tue, 4 Aug 2020 15:42:54 +0000 (16:42 +0100)]
msr and pc moved to "state" in PowerDecode2
Luke Kenneth Casson Leighton [Tue, 4 Aug 2020 15:38:43 +0000 (16:38 +0100)]
whoops must output NIA not PC to debug DMI query in test_issuer
Luke Kenneth Casson Leighton [Tue, 4 Aug 2020 15:04:43 +0000 (16:04 +0100)]
allow instruction to run if initiated whilst "stopped" requested
Luke Kenneth Casson Leighton [Tue, 4 Aug 2020 14:15:52 +0000 (15:15 +0100)]
cycle through INT regs, read and debug in litex sim
Luke Kenneth Casson Leighton [Tue, 4 Aug 2020 12:20:09 +0000 (13:20 +0100)]
add DMI debug interface to libresoc litex sim
Luke Kenneth Casson Leighton [Tue, 4 Aug 2020 12:06:06 +0000 (13:06 +0100)]
single-step and print out PC using DMI in litex sim
Luke Kenneth Casson Leighton [Tue, 4 Aug 2020 11:44:13 +0000 (12:44 +0100)]
get litex sim to kick off a "STEP" via the DMI interface every N cycles
Luke Kenneth Casson Leighton [Tue, 4 Aug 2020 11:07:26 +0000 (12:07 +0100)]
connect up a DMI FSM to litex sim
Luke Kenneth Casson Leighton [Tue, 4 Aug 2020 09:41:45 +0000 (10:41 +0100)]
more remove wildcard imports
Luke Kenneth Casson Leighton [Tue, 4 Aug 2020 09:20:15 +0000 (10:20 +0100)]
do not use wildcard imports
Luke Kenneth Casson Leighton [Tue, 4 Aug 2020 09:16:39 +0000 (10:16 +0100)]
adding litex sim experimentation.
not keen on doing this: adding microwatt.v however it is an important
test and a massive dependency chain needed for generating it
Samuel A. Falvo II [Tue, 4 Aug 2020 02:54:16 +0000 (19:54 -0700)]
Remove XXX; this seems done otherwise.
Luke Kenneth Casson Leighton [Mon, 3 Aug 2020 19:55:51 +0000 (20:55 +0100)]
add quick demo/test of reading DMI reg 9
Luke Kenneth Casson Leighton [Mon, 3 Aug 2020 19:24:03 +0000 (20:24 +0100)]
add extra port for debug read of int regs via DMI
Luke Kenneth Casson Leighton [Mon, 3 Aug 2020 19:19:17 +0000 (20:19 +0100)]
pass state (MSR/PC) around between PowerDecode2, DMI, and TestIssuer
Luke Kenneth Casson Leighton [Mon, 3 Aug 2020 19:08:49 +0000 (20:08 +0100)]
https://bugs.libre-soc.org/show_bug.cgi?id=446
Revert "LDSTSplitter: report exception"
This reverts commit
16f3cca9062314475a9039c96ffa1bc97122a408.
Luke Kenneth Casson Leighton [Mon, 3 Aug 2020 19:04:56 +0000 (20:04 +0100)]
use new soc.config.state CoreState class in DMI and test_issuer
Tobias Platen [Mon, 3 Aug 2020 18:37:47 +0000 (20:37 +0200)]
LDSTSplitter: report exception
Tobias Platen [Mon, 3 Aug 2020 18:06:25 +0000 (20:06 +0200)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc
Tobias Platen [Mon, 3 Aug 2020 18:06:15 +0000 (20:06 +0200)]
TstDataMerger2
Luke Kenneth Casson Leighton [Mon, 3 Aug 2020 17:02:52 +0000 (18:02 +0100)]
change over to DMI debug start/stop interface
Luke Kenneth Casson Leighton [Mon, 3 Aug 2020 17:02:13 +0000 (18:02 +0100)]
move debug to record
Samuel A. Falvo II [Mon, 3 Aug 2020 15:17:55 +0000 (08:17 -0700)]
WIP: check MB > ME and select mask appropriately
Luke Kenneth Casson Leighton [Sun, 2 Aug 2020 15:21:56 +0000 (16:21 +0100)]
convert microwatt core_debug.vhdl to nmigen
Luke Kenneth Casson Leighton [Sun, 2 Aug 2020 09:16:18 +0000 (10:16 +0100)]
add debug dir
Luke Kenneth Casson Leighton [Sat, 1 Aug 2020 13:00:00 +0000 (14:00 +0100)]
add quick test of litex bios IMM64 macro
Luke Kenneth Casson Leighton [Sat, 1 Aug 2020 11:05:07 +0000 (12:05 +0100)]
add rlwnm test showing that shift rot OP_RLC proof is incorrect.
using same values as inputs from the proof
Luke Kenneth Casson Leighton [Sat, 1 Aug 2020 10:24:25 +0000 (11:24 +0100)]
line-length / whitespace
Luke Kenneth Casson Leighton [Sat, 1 Aug 2020 09:49:08 +0000 (10:49 +0100)]
expand out for-loop setting up input record subset
this to help in formal proof shiftrot analysis
Luke Kenneth Casson Leighton [Fri, 31 Jul 2020 16:52:11 +0000 (17:52 +0100)]
reorg DecodeB in power_decoder2.py to sign-extend immediates
Luke Kenneth Casson Leighton [Fri, 31 Jul 2020 16:31:21 +0000 (17:31 +0100)]
add more instructions to litex trampoline test (not tested)
Luke Kenneth Casson Leighton [Fri, 31 Jul 2020 16:30:56 +0000 (17:30 +0100)]
restrict external port list further in test_issuer
Luke Kenneth Casson Leighton [Fri, 31 Jul 2020 16:30:25 +0000 (17:30 +0100)]
missed go_i/rel_o rename
Samuel A. Falvo II [Fri, 31 Jul 2020 16:53:41 +0000 (09:53 -0700)]
WIP: more debugging signals for inspection
Samuel A. Falvo II [Thu, 30 Jul 2020 23:18:49 +0000 (16:18 -0700)]
WIP: rlwinm/rlwnm/rlwimi-type proofs
Been trying to wittle away at this for several days now, without luck.
What am I missing?!
Tobias Platen [Thu, 30 Jul 2020 17:40:09 +0000 (19:40 +0200)]
begin work on TestCase for two DataMergers/Cache
Tobias Platen [Thu, 30 Jul 2020 16:57:46 +0000 (18:57 +0200)]
add CacheRecord
Luke Kenneth Casson Leighton [Thu, 30 Jul 2020 14:12:05 +0000 (15:12 +0100)]
core_start/stop/endian were inverted (output)
Luke Kenneth Casson Leighton [Thu, 30 Jul 2020 12:27:55 +0000 (13:27 +0100)]
ha! have to explicitly specify the ports when writing out to ilang or verilog
this gives unused signals that default to a non-zero value to inherently
set by default to that value.
exposing them externally via ports makes setting them the *users*
Luke Kenneth Casson Leighton [Thu, 30 Jul 2020 12:21:43 +0000 (13:21 +0100)]
add trampoline test from litex
Luke Kenneth Casson Leighton [Thu, 30 Jul 2020 12:19:07 +0000 (13:19 +0100)]
set sel line in minerva instruction fetch
Luke Kenneth Casson Leighton [Thu, 30 Jul 2020 09:39:43 +0000 (10:39 +0100)]
ha! found source of XICS test bug: wishbone stb was being left HI
for more than one cycle in the *unit* test, thereby putting spurious
data onto the bus and corrupting transactions
Luke Kenneth Casson Leighton [Wed, 29 Jul 2020 17:48:14 +0000 (18:48 +0100)]
more exploratory testing of XICS, joining ICP and ICS together
Tobias Platen [Wed, 29 Jul 2020 16:55:54 +0000 (18:55 +0200)]
modified LDSTSplitter to conform to PortInterface
Luke Kenneth Casson Leighton [Wed, 29 Jul 2020 16:22:29 +0000 (17:22 +0100)]
forgot to rename ad/st in LDSTCompUnitRecord
Luke Kenneth Casson Leighton [Wed, 29 Jul 2020 15:19:08 +0000 (16:19 +0100)]
bit of a big change: add prefixes "cu_" to all CompUnit management signals
also change go/rel to go_i and rel_o at the same time
Luke Kenneth Casson Leighton [Wed, 29 Jul 2020 13:23:18 +0000 (14:23 +0100)]
start on test joining XICS ICS to ICP
Luke Kenneth Casson Leighton [Wed, 29 Jul 2020 13:08:32 +0000 (14:08 +0100)]
tidyup XICS, identify (potential?) bug?