Luke Kenneth Casson Leighton [Sat, 9 May 2020 14:06:02 +0000 (15:06 +0100)]
comment where ALUIntermediateData to go
Luke Kenneth Casson Leighton [Sat, 9 May 2020 14:04:55 +0000 (15:04 +0100)]
TODO on AluIntermediateData
Luke Kenneth Casson Leighton [Sat, 9 May 2020 13:59:30 +0000 (14:59 +0100)]
missing sticky-overflow pass-through from middle stage
Luke Kenneth Casson Leighton [Sat, 9 May 2020 13:56:16 +0000 (14:56 +0100)]
pass through sticky-overflow
Luke Kenneth Casson Leighton [Sat, 9 May 2020 13:56:02 +0000 (14:56 +0100)]
remove unneeded class
Luke Kenneth Casson Leighton [Sat, 9 May 2020 13:54:34 +0000 (14:54 +0100)]
clarifying comments
Michael Nolan [Sat, 9 May 2020 13:19:26 +0000 (09:19 -0400)]
Minor cleanup
Luke Kenneth Casson Leighton [Sat, 9 May 2020 11:18:11 +0000 (12:18 +0100)]
preliminary test for LD/ST "update" mode working
Luke Kenneth Casson Leighton [Sat, 9 May 2020 10:58:54 +0000 (11:58 +0100)]
document PowerOp
Luke Kenneth Casson Leighton [Fri, 8 May 2020 23:01:22 +0000 (00:01 +0100)]
add comments
Luke Kenneth Casson Leighton [Fri, 8 May 2020 23:01:12 +0000 (00:01 +0100)]
add ALUFirstInputData
Luke Kenneth Casson Leighton [Fri, 8 May 2020 21:29:55 +0000 (22:29 +0100)]
send address to memory only for one cycle and acknowledge LD immediately
in test-L0CacheBuffer
Luke Kenneth Casson Leighton [Fri, 8 May 2020 21:13:51 +0000 (22:13 +0100)]
experimenting
Luke Kenneth Casson Leighton [Fri, 8 May 2020 20:54:19 +0000 (21:54 +0100)]
working indexed version of LD/ST CompUnit
Luke Kenneth Casson Leighton [Fri, 8 May 2020 20:45:42 +0000 (21:45 +0100)]
hmmm i think LD/ST Comp Unit might actually be working...
Michael Nolan [Fri, 8 May 2020 20:35:40 +0000 (16:35 -0400)]
Oops, forgot pipeline.py
Michael Nolan [Fri, 8 May 2020 20:34:57 +0000 (16:34 -0400)]
Add tests for immediates, add subf to tests
Michael Nolan [Fri, 8 May 2020 20:11:41 +0000 (16:11 -0400)]
Add comments about the purpose of each alu stage
Michael Nolan [Fri, 8 May 2020 19:55:26 +0000 (15:55 -0400)]
Add test for alu against simulator
Michael Nolan [Fri, 8 May 2020 18:59:45 +0000 (14:59 -0400)]
Add assertions for output stage cr0
Michael Nolan [Fri, 8 May 2020 18:51:58 +0000 (14:51 -0400)]
Add output stage
Michael Nolan [Fri, 8 May 2020 17:56:37 +0000 (13:56 -0400)]
Add and or and xor to main_stage
Michael Nolan [Fri, 8 May 2020 17:52:30 +0000 (13:52 -0400)]
Add carry in and out
Michael Nolan [Fri, 8 May 2020 17:49:27 +0000 (13:49 -0400)]
Have input_stage set the b operand to imm_data if it is valid
Michael Nolan [Fri, 8 May 2020 17:32:35 +0000 (13:32 -0400)]
Add extra bits (carry, overflow, etc) to input and output structs
Michael Nolan [Fri, 8 May 2020 17:23:09 +0000 (13:23 -0400)]
Begin adding main ALU stage
Michael Nolan [Fri, 8 May 2020 16:35:51 +0000 (12:35 -0400)]
Convert alu to use the op in ctx
Michael Nolan [Fri, 8 May 2020 15:56:09 +0000 (11:56 -0400)]
Add FPPipeContext to alu pipe_data
Luke Kenneth Casson Leighton [Fri, 8 May 2020 15:31:10 +0000 (16:31 +0100)]
almost got LD/ST CompUnit working
Luke Kenneth Casson Leighton [Fri, 8 May 2020 12:16:07 +0000 (13:16 +0100)]
prototype LD/ST L0 cache/buffer was bouncing address-acknowledgement up
and down. clear the latch during the "reset" phase and it works now
Michael Nolan [Fri, 8 May 2020 15:09:40 +0000 (11:09 -0400)]
Add handling of A inversion and B input
Michael Nolan [Fri, 8 May 2020 15:03:34 +0000 (11:03 -0400)]
Begin adding input stage of alu
Michael Nolan [Fri, 8 May 2020 14:43:32 +0000 (10:43 -0400)]
Add pipe data for ALU pipeline
Michael Nolan [Fri, 8 May 2020 14:41:23 +0000 (10:41 -0400)]
Update gitignore in isa dir
Michael Nolan [Fri, 8 May 2020 14:40:06 +0000 (10:40 -0400)]
Separate out ALU Input record from alu_hier.py
Michael Nolan [Thu, 7 May 2020 19:54:32 +0000 (15:54 -0400)]
Add test_branch_loop_ctr
Michael Nolan [Thu, 7 May 2020 19:41:06 +0000 (15:41 -0400)]
Add tests for conditional branches
Luke Kenneth Casson Leighton [Thu, 7 May 2020 18:35:32 +0000 (19:35 +0100)]
move unused simulator code out the way
Luke Kenneth Casson Leighton [Thu, 7 May 2020 18:34:56 +0000 (19:34 +0100)]
testing LD without ST
Michael Nolan [Thu, 7 May 2020 18:21:07 +0000 (14:21 -0400)]
Ooops, forgot comparefixed.patch
Michael Nolan [Thu, 7 May 2020 18:18:32 +0000 (14:18 -0400)]
Get test_cmp working
Michael Nolan [Thu, 7 May 2020 18:13:24 +0000 (14:13 -0400)]
Fix test_mtcrf. Test has been verified against qemu
Michael Nolan [Thu, 7 May 2020 17:44:33 +0000 (13:44 -0400)]
Make FieldSelectableInt accept slices for set and get
Michael Nolan [Thu, 7 May 2020 15:40:31 +0000 (11:40 -0400)]
Add handling of add with comparison
Michael Nolan [Thu, 7 May 2020 15:17:48 +0000 (11:17 -0400)]
Fix bug with comparisons in selectable_int.py
Michael Nolan [Thu, 7 May 2020 14:37:20 +0000 (10:37 -0400)]
Add test_mfcr
Luke Kenneth Casson Leighton [Thu, 7 May 2020 14:20:40 +0000 (15:20 +0100)]
continuing debugging of LD/ST CompUnit FSM and unit test
Luke Kenneth Casson Leighton [Thu, 7 May 2020 12:48:33 +0000 (13:48 +0100)]
partially-debugged ld/st comp unit using new PortInterface
Michael Nolan [Wed, 6 May 2020 18:23:20 +0000 (14:23 -0400)]
Re-enable test_mtcrf
Michael Nolan [Wed, 6 May 2020 18:21:40 +0000 (14:21 -0400)]
Add length helper for getting length of a selectable int
Michael Nolan [Wed, 6 May 2020 18:19:06 +0000 (14:19 -0400)]
Add helper functions to replace direct comparison in generated code
Luke Kenneth Casson Leighton [Wed, 6 May 2020 17:08:23 +0000 (18:08 +0100)]
no syntax errors in LDSTCompUnit multi version
Luke Kenneth Casson Leighton [Wed, 6 May 2020 16:46:30 +0000 (17:46 +0100)]
almost complete LD/ST CompUnit, nearing testing
Michael Nolan [Wed, 6 May 2020 15:44:35 +0000 (11:44 -0400)]
Look up spr length from spr table
Michael Nolan [Wed, 6 May 2020 15:42:23 +0000 (11:42 -0400)]
Add dict of spr properties to power_enums
Michael Nolan [Wed, 6 May 2020 15:35:47 +0000 (11:35 -0400)]
Implement bctr and mtspr
Michael Nolan [Wed, 6 May 2020 15:05:59 +0000 (11:05 -0400)]
Properly implement LR and CTR
Michael Nolan [Wed, 6 May 2020 14:43:27 +0000 (10:43 -0400)]
Add ability to patch generated isa files
Michael Nolan [Wed, 6 May 2020 14:32:24 +0000 (10:32 -0400)]
Sorta kinda working bl and blr - need to properly implement lr
Luke Kenneth Casson Leighton [Wed, 6 May 2020 12:34:28 +0000 (13:34 +0100)]
remove unneeded minerva code
Luke Kenneth Casson Leighton [Wed, 6 May 2020 12:26:24 +0000 (13:26 +0100)]
mention need for DualPortSplitter class
Luke Kenneth Casson Leighton [Wed, 6 May 2020 10:55:45 +0000 (11:55 +0100)]
more connecting signals for LDSTCompUnit according to diagram
Jacob Lifshay [Wed, 6 May 2020 00:55:05 +0000 (17:55 -0700)]
update Makefile to include required build steps
Michael Nolan [Tue, 5 May 2020 19:58:34 +0000 (15:58 -0400)]
Add rudimentary branch capability
Michael Nolan [Tue, 5 May 2020 18:40:46 +0000 (14:40 -0400)]
Fix broken test_decoder_gas
Luke Kenneth Casson Leighton [Tue, 5 May 2020 16:26:52 +0000 (17:26 +0100)]
begin connecting up signals for LDSTCompUnit
Yehowshua Immanuel [Tue, 5 May 2020 14:21:10 +0000 (10:21 -0400)]
Merge branch 'master' of git.libre-riscv.org:soc
Removed named tuple duplicate - merging with Lukes commit.
Yehowshua Immanuel [Tue, 5 May 2020 14:20:57 +0000 (10:20 -0400)]
Git rid of named tuple imported twice
Luke Kenneth Casson Leighton [Tue, 5 May 2020 14:12:57 +0000 (15:12 +0100)]
new version of LDSTCompUnit
Yehowshua Immanuel [Tue, 5 May 2020 14:06:40 +0000 (10:06 -0400)]
Link to documentation in README.md
Luke Kenneth Casson Leighton [Mon, 4 May 2020 19:53:13 +0000 (20:53 +0100)]
comments
Luke Kenneth Casson Leighton [Mon, 4 May 2020 19:49:02 +0000 (20:49 +0100)]
take out wait for busy in L0BufferCache tests
Luke Kenneth Casson Leighton [Mon, 4 May 2020 19:41:53 +0000 (20:41 +0100)]
whitespace cleanup
Luke Kenneth Casson Leighton [Mon, 4 May 2020 19:41:05 +0000 (20:41 +0100)]
bit of a mess, but functional. unit test passes on "basic" L0CacheBuffer
Luke Kenneth Casson Leighton [Mon, 4 May 2020 17:59:51 +0000 (18:59 +0100)]
hmmm trying to get st to acknowledge properly
Luke Kenneth Casson Leighton [Mon, 4 May 2020 17:27:23 +0000 (18:27 +0100)]
add links to bugreport and to memory/cache wiki page
Luke Kenneth Casson Leighton [Mon, 4 May 2020 17:21:16 +0000 (18:21 +0100)]
L0 cache/buffer first unit test, working except for one niggle
Yehowshua Immanuel [Mon, 4 May 2020 16:39:13 +0000 (12:39 -0400)]
Remove request since no longer https fetches from wiki
Tobias Platen [Mon, 4 May 2020 14:26:22 +0000 (16:26 +0200)]
update cr0 when rc is set
Luke Kenneth Casson Leighton [Mon, 4 May 2020 13:48:18 +0000 (14:48 +0100)]
first cut at "basic" L0 Cache/Buffer (untested), only sends one LD/ST through
at a time. demonstrates the LDST PortInterface
Luke Kenneth Casson Leighton [Mon, 4 May 2020 10:18:12 +0000 (11:18 +0100)]
document PortInterface, start on "dummy" L0CacheBuffer
Luke Kenneth Casson Leighton [Mon, 4 May 2020 09:48:21 +0000 (10:48 +0100)]
whitespace
Luke Kenneth Casson Leighton [Mon, 4 May 2020 09:31:15 +0000 (10:31 +0100)]
better comments on rd/wr pending
Luke Kenneth Casson Leighton [Sun, 3 May 2020 10:52:23 +0000 (11:52 +0100)]
move unused out of soc directory
Luke Kenneth Casson Leighton [Sun, 3 May 2020 10:32:12 +0000 (11:32 +0100)]
add comments to power decoder
Luke Kenneth Casson Leighton [Sun, 3 May 2020 09:49:14 +0000 (10:49 +0100)]
move TLB and iommu to unused directory
Michael Nolan [Sat, 2 May 2020 19:27:34 +0000 (15:27 -0400)]
Read decoder tables from wiki submodule instead of web
Luke Kenneth Casson Leighton [Mon, 27 Apr 2020 11:49:49 +0000 (12:49 +0100)]
add LDST PortInterface class
Luke Kenneth Casson Leighton [Mon, 27 Apr 2020 11:49:11 +0000 (12:49 +0100)]
add CompLDSTOpSubset, contains subset of decode instruction for LD/ST
Luke Kenneth Casson Leighton [Mon, 27 Apr 2020 11:45:54 +0000 (12:45 +0100)]
update signal in DecodeToExecute1Type is "LD/ST performs update"
Luke Kenneth Casson Leighton [Fri, 24 Apr 2020 12:02:46 +0000 (13:02 +0100)]
experimenting with ld/st comp unit
Luke Kenneth Casson Leighton [Fri, 24 Apr 2020 08:55:56 +0000 (09:55 +0100)]
remove out-of-date comments
Luke Kenneth Casson Leighton [Thu, 23 Apr 2020 17:15:17 +0000 (18:15 +0100)]
comment req_done
Luke Kenneth Casson Leighton [Thu, 23 Apr 2020 16:48:50 +0000 (17:48 +0100)]
hair-raising series of half-way-house changes which gets a mix of add/addi
working
Luke Kenneth Casson Leighton [Thu, 23 Apr 2020 14:17:25 +0000 (15:17 +0100)]
start using records in score6600
Luke Kenneth Casson Leighton [Thu, 23 Apr 2020 13:54:55 +0000 (14:54 +0100)]
rename MultiCompUnit
Luke Kenneth Casson Leighton [Thu, 23 Apr 2020 13:53:54 +0000 (14:53 +0100)]
use go/rel Record in ldstcomp
Luke Kenneth Casson Leighton [Wed, 22 Apr 2020 15:56:22 +0000 (16:56 +0100)]
fix request-done in compalu_multi
Luke Kenneth Casson Leighton [Wed, 22 Apr 2020 14:55:28 +0000 (15:55 +0100)]
LDSTCompUnit converted, no need to special-case
Luke Kenneth Casson Leighton [Wed, 22 Apr 2020 14:54:54 +0000 (15:54 +0100)]
convert CompALU to Record in/out