Luke Kenneth Casson Leighton [Wed, 24 Mar 2021 09:26:36 +0000 (09:26 +0000)]
add --disable-svp64 to litex sim build
Tobias Platen [Tue, 23 Mar 2021 20:51:03 +0000 (21:51 +0100)]
make addrshift human readable
Tobias Platen [Tue, 23 Mar 2021 20:09:58 +0000 (21:09 +0100)]
add addrshift function (based on microwatt)
Luke Kenneth Casson Leighton [Mon, 22 Mar 2021 23:51:06 +0000 (23:51 +0000)]
do not set sv_changed
Tobias Platen [Mon, 22 Mar 2021 20:21:28 +0000 (21:21 +0100)]
testcase for _get_pgtable_addr
Luke Kenneth Casson Leighton [Mon, 22 Mar 2021 17:33:14 +0000 (17:33 +0000)]
read predicate mask from correct point in SVP64Asm
Luke Kenneth Casson Leighton [Mon, 22 Mar 2021 17:30:58 +0000 (17:30 +0000)]
add SVP64Asm option for "m=" to set both src and dest mask
Luke Kenneth Casson Leighton [Mon, 22 Mar 2021 17:14:25 +0000 (17:14 +0000)]
add very small dff sram variant (no 4k SRAMs)
Cesar Strauss [Mon, 22 Mar 2021 11:46:22 +0000 (08:46 -0300)]
Add test cases for integer VCOMPRESS and VEXPAND
In these cases, either srcmask or destmask is "always", so the
corresponding mask should be all ones, instead of being fetched from the
register file.
Luke Kenneth Casson Leighton [Mon, 22 Mar 2021 12:40:35 +0000 (12:40 +0000)]
make sure non-svp64-mode works
Luke Kenneth Casson Leighton [Mon, 22 Mar 2021 12:12:06 +0000 (12:12 +0000)]
have get_predint return indicator that mask is all 1s
Cesar Strauss [Mon, 22 Mar 2021 10:34:09 +0000 (07:34 -0300)]
Skip fetching integer predicate mask when register number is zero
Cesar Strauss [Mon, 22 Mar 2021 00:52:47 +0000 (21:52 -0300)]
Add traces for the new FSM and integer predicate decoding
Cesar Strauss [Mon, 22 Mar 2021 00:26:11 +0000 (21:26 -0300)]
Decode and fetch integer predicate registers
Cesar Strauss [Sun, 21 Mar 2021 21:41:06 +0000 (18:41 -0300)]
Fix typo
Cesar Strauss [Sun, 21 Mar 2021 21:14:54 +0000 (18:14 -0300)]
Add unique name to decoded predication signals
Cesar Strauss [Sun, 21 Mar 2021 20:53:21 +0000 (17:53 -0300)]
Revert removal of *.value from Enums
Cesar Strauss [Sun, 21 Mar 2021 18:03:28 +0000 (15:03 -0300)]
Fix syntax
Luke Kenneth Casson Leighton [Sun, 21 Mar 2021 18:03:29 +0000 (18:03 +0000)]
more TODO comments
Luke Kenneth Casson Leighton [Sun, 21 Mar 2021 14:48:01 +0000 (14:48 +0000)]
add for-loop pseudocode for CR predicate mask reading
Luke Kenneth Casson Leighton [Sun, 21 Mar 2021 13:25:26 +0000 (13:25 +0000)]
code comments in TestIssuer
Luke Kenneth Casson Leighton [Sun, 21 Mar 2021 13:18:30 +0000 (13:18 +0000)]
adjust syntax of SVP64 predicate test cas
Luke Kenneth Casson Leighton [Sun, 21 Mar 2021 13:17:26 +0000 (13:17 +0000)]
naah. back to "sv." syntax for SVP64 assembly
Cesar Strauss [Sun, 21 Mar 2021 13:02:19 +0000 (10:02 -0300)]
Start work on the predicate fetch FSM
After an instruction arrives, it will decode the SVP64 mask part
and will fetch the masks from the register files.
At the moment, it just returns the all ones mask.
The Issue FSM calls it, after receiving an instruction from Fetch, and
before entering execution vector loop.
Cesar Strauss [Sun, 21 Mar 2021 11:44:09 +0000 (08:44 -0300)]
Add predication test case, initially disabled
Directly derived from a test in test_caller_svp64_predication.py
The goal is to incrementally develop the TestIssuer FSMs, until it passes.
Luke Kenneth Casson Leighton [Sun, 21 Mar 2021 11:07:59 +0000 (11:07 +0000)]
add override for build commands powerpc64-linux-gnu-{ENVVAR}
Luke Kenneth Casson Leighton [Sun, 21 Mar 2021 10:55:01 +0000 (10:55 +0000)]
enable -mregnames in assembly syntax for unit tests
Luke Kenneth Casson Leighton [Sat, 20 Mar 2021 18:58:54 +0000 (18:58 +0000)]
more pseudocode in TestIssuer
Luke Kenneth Casson Leighton [Sat, 20 Mar 2021 18:51:41 +0000 (18:51 +0000)]
move radixmmu to unit test format
Luke Kenneth Casson Leighton [Sat, 20 Mar 2021 18:29:01 +0000 (18:29 +0000)]
add harmless code and commented-out pseudocode for predication in TestIssuer
Luke Kenneth Casson Leighton [Sat, 20 Mar 2021 11:22:23 +0000 (11:22 +0000)]
sort out predicate zeroing in ISACaller
Luke Kenneth Casson Leighton [Sat, 20 Mar 2021 00:12:06 +0000 (00:12 +0000)]
attempting to add src/dest-zeroing to ISACaller
Luke Kenneth Casson Leighton [Fri, 19 Mar 2021 23:40:38 +0000 (23:40 +0000)]
more comments for TestIssuer when adding predication
Tobias Platen [Fri, 19 Mar 2021 19:33:22 +0000 (20:33 +0100)]
testcase for _get_pgtable_addr
Luke Kenneth Casson Leighton [Fri, 19 Mar 2021 19:12:11 +0000 (19:12 +0000)]
decode predicate src/dest zeroing in SVP64RMModeDecode
Luke Kenneth Casson Leighton [Fri, 19 Mar 2021 14:45:01 +0000 (14:45 +0000)]
comments for TestIssuer get_predint and get_predcr
Luke Kenneth Casson Leighton [Fri, 19 Mar 2021 14:37:17 +0000 (14:37 +0000)]
add more pieces of predication reading puzzle to TestIssuer
Luke Kenneth Casson Leighton [Fri, 19 Mar 2021 14:17:00 +0000 (14:17 +0000)]
cleanup TestIssuer (comments)
Luke Kenneth Casson Leighton [Fri, 19 Mar 2021 14:14:10 +0000 (14:14 +0000)]
spelling
Luke Kenneth Casson Leighton [Fri, 19 Mar 2021 14:12:44 +0000 (14:12 +0000)]
code-shuffle in TestIssuer, split out setting up peripherals
Luke Kenneth Casson Leighton [Fri, 19 Mar 2021 14:04:23 +0000 (14:04 +0000)]
move duplicated code to a function in TestIssuer
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 21:26:04 +0000 (21:26 +0000)]
more hint/comments
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 21:23:53 +0000 (21:23 +0000)]
comments / code-shuffle
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 21:16:21 +0000 (21:16 +0000)]
update TestIssuer comments
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 20:02:32 +0000 (20:02 +0000)]
add comments on most likely place to put predicate mask read-firing
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 19:15:38 +0000 (19:15 +0000)]
comments TestIssuer, add a stub FSM
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 18:45:38 +0000 (18:45 +0000)]
add MSR PR read in RADIXMMU ISACaller
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 18:34:07 +0000 (18:34 +0000)]
re-add auto-generated file simplev.py to gitignore
https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=
d3767842a2f8f66f9e3de882a36592bfa3d344b8;hp=
3f8a17ca49a1cc9636b85b41b84a0a88476cbdf8
Jacob Lifshay [Thu, 18 Mar 2021 16:42:45 +0000 (09:42 -0700)]
re-add nmigen-type-annotations with libre-soc url
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 14:42:40 +0000 (14:42 +0000)]
experiment in radixmmu with returning addr_next (and some error messages)
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 12:24:54 +0000 (12:24 +0000)]
add sv_out2 to PowerDecode and PowerDecoder2
used for 2nd write (currently LD/ST update only)
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 12:15:00 +0000 (12:15 +0000)]
cross-reference to bug #619
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 12:13:20 +0000 (12:13 +0000)]
add auto-generation of out2 column in SVP64RM
needed for PowerDecoder2 as well as microwatt svp64 vhdl generation
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 11:48:14 +0000 (11:48 +0000)]
remove nmigen-type-annotations temporarily
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 11:47:07 +0000 (11:47 +0000)]
remove nmigen-type-annotations temporarily
Luke Kenneth Casson Leighton [Thu, 18 Mar 2021 11:22:05 +0000 (11:22 +0000)]
add option to move RS in CSV file reading, for compatibility with microwatt
decode1.vhdl;
Luke Kenneth Casson Leighton [Wed, 17 Mar 2021 22:33:15 +0000 (22:33 +0000)]
correct comments
Luke Kenneth Casson Leighton [Wed, 17 Mar 2021 22:29:07 +0000 (22:29 +0000)]
re-enable SVP64 ISACaller predicate tests
Luke Kenneth Casson Leighton [Wed, 17 Mar 2021 22:25:21 +0000 (22:25 +0000)]
add ascii graphic for extsw svp64 operation
Luke Kenneth Casson Leighton [Wed, 17 Mar 2021 22:21:12 +0000 (22:21 +0000)]
add more explanatory comments
Luke Kenneth Casson Leighton [Wed, 17 Mar 2021 22:15:58 +0000 (22:15 +0000)]
add twin-predicated extsw SVP64 ISACaller unit test
Luke Kenneth Casson Leighton [Wed, 17 Mar 2021 21:29:49 +0000 (21:29 +0000)]
add SVP64 dststep incrementing in PowerDecoder2, Testissuer and ISACaller
Luke Kenneth Casson Leighton [Wed, 17 Mar 2021 20:40:49 +0000 (20:40 +0000)]
add CR-based predication to ISACaller
Tobias Platen [Wed, 17 Mar 2021 19:13:40 +0000 (20:13 +0100)]
cleanup raduxmmu._walk_tree
Tobias Platen [Wed, 17 Mar 2021 18:59:12 +0000 (19:59 +0100)]
create iterative mmu lookup loop
Luke Kenneth Casson Leighton [Wed, 17 Mar 2021 15:20:02 +0000 (15:20 +0000)]
add SVP64 INT-style predication to ISACaller
Luke Kenneth Casson Leighton [Wed, 17 Mar 2021 14:13:02 +0000 (14:13 +0000)]
add predication SVP64 unit test
Luke Kenneth Casson Leighton [Wed, 17 Mar 2021 13:21:25 +0000 (13:21 +0000)]
add predication read ports (CR and INT)
Luke Kenneth Casson Leighton [Wed, 17 Mar 2021 13:16:24 +0000 (13:16 +0000)]
whoops shift has to be done at same bitwidth
Luke Kenneth Casson Leighton [Wed, 17 Mar 2021 13:14:07 +0000 (13:14 +0000)]
split out new_lookup function
Luke Kenneth Casson Leighton [Wed, 17 Mar 2021 13:00:28 +0000 (13:00 +0000)]
link up SVP64 RM Mode decoding into PowerDecoder2
Luke Kenneth Casson Leighton [Wed, 17 Mar 2021 12:46:54 +0000 (12:46 +0000)]
add priv and mode to RADIXMMU
Luke Kenneth Casson Leighton [Wed, 17 Mar 2021 12:34:04 +0000 (12:34 +0000)]
add instr_fetch mode to ISACaller Mem and RADIXMMU
Luke Kenneth Casson Leighton [Wed, 17 Mar 2021 12:22:44 +0000 (12:22 +0000)]
whitespace
Luke Kenneth Casson Leighton [Wed, 17 Mar 2021 12:19:06 +0000 (12:19 +0000)]
add in SVP64 RM Mode decoder
Tobias Platen [Tue, 16 Mar 2021 18:49:20 +0000 (19:49 +0100)]
radixmmu: detect badtree
Tobias Platen [Tue, 16 Mar 2021 17:35:35 +0000 (18:35 +0100)]
add valid, leaf to loop
Cesar Strauss [Tue, 16 Mar 2021 10:55:48 +0000 (07:55 -0300)]
Use symbolic values for subfields and bits
Cesar Strauss [Tue, 16 Mar 2021 10:48:05 +0000 (07:48 -0300)]
Add subfield and bit definitions for the SVP64 RM mode field
Cesar Strauss [Tue, 16 Mar 2021 00:12:11 +0000 (21:12 -0300)]
Define and initialise the mode variable, to be used later on
Cesar Strauss [Tue, 16 Mar 2021 00:02:28 +0000 (21:02 -0300)]
Rename class so it does not clash with the enum
Cesar Strauss [Mon, 15 Mar 2021 22:33:34 +0000 (19:33 -0300)]
Fix import
Tobias Platen [Mon, 15 Mar 2021 18:49:44 +0000 (19:49 +0100)]
add rpte bitfields valid and leaf
Luke Kenneth Casson Leighton [Sun, 14 Mar 2021 14:55:28 +0000 (14:55 +0000)]
remove "sv." and replace with "sv" in all SVP64Asm
Luke Kenneth Casson Leighton [Sun, 14 Mar 2021 14:54:45 +0000 (14:54 +0000)]
remove "sv." and replace with "sv" in all SVP64Asm
Cesar Strauss [Sun, 14 Mar 2021 13:46:08 +0000 (10:46 -0300)]
Activate the VL==0 loop with any SVP64 prefix whatsoever
Besides agreeing with documentation, this will ease doing the VL==0
loop entirely on the Fetch FSM, since no opcode decoding is needed.
Luke Kenneth Casson Leighton [Sat, 13 Mar 2021 17:07:09 +0000 (17:07 +0000)]
add setvl unit test assertions, add 2nd test
Luke Kenneth Casson Leighton [Sat, 13 Mar 2021 16:10:02 +0000 (16:10 +0000)]
get first revision setvl operational in ISACaller
Luke Kenneth Casson Leighton [Sat, 13 Mar 2021 13:35:30 +0000 (13:35 +0000)]
add setvl-to-long converter in SVP64Asm (sigh)
Luke Kenneth Casson Leighton [Sat, 13 Mar 2021 12:22:16 +0000 (12:22 +0000)]
add setvl unit test
Luke Kenneth Casson Leighton [Sat, 13 Mar 2021 12:20:02 +0000 (12:20 +0000)]
update submodule to include simplev setvl
Luke Kenneth Casson Leighton [Sat, 13 Mar 2021 11:33:53 +0000 (11:33 +0000)]
include SVSTATE in namespace, passing to ISACaller
Jacob Lifshay [Fri, 12 Mar 2021 22:55:24 +0000 (14:55 -0800)]
update submodule
Jacob Lifshay [Fri, 12 Mar 2021 22:52:16 +0000 (14:52 -0800)]
add setvl to decoder
Jacob Lifshay [Fri, 12 Mar 2021 22:50:01 +0000 (14:50 -0800)]
autoformat code
Luke Kenneth Casson Leighton [Fri, 12 Mar 2021 21:50:44 +0000 (21:50 +0000)]
add OP_SETVL to MicrOp in power_enums.py
Luke Kenneth Casson Leighton [Fri, 12 Mar 2021 21:41:57 +0000 (21:41 +0000)]
add ability to set and distinguish RT=0 (RT_OR_ZERO) to OutSel enum
Luke Kenneth Casson Leighton [Fri, 12 Mar 2021 15:02:06 +0000 (15:02 +0000)]
use PowerDecoder2.loop_continue instead of no_out_vec
Luke Kenneth Casson Leighton [Fri, 12 Mar 2021 14:17:17 +0000 (14:17 +0000)]
remove old code
Luke Kenneth Casson Leighton [Fri, 12 Mar 2021 14:16:10 +0000 (14:16 +0000)]
remove old code