Luke Kenneth Casson Leighton [Sun, 14 Nov 2021 19:40:51 +0000 (19:40 +0000)]
getting microtest to work again (adapting json output)
Luke Kenneth Casson Leighton [Sun, 14 Nov 2021 19:22:58 +0000 (19:22 +0000)]
move json creation to separate file
Luke Kenneth Casson Leighton [Sun, 14 Nov 2021 19:19:26 +0000 (19:19 +0000)]
sort out JSON function missing and get mapping working
Luke Kenneth Casson Leighton [Sun, 14 Nov 2021 19:13:19 +0000 (19:13 +0000)]
add missing clock to I2S pinfunction
Luke Kenneth Casson Leighton [Sun, 14 Nov 2021 19:10:56 +0000 (19:10 +0000)]
python2 print conversion
Luke Kenneth Casson Leighton [Sun, 14 Nov 2021 16:48:17 +0000 (16:48 +0000)]
comments
Luke Kenneth Casson Leighton [Sun, 14 Nov 2021 16:45:40 +0000 (16:45 +0000)]
add a few more asserts just to be safe
Luke Kenneth Casson Leighton [Sun, 14 Nov 2021 16:42:33 +0000 (16:42 +0000)]
yargh, hook into PlatformManager.request() so that seamlessly a
duplicate pad manager request can be made, and, further, the ports analysed
in order to hook up the names between pads and core (padlookup)
this is much cleaner than having to allocate all resources in advance
in the constructur
Luke Kenneth Casson Leighton [Sun, 14 Nov 2021 15:25:41 +0000 (15:25 +0000)]
override Platform.add_resources() so as to be able to add
resources to the Boundary Scan pad_mgr
Luke Kenneth Casson Leighton [Sat, 13 Nov 2021 22:33:55 +0000 (22:33 +0000)]
code-morph to drop in a duplicate resource set, for the IO ring
Luke Kenneth Casson Leighton [Sat, 13 Nov 2021 22:10:15 +0000 (22:10 +0000)]
add JTAG module to test example
Luke Kenneth Casson Leighton [Sat, 13 Nov 2021 22:08:06 +0000 (22:08 +0000)]
cleanup jtag.py for demo/test purposes
Luke Kenneth Casson Leighton [Sat, 13 Nov 2021 22:04:48 +0000 (22:04 +0000)]
add first cut of jtag.py (from soc) to be cut down later
Luke Kenneth Casson Leighton [Sat, 13 Nov 2021 20:28:54 +0000 (20:28 +0000)]
add copies of get_input/output/etc to at least put in some prints
Luke Kenneth Casson Leighton [Sat, 13 Nov 2021 20:27:33 +0000 (20:27 +0000)]
add comments and GPIO pads with triplet of Pins i/o/oe
Luke Kenneth Casson Leighton [Sat, 13 Nov 2021 20:01:47 +0000 (20:01 +0000)]
hmmm experimenting with gpio directions
Luke Kenneth Casson Leighton [Sat, 13 Nov 2021 19:45:57 +0000 (19:45 +0000)]
add clock/reset to dummy platform, now sync domain exists
Luke Kenneth Casson Leighton [Sat, 13 Nov 2021 18:31:13 +0000 (18:31 +0000)]
mess about with resources a bit
Luke Kenneth Casson Leighton [Sat, 13 Nov 2021 18:10:02 +0000 (18:10 +0000)]
hooray got the output at least created in build/
Luke Kenneth Casson Leighton [Sat, 13 Nov 2021 18:06:12 +0000 (18:06 +0000)]
tidyup, got testing_stage1.py at least running
Andrey Miroshnikov [Sat, 13 Nov 2021 17:16:42 +0000 (17:16 +0000)]
Added resource function (not working yet)
Andrey Miroshnikov [Sat, 13 Nov 2021 09:23:21 +0000 (09:23 +0000)]
Added platform instantiation (missing import statement though)
Andrey Miroshnikov [Sat, 13 Nov 2021 08:53:23 +0000 (08:53 +0000)]
Adding stage1 test file
Andrey Miroshnikov [Mon, 8 Nov 2021 19:57:24 +0000 (19:57 +0000)]
Cloned create_sv for ngi_router svg scaling
Andrey Miroshnikov [Mon, 8 Nov 2021 19:53:15 +0000 (19:53 +0000)]
Added most of the peripherals, still a few more to add
Andrey Miroshnikov [Mon, 8 Nov 2021 13:53:24 +0000 (13:53 +0000)]
In-progress, re-arranging peripherals
Andrey Miroshnikov [Mon, 8 Nov 2021 11:48:00 +0000 (11:48 +0000)]
In progress of adding peripherals and re-arranging.
Andrey Miroshnikov [Mon, 8 Nov 2021 11:27:48 +0000 (11:27 +0000)]
Added svgwrite lib to readme
Andrey Miroshnikov [Sat, 6 Nov 2021 16:46:52 +0000 (16:46 +0000)]
Adding a USB and LAN datasheet entries
Luke Kenneth Casson Leighton [Sat, 6 Nov 2021 15:51:36 +0000 (15:51 +0000)]
add two RGMII interfaces (random locations), move VSS/VDD on N
Luke Kenneth Casson Leighton [Sat, 6 Nov 2021 15:41:15 +0000 (15:41 +0000)]
drop PLL into top left (NE)
Luke Kenneth Casson Leighton [Sat, 6 Nov 2021 15:37:59 +0000 (15:37 +0000)]
add ngi_router spec
Luke Kenneth Casson Leighton [Sat, 6 Nov 2021 15:37:48 +0000 (15:37 +0000)]
print statements convert to python3
Luke Kenneth Casson Leighton [Sat, 6 Nov 2021 15:33:33 +0000 (15:33 +0000)]
convert to python3
Andrey Miroshnikov [Thu, 4 Nov 2021 23:16:15 +0000 (23:16 +0000)]
Copied ls180 module file into new ngi_router module. Not being imported yet.
Luke Kenneth Casson Leighton [Fri, 11 Jun 2021 17:46:42 +0000 (18:46 +0100)]
update ls180 svg image to include snapshot of GDS-II
Luke Kenneth Casson Leighton [Fri, 11 Jun 2021 15:33:41 +0000 (16:33 +0100)]
add C4M Logo to ls180
Luke Kenneth Casson Leighton [Fri, 11 Jun 2021 15:03:45 +0000 (16:03 +0100)]
include extra pin image and package marking
Luke Kenneth Casson Leighton [Fri, 11 Jun 2021 14:29:12 +0000 (15:29 +0100)]
add outer leads and pack/qfp drawings
Luke Kenneth Casson Leighton [Fri, 11 Jun 2021 13:16:01 +0000 (14:16 +0100)]
add internal-to-external bond number conversion
Luke Kenneth Casson Leighton [Fri, 11 Jun 2021 12:14:39 +0000 (13:14 +0100)]
add internal-to-external bond number conversion
Luke Kenneth Casson Leighton [Fri, 11 Jun 2021 11:02:06 +0000 (12:02 +0100)]
add note on viewing image automatically update
Luke Kenneth Casson Leighton [Thu, 10 Jun 2021 21:28:44 +0000 (22:28 +0100)]
shuffle pinouts... again
Luke Kenneth Casson Leighton [Thu, 10 Jun 2021 21:23:30 +0000 (22:23 +0100)]
update image colours
Luke Kenneth Casson Leighton [Thu, 10 Jun 2021 21:22:30 +0000 (22:22 +0100)]
move image words
Luke Kenneth Casson Leighton [Thu, 10 Jun 2021 21:21:26 +0000 (22:21 +0100)]
update image colours
Luke Kenneth Casson Leighton [Thu, 10 Jun 2021 21:17:53 +0000 (22:17 +0100)]
dont make image if no svgwrite module
Luke Kenneth Casson Leighton [Thu, 10 Jun 2021 21:06:08 +0000 (22:06 +0100)]
add naming and pin-order reverse option
Luke Kenneth Casson Leighton [Thu, 10 Jun 2021 21:05:56 +0000 (22:05 +0100)]
mirror W pins to match coriolis2 pad positions
Luke Kenneth Casson Leighton [Thu, 10 Jun 2021 20:51:57 +0000 (21:51 +0100)]
add SVG generator
Luke Kenneth Casson Leighton [Thu, 10 Jun 2021 11:59:37 +0000 (12:59 +0100)]
swap over S and W to get SDRAM AD* to line up
Luke Kenneth Casson Leighton [Thu, 10 Jun 2021 11:53:30 +0000 (12:53 +0100)]
correction on VSS/VDD internal/external
Luke Kenneth Casson Leighton [Thu, 10 Jun 2021 11:30:50 +0000 (12:30 +0100)]
power shuffle, split SDRAM
Luke Kenneth Casson Leighton [Thu, 10 Jun 2021 10:52:47 +0000 (11:52 +0100)]
moved CLK away from testout
Luke Kenneth Casson Leighton [Thu, 10 Jun 2021 10:50:44 +0000 (11:50 +0100)]
move VCC/VSS inward on NORTH
Luke Kenneth Casson Leighton [Thu, 10 Jun 2021 10:41:17 +0000 (11:41 +0100)]
move PLL around slightly, VCO on east top
Luke Kenneth Casson Leighton [Thu, 10 Jun 2021 10:36:35 +0000 (11:36 +0100)]
renumber power, add support for Analog pad spec
Luke Kenneth Casson Leighton [Wed, 9 Jun 2021 15:07:02 +0000 (16:07 +0100)]
rename sys_clk to sys_pllclk - conflict with litex
Luke Kenneth Casson Leighton [Wed, 9 Jun 2021 11:54:48 +0000 (12:54 +0100)]
pinmux update for ls180
Luke Kenneth Casson Leighton [Sat, 22 May 2021 10:47:23 +0000 (11:47 +0100)]
raise pinmux SYS pincount to 7 to include PLL
Luke Kenneth Casson Leighton [Sat, 24 Apr 2021 20:46:45 +0000 (21:46 +0100)]
argh reorder functions to not be recursively dependent
Luke Kenneth Casson Leighton [Tue, 13 Apr 2021 16:33:12 +0000 (17:33 +0100)]
fix litex name map
Luke Kenneth Casson Leighton [Tue, 13 Apr 2021 16:29:56 +0000 (17:29 +0100)]
fix litex name map
Luke Kenneth Casson Leighton [Tue, 13 Apr 2021 16:25:41 +0000 (17:25 +0100)]
add litex name map
Luke Kenneth Casson Leighton [Tue, 13 Apr 2021 16:21:32 +0000 (17:21 +0100)]
add litex name map
Luke Kenneth Casson Leighton [Tue, 13 Apr 2021 16:02:52 +0000 (17:02 +0100)]
add pin-to-litex json map
Luke Kenneth Casson Leighton [Tue, 13 Apr 2021 14:32:37 +0000 (15:32 +0100)]
update names of PLL connections for ls180
Luke Kenneth Casson Leighton [Mon, 5 Apr 2021 10:46:12 +0000 (11:46 +0100)]
do not try to merge OE signals into one for JTAG boundary driving
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 22:33:01 +0000 (23:33 +0100)]
disable PLL temporarily
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 15:50:31 +0000 (16:50 +0100)]
use OrderedDict in pinmap so that JTAG boundary scan is ordered
Luke Kenneth Casson Leighton [Sat, 27 Mar 2021 20:08:53 +0000 (20:08 +0000)]
comment out sdmmc
Luke Kenneth Casson Leighton [Sat, 27 Mar 2021 19:42:59 +0000 (19:42 +0000)]
change name format of EINT pads for litex, sigh
Luke Kenneth Casson Leighton [Sat, 27 Mar 2021 19:28:52 +0000 (19:28 +0000)]
change name format of EINT pads for litex, sigh
Luke Kenneth Casson Leighton [Thu, 25 Mar 2021 16:55:02 +0000 (16:55 +0000)]
re-add sdmmc ls180
Luke Kenneth Casson Leighton [Thu, 25 Mar 2021 08:32:41 +0000 (08:32 +0000)]
comment out eint litex problem
Luke Kenneth Casson Leighton [Thu, 25 Mar 2021 08:31:51 +0000 (08:31 +0000)]
comment out eint litex problem
Luke Kenneth Casson Leighton [Thu, 25 Mar 2021 06:54:08 +0000 (06:54 +0000)]
comment out sd0 litex problem
Luke Kenneth Casson Leighton [Thu, 25 Mar 2021 06:14:20 +0000 (06:14 +0000)]
temporary comment out mspi0, litex problem
Luke Kenneth Casson Leighton [Tue, 16 Mar 2021 17:25:38 +0000 (17:25 +0000)]
SDR DQMask incorrectly bi-directional, actually an output
Luke Kenneth Casson Leighton [Mon, 30 Nov 2020 15:00:41 +0000 (15:00 +0000)]
whoops invert vss/vdd power/ground by mistake
Luke Kenneth Casson Leighton [Fri, 13 Nov 2020 17:45:39 +0000 (17:45 +0000)]
rename ls180 pllock signal
Luke Kenneth Casson Leighton [Fri, 13 Nov 2020 16:01:03 +0000 (16:01 +0000)]
rename pll_48_o to pll_18_o in ls180 spec
Luke Kenneth Casson Leighton [Wed, 11 Nov 2020 14:45:51 +0000 (14:45 +0000)]
remove extraneous debug prints
Luke Kenneth Casson Leighton [Wed, 11 Nov 2020 14:31:31 +0000 (14:31 +0000)]
extend sys_clk pad name
Luke Kenneth Casson Leighton [Wed, 11 Nov 2020 14:30:22 +0000 (14:30 +0000)]
explicitly add sys_clk pad
Luke Kenneth Casson Leighton [Wed, 11 Nov 2020 14:21:59 +0000 (14:21 +0000)]
power and ground have to be named power and ground
Luke Kenneth Casson Leighton [Wed, 11 Nov 2020 14:10:43 +0000 (14:10 +0000)]
rename ls180 (io)vdd/vss pads
Luke Kenneth Casson Leighton [Wed, 11 Nov 2020 13:52:32 +0000 (13:52 +0000)]
add not-connected pads to ls180
Luke Kenneth Casson Leighton [Wed, 11 Nov 2020 13:07:41 +0000 (13:07 +0000)]
explicit add of sys pll lock to ls180
Luke Kenneth Casson Leighton [Wed, 11 Nov 2020 13:07:20 +0000 (13:07 +0000)]
explicit add of sys pll lock to ls180
Luke Kenneth Casson Leighton [Wed, 11 Nov 2020 13:01:34 +0000 (13:01 +0000)]
missing domain indicator, which removed EINT and PWM from JSON pads.instances
Luke Kenneth Casson Leighton [Tue, 10 Nov 2020 16:55:22 +0000 (16:55 +0000)]
move sys group over to opposite south corner
Luke Kenneth Casson Leighton [Tue, 10 Nov 2020 16:46:58 +0000 (16:46 +0000)]
PLL sys group has 2 select lines and PLL Lock out
Luke Kenneth Casson Leighton [Sat, 7 Nov 2020 19:23:39 +0000 (19:23 +0000)]
really laborious way of getting the direction of the pin into the json file
Luke Kenneth Casson Leighton [Fri, 6 Nov 2020 11:39:30 +0000 (11:39 +0000)]
reference correct pads for sl180 pwm
Luke Kenneth Casson Leighton [Fri, 6 Nov 2020 11:39:14 +0000 (11:39 +0000)]
rename VSS/VDD for ls180
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 13:06:06 +0000 (14:06 +0100)]
ignore built spec (ls180)
Luke Kenneth Casson Leighton [Sun, 4 Oct 2020 17:44:56 +0000 (18:44 +0100)]
apparently sdcard CMD is bi-directional
Luke Kenneth Casson Leighton [Sun, 4 Oct 2020 17:33:42 +0000 (18:33 +0100)]
rename spi_master to spimaster
Luke Kenneth Casson Leighton [Sun, 4 Oct 2020 15:16:59 +0000 (16:16 +0100)]
add pinmap to json file