Luke Kenneth Casson Leighton [Sat, 18 Apr 2020 16:26:45 +0000 (17:26 +0100)]
attempting to get CompUnitsBase connected up
Luke Kenneth Casson Leighton [Sat, 18 Apr 2020 13:31:15 +0000 (14:31 +0100)]
1st operation successful, 2nd still not running correctly
Luke Kenneth Casson Leighton [Sat, 18 Apr 2020 13:03:32 +0000 (14:03 +0100)]
yield ports in dep cell
Luke Kenneth Casson Leighton [Sat, 18 Apr 2020 13:01:07 +0000 (14:01 +0100)]
go_rd/go_wr should not be array in FU-REGs
Jacob Lifshay [Sat, 18 Apr 2020 00:07:58 +0000 (17:07 -0700)]
update libreriscv submodule
Jacob Lifshay [Sat, 18 Apr 2020 00:06:48 +0000 (17:06 -0700)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc
Jacob Lifshay [Sat, 18 Apr 2020 00:05:56 +0000 (17:05 -0700)]
adding WIP memory_pipe_experiment
Luke Kenneth Casson Leighton [Fri, 17 Apr 2020 16:29:46 +0000 (17:29 +0100)]
intpick request-release bug
Tobias Platen [Fri, 17 Apr 2020 16:06:25 +0000 (16:06 +0000)]
add with carry instructions
Luke Kenneth Casson Leighton [Fri, 17 Apr 2020 15:26:20 +0000 (16:26 +0100)]
rename signals
Luke Kenneth Casson Leighton [Fri, 17 Apr 2020 14:01:13 +0000 (15:01 +0100)]
delay too long
Luke Kenneth Casson Leighton [Fri, 17 Apr 2020 13:40:56 +0000 (14:40 +0100)]
temporarily not use MultiPriorityPicker
Luke Kenneth Casson Leighton [Fri, 17 Apr 2020 13:01:39 +0000 (14:01 +0100)]
whoops fu-fu readable / writeable output not an array
Luke Kenneth Casson Leighton [Fri, 17 Apr 2020 12:28:05 +0000 (13:28 +0100)]
whoops src_rsel signal-copy error
Luke Kenneth Casson Leighton [Fri, 17 Apr 2020 12:18:03 +0000 (13:18 +0100)]
whew multi rd/wr signals finally connecting
Luke Kenneth Casson Leighton [Fri, 17 Apr 2020 12:05:10 +0000 (13:05 +0100)]
whoops not using CompUnitMulti
Luke Kenneth Casson Leighton [Fri, 17 Apr 2020 10:32:37 +0000 (11:32 +0100)]
not using relative imports (pain in the neck)
Luke Kenneth Casson Leighton [Fri, 17 Apr 2020 10:31:12 +0000 (11:31 +0100)]
correct-wiring of FunctionUnit src/dest
Luke Kenneth Casson Leighton [Fri, 17 Apr 2020 10:30:57 +0000 (11:30 +0100)]
create distinct "done_o" signal
Jacob Lifshay [Fri, 17 Apr 2020 03:29:25 +0000 (20:29 -0700)]
fix tests
Jacob Lifshay [Fri, 17 Apr 2020 02:38:11 +0000 (19:38 -0700)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc
Jacob Lifshay [Fri, 17 Apr 2020 02:37:15 +0000 (19:37 -0700)]
add memory_pipe_experiment
Luke Kenneth Casson Leighton [Thu, 16 Apr 2020 21:10:50 +0000 (22:10 +0100)]
thoroughly broken but at least partly connected up scoreboard code
with multi-read/write signals
Luke Kenneth Casson Leighton [Thu, 16 Apr 2020 15:24:10 +0000 (16:24 +0100)]
update group picker to be multi-level capable. now uses MultiPriorityPicker
Luke Kenneth Casson Leighton [Thu, 16 Apr 2020 12:15:59 +0000 (13:15 +0100)]
combine read and rd_rel to get faster response for all_read
Luke Kenneth Casson Leighton [Thu, 16 Apr 2020 11:04:44 +0000 (12:04 +0100)]
add experimental multi-rd/wr comp unit
Tobias Platen [Wed, 15 Apr 2020 16:38:00 +0000 (18:38 +0200)]
fix a bug in QemuController.get_register
Luke Kenneth Casson Leighton [Tue, 14 Apr 2020 20:28:38 +0000 (21:28 +0100)]
turn experimental ALU into array-input
Luke Kenneth Casson Leighton [Tue, 14 Apr 2020 20:05:40 +0000 (21:05 +0100)]
whoops missed for-loop on fu-reg-multi
Luke Kenneth Casson Leighton [Tue, 14 Apr 2020 18:34:53 +0000 (19:34 +0100)]
rename multi modules
Luke Kenneth Casson Leighton [Tue, 14 Apr 2020 18:31:57 +0000 (19:31 +0100)]
move scoreboard multi rd/wr to new folder
Luke Kenneth Casson Leighton [Tue, 14 Apr 2020 18:29:47 +0000 (19:29 +0100)]
add multi version of memfu matrix
Luke Kenneth Casson Leighton [Tue, 14 Apr 2020 17:43:26 +0000 (18:43 +0100)]
add scoreboard fu-fu matrix with multi gord/wr
Luke Kenneth Casson Leighton [Tue, 14 Apr 2020 17:25:33 +0000 (18:25 +0100)]
add fu-fu multi-rd/wr dep cell
Luke Kenneth Casson Leighton [Tue, 14 Apr 2020 12:59:12 +0000 (13:59 +0100)]
scoreboard go_wr/go_wr multi-signal
Luke Kenneth Casson Leighton [Tue, 14 Apr 2020 12:52:09 +0000 (13:52 +0100)]
add first cut of variants that have multi-dest and multi-rd/wr flags
Luke Kenneth Casson Leighton [Mon, 13 Apr 2020 20:31:42 +0000 (21:31 +0100)]
dep cell src2_rsel_o replaced by src_rsel_o array
Luke Kenneth Casson Leighton [Sat, 11 Apr 2020 19:57:29 +0000 (20:57 +0100)]
spelling mistake
Luke Kenneth Casson Leighton [Sat, 11 Apr 2020 11:15:07 +0000 (12:15 +0100)]
holy cow, decode and run instruction works!
Luke Kenneth Casson Leighton [Sat, 11 Apr 2020 10:41:42 +0000 (11:41 +0100)]
add basic comment / docstring on program.py
Luke Kenneth Casson Leighton [Sat, 11 Apr 2020 10:32:44 +0000 (11:32 +0100)]
test additional instructions
Luke Kenneth Casson Leighton [Sat, 11 Apr 2020 09:26:13 +0000 (10:26 +0100)]
pass and lock immediate in
Luke Kenneth Casson Leighton [Sat, 11 Apr 2020 08:53:51 +0000 (09:53 +0100)]
adding immediates, tracking down a bug
Luke Kenneth Casson Leighton [Sat, 11 Apr 2020 08:53:24 +0000 (09:53 +0100)]
adding immediates, tracking down a bug
Michael Nolan [Fri, 10 Apr 2020 17:55:01 +0000 (13:55 -0400)]
Update libreriscv to fix test_mtcrf
Luke Kenneth Casson Leighton [Fri, 10 Apr 2020 16:07:07 +0000 (17:07 +0100)]
connect up ALU properly to pass full InternalOp subset over, MUL now works
Luke Kenneth Casson Leighton [Fri, 10 Apr 2020 14:59:44 +0000 (15:59 +0100)]
add 2nd add instruction to see what happens (success)
Luke Kenneth Casson Leighton [Fri, 10 Apr 2020 14:51:19 +0000 (15:51 +0100)]
eek, first cut at using POWER decoder2 in 6600 simulator, barely working
but at least working!
Luke Kenneth Casson Leighton [Fri, 10 Apr 2020 14:04:41 +0000 (15:04 +0100)]
whoops syntax error
Luke Kenneth Casson Leighton [Fri, 10 Apr 2020 12:57:12 +0000 (13:57 +0100)]
converting InstructionQ to use Decode2ToExecuteType
needed to convert Decode2ToExecuteType to use RecordObject
Luke Kenneth Casson Leighton [Fri, 10 Apr 2020 12:34:51 +0000 (13:34 +0100)]
add eq_from_execute1 subset function
Luke Kenneth Casson Leighton [Thu, 9 Apr 2020 15:33:13 +0000 (16:33 +0100)]
get CompUnitALU test running with InternalOp ALU subset
Luke Kenneth Casson Leighton [Thu, 9 Apr 2020 12:57:29 +0000 (13:57 +0100)]
experiment morphing ALU to take subset of Decode2ToExecute1
Tobias Platen [Thu, 9 Apr 2020 09:12:34 +0000 (11:12 +0200)]
fix 'Object is not an nMigen signal' error in test_sim.py
Luke Kenneth Casson Leighton [Wed, 8 Apr 2020 15:25:44 +0000 (16:25 +0100)]
pass InternalOp through to CompUnit ALU
Luke Kenneth Casson Leighton [Wed, 8 Apr 2020 14:54:09 +0000 (15:54 +0100)]
whoops realised src1/2 need to receive reg data, not reg #
Luke Kenneth Casson Leighton [Wed, 8 Apr 2020 14:48:48 +0000 (15:48 +0100)]
use power decoder InternalOp
Luke Kenneth Casson Leighton [Wed, 8 Apr 2020 13:46:32 +0000 (14:46 +0100)]
start using power decoder in 6600 comp units
Luke Kenneth Casson Leighton [Wed, 8 Apr 2020 12:00:34 +0000 (13:00 +0100)]
convert power_decoder2 Data to Record-based
Luke Kenneth Casson Leighton [Wed, 8 Apr 2020 10:48:03 +0000 (11:48 +0100)]
absolute imports
Luke Kenneth Casson Leighton [Tue, 7 Apr 2020 18:46:03 +0000 (19:46 +0100)]
try making CR bitrange 32..63 not 0..31
Luke Kenneth Casson Leighton [Tue, 7 Apr 2020 18:27:15 +0000 (19:27 +0100)]
note that CR must be offset by 32
Luke Kenneth Casson Leighton [Tue, 7 Apr 2020 18:25:49 +0000 (19:25 +0100)]
submodule update
Luke Kenneth Casson Leighton [Tue, 7 Apr 2020 18:13:38 +0000 (19:13 +0100)]
add "undefined" to namespace
Luke Kenneth Casson Leighton [Tue, 7 Apr 2020 18:11:36 +0000 (19:11 +0100)]
CR test "working" (for a given value of "success")
Luke Kenneth Casson Leighton [Tue, 7 Apr 2020 16:49:46 +0000 (17:49 +0100)]
add in special regs to be passed out of function (as return results)
Luke Kenneth Casson Leighton [Tue, 7 Apr 2020 16:27:41 +0000 (17:27 +0100)]
attempting to add mtcrf test, requires bringing CR and other regs into ops
Luke Kenneth Casson Leighton [Tue, 7 Apr 2020 16:12:08 +0000 (17:12 +0100)]
whoops off-by-one in slice ranges
Luke Kenneth Casson Leighton [Tue, 7 Apr 2020 16:01:06 +0000 (17:01 +0100)]
update submodules
Luke Kenneth Casson Leighton [Tue, 7 Apr 2020 15:54:50 +0000 (16:54 +0100)]
op_fields is passed over (and excludes register names)
Luke Kenneth Casson Leighton [Tue, 7 Apr 2020 14:37:35 +0000 (15:37 +0100)]
add CR and add field-selectable versions of CR0-7
Luke Kenneth Casson Leighton [Tue, 7 Apr 2020 14:37:11 +0000 (15:37 +0100)]
comment not to do bit-inversion here
Luke Kenneth Casson Leighton [Tue, 7 Apr 2020 14:35:30 +0000 (15:35 +0100)]
add setitem/getitem to FieldSelectableInt, and mod operator
Luke Kenneth Casson Leighton [Tue, 7 Apr 2020 14:30:26 +0000 (15:30 +0100)]
allow FieldSelectableInt to initialise from list or tuple
Luke Kenneth Casson Leighton [Tue, 7 Apr 2020 14:26:52 +0000 (15:26 +0100)]
add FieldSelectableInt which allows re-targetting of fields
Luke Kenneth Casson Leighton [Tue, 7 Apr 2020 11:09:19 +0000 (12:09 +0100)]
whew finally located opcodes for managing CRs
Jacob Lifshay [Tue, 7 Apr 2020 00:15:31 +0000 (17:15 -0700)]
fix apt cache
Jacob Lifshay [Mon, 6 Apr 2020 23:58:25 +0000 (16:58 -0700)]
update libreriscv submodule
Jacob Lifshay [Mon, 6 Apr 2020 23:56:31 +0000 (16:56 -0700)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc
Luke Kenneth Casson Leighton [Mon, 6 Apr 2020 21:08:35 +0000 (22:08 +0100)]
add extra info on SPRs
Luke Kenneth Casson Leighton [Mon, 6 Apr 2020 21:03:30 +0000 (22:03 +0100)]
update submodule
Luke Kenneth Casson Leighton [Mon, 6 Apr 2020 21:03:21 +0000 (22:03 +0100)]
add list of SPRs needed
Jacob Lifshay [Mon, 6 Apr 2020 19:00:27 +0000 (12:00 -0700)]
Merge branch 'fix-tests'
Michael Nolan [Mon, 6 Apr 2020 13:26:02 +0000 (09:26 -0400)]
Convert instruction info from tuple to namedtuple
Michael Nolan [Mon, 6 Apr 2020 13:15:33 +0000 (09:15 -0400)]
Add test for addpcis
Michael Nolan [Mon, 6 Apr 2020 13:15:08 +0000 (09:15 -0400)]
Begin adding PC to caller.py
Michael Nolan [Mon, 6 Apr 2020 13:14:39 +0000 (09:14 -0400)]
Fix broken tests from parser update
Michael Nolan [Sun, 5 Apr 2020 23:28:12 +0000 (19:28 -0400)]
Auto insert instruction fields into the namespace
Luke Kenneth Casson Leighton [Mon, 6 Apr 2020 12:56:33 +0000 (13:56 +0100)]
whoops swap regs and form
Luke Kenneth Casson Leighton [Mon, 6 Apr 2020 12:56:20 +0000 (13:56 +0100)]
split regs by comma into list
Luke Kenneth Casson Leighton [Mon, 6 Apr 2020 12:48:26 +0000 (13:48 +0100)]
whoops missing final newline, needed for parser to end
Luke Kenneth Casson Leighton [Mon, 6 Apr 2020 12:45:25 +0000 (13:45 +0100)]
skip blank lines between cases
Luke Kenneth Casson Leighton [Mon, 6 Apr 2020 12:33:56 +0000 (13:33 +0100)]
add annoying case-hack filter
Luke Kenneth Casson Leighton [Mon, 6 Apr 2020 11:15:28 +0000 (12:15 +0100)]
add individual field-detection where field spec is "d0,d1,d2"
Jacob Lifshay [Mon, 6 Apr 2020 02:08:22 +0000 (19:08 -0700)]
add apt-cache dir
Jacob Lifshay [Mon, 6 Apr 2020 02:01:40 +0000 (19:01 -0700)]
fix apt cache
Jacob Lifshay [Mon, 6 Apr 2020 01:53:14 +0000 (18:53 -0700)]
add pip and apt to gitlab cache
Jacob Lifshay [Mon, 6 Apr 2020 01:20:20 +0000 (18:20 -0700)]
all tests pass!
Jacob Lifshay [Mon, 6 Apr 2020 01:02:34 +0000 (18:02 -0700)]
add symbiyosys to ci
Jacob Lifshay [Mon, 6 Apr 2020 00:39:30 +0000 (17:39 -0700)]
add git submodules to CI