Luke Kenneth Casson Leighton [Mon, 13 Jul 2020 11:55:48 +0000 (12:55 +0100)]
fix read of sliced register
Luke Kenneth Casson Leighton [Mon, 13 Jul 2020 10:30:30 +0000 (11:30 +0100)]
not perfect but close enough: add read registers RA/S/B/C in parser
Luke Kenneth Casson Leighton [Mon, 13 Jul 2020 10:27:08 +0000 (11:27 +0100)]
add extswsli unit test
Luke Kenneth Casson Leighton [Mon, 13 Jul 2020 10:02:15 +0000 (11:02 +0100)]
add link to rotator, sign-extend mode OP_EXTSWSLI
Luke Kenneth Casson Leighton [Sun, 12 Jul 2020 22:01:50 +0000 (23:01 +0100)]
rename InternalOp to MicrOp
Luke Kenneth Casson Leighton [Sun, 12 Jul 2020 21:08:45 +0000 (22:08 +0100)]
attempting to get test_trap_sim working, seems to switch mode
Luke Kenneth Casson Leighton [Sun, 12 Jul 2020 20:55:54 +0000 (21:55 +0100)]
submodule update
Luke Kenneth Casson Leighton [Sun, 12 Jul 2020 20:55:48 +0000 (21:55 +0100)]
add OP_ATTN test back in
Luke Kenneth Casson Leighton [Sun, 12 Jul 2020 20:48:36 +0000 (21:48 +0100)]
exit FSM when termination detected
Luke Kenneth Casson Leighton [Sun, 12 Jul 2020 20:32:44 +0000 (21:32 +0100)]
code-morph on core connect_instruction
Luke Kenneth Casson Leighton [Sun, 12 Jul 2020 20:04:24 +0000 (21:04 +0100)]
modify PowerDecoder to read LDSTMode correctly
Luke Kenneth Casson Leighton [Sun, 12 Jul 2020 19:46:47 +0000 (20:46 +0100)]
change CSV LD/ST update field to LDSTMode (support cix)
Luke Kenneth Casson Leighton [Sun, 12 Jul 2020 12:33:19 +0000 (13:33 +0100)]
return unsigned int from binary reading
Luke Kenneth Casson Leighton [Sun, 12 Jul 2020 12:13:09 +0000 (13:13 +0100)]
update submodule
Luke Kenneth Casson Leighton [Sun, 12 Jul 2020 10:46:22 +0000 (11:46 +0100)]
missed setting of link register on OP_BC in PowerDecoder2
Luke Kenneth Casson Leighton [Sun, 12 Jul 2020 04:10:10 +0000 (05:10 +0100)]
msb of instruction causing sign-overflow
Luke Kenneth Casson Leighton [Sun, 12 Jul 2020 03:46:31 +0000 (04:46 +0100)]
add std and stdu ldst unit tests
Luke Kenneth Casson Leighton [Sun, 12 Jul 2020 03:46:04 +0000 (04:46 +0100)]
update-mode request write signalled too early
Luke Kenneth Casson Leighton [Sat, 11 Jul 2020 22:48:46 +0000 (23:48 +0100)]
sort out core write latching: gate by busy, and use CompUnit dest output
Luke Kenneth Casson Leighton [Sat, 11 Jul 2020 22:24:20 +0000 (23:24 +0100)]
* clarifying core function unit enable
* disabling wrflag based on fu busy
* NOP enabled when not stopped
g
Luke Kenneth Casson Leighton [Sat, 11 Jul 2020 22:13:44 +0000 (23:13 +0100)]
add bigendian flag
Luke Kenneth Casson Leighton [Sat, 11 Jul 2020 21:53:19 +0000 (22:53 +0100)]
add endian
Luke Kenneth Casson Leighton [Sat, 11 Jul 2020 21:50:37 +0000 (22:50 +0100)]
fix spr setting, set endianness
Luke Kenneth Casson Leighton [Sat, 11 Jul 2020 21:48:58 +0000 (22:48 +0100)]
sigh spelling
Luke Kenneth Casson Leighton [Sat, 11 Jul 2020 21:46:10 +0000 (22:46 +0100)]
add bigendian
Luke Kenneth Casson Leighton [Sat, 11 Jul 2020 20:06:51 +0000 (21:06 +0100)]
more setting bigendian
Luke Kenneth Casson Leighton [Sat, 11 Jul 2020 20:01:47 +0000 (21:01 +0100)]
add bigendian mode to helloworld test
Luke Kenneth Casson Leighton [Sat, 11 Jul 2020 16:38:14 +0000 (17:38 +0100)]
sort out big/little endian startup on qemu
Luke Kenneth Casson Leighton [Sat, 11 Jul 2020 16:34:07 +0000 (17:34 +0100)]
sorting out bigendian/littleendian including in qemu
qemu is a pain!
Luke Kenneth Casson Leighton [Sat, 11 Jul 2020 11:35:23 +0000 (12:35 +0100)]
whoops output trunc_divs not trunc_div
Luke Kenneth Casson Leighton [Sat, 11 Jul 2020 11:02:29 +0000 (12:02 +0100)]
add random mulhd and mulld tests
Luke Kenneth Casson Leighton [Sat, 11 Jul 2020 10:26:20 +0000 (11:26 +0100)]
enable mul tests after sorting pseudo-code mul overflow
Luke Kenneth Casson Leighton [Sat, 11 Jul 2020 10:08:48 +0000 (11:08 +0100)]
special test for mul hw to cope with ignoring OE flag
Luke Kenneth Casson Leighton [Fri, 10 Jul 2020 20:09:30 +0000 (21:09 +0100)]
add a DIVS function as separate and discrete from floor_div
likewise for MODS and MULS
Luke Kenneth Casson Leighton [Fri, 10 Jul 2020 15:29:07 +0000 (16:29 +0100)]
add random unsigned div tests
Luke Kenneth Casson Leighton [Fri, 10 Jul 2020 15:28:24 +0000 (16:28 +0100)]
add overflow div tests
Luke Kenneth Casson Leighton [Fri, 10 Jul 2020 15:28:12 +0000 (16:28 +0100)]
propagate missing parameters from div
Luke Kenneth Casson Leighton [Fri, 10 Jul 2020 15:27:01 +0000 (16:27 +0100)]
code comments
Luke Kenneth Casson Leighton [Fri, 10 Jul 2020 15:16:12 +0000 (16:16 +0100)]
do not set div result if overflow occurs
Luke Kenneth Casson Leighton [Fri, 10 Jul 2020 15:05:23 +0000 (16:05 +0100)]
re-enable div random tests and other regressions
Luke Kenneth Casson Leighton [Fri, 10 Jul 2020 15:04:08 +0000 (16:04 +0100)]
check for div_overflow equal to None rather than == 1
Luke Kenneth Casson Leighton [Fri, 10 Jul 2020 13:30:28 +0000 (14:30 +0100)]
re-add rc/oe back into LDST input record
this for later use with st*cx because it writes CR and OV (and SO)
Luke Kenneth Casson Leighton [Fri, 10 Jul 2020 13:21:48 +0000 (14:21 +0100)]
whew panic over, missed a bigendian argument in test_compunit.py
Luke Kenneth Casson Leighton [Fri, 10 Jul 2020 13:12:50 +0000 (14:12 +0100)]
add test7 div regression
Luke Kenneth Casson Leighton [Fri, 10 Jul 2020 09:40:15 +0000 (10:40 +0100)]
add more debug output for #425
Luke Kenneth Casson Leighton [Fri, 10 Jul 2020 09:16:28 +0000 (10:16 +0100)]
add debugging chain for #425
Luke Kenneth Casson Leighton [Fri, 10 Jul 2020 09:15:52 +0000 (10:15 +0100)]
update submodule
Luke Kenneth Casson Leighton [Fri, 10 Jul 2020 08:44:27 +0000 (09:44 +0100)]
cut/paste error writing to wrong vcd file
Jacob Lifshay [Fri, 10 Jul 2020 00:21:37 +0000 (17:21 -0700)]
switch to using Signal.width instead of Signal.shape()[0] since Shape isn't a tuple anymore
see https://github.com/nmigen/nmigen/pull/422
Jacob Lifshay [Fri, 10 Jul 2020 00:21:19 +0000 (17:21 -0700)]
format file
Jacob Lifshay [Fri, 10 Jul 2020 00:19:29 +0000 (17:19 -0700)]
update libreriscv submodule
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 23:18:53 +0000 (00:18 +0100)]
add regression test for div overflow case
see https://bugs.libre-soc.org/show_bug.cgi?id=425
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 21:20:41 +0000 (22:20 +0100)]
slightly different so handling in common output stage
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 21:08:55 +0000 (22:08 +0100)]
also set so only if OE requires it
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 21:08:15 +0000 (22:08 +0100)]
debug information related to 32/64 bit mode
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 21:07:06 +0000 (22:07 +0100)]
bug #424 - 32/64 bit is a *global* flag not a per-op one
when it comes to setting CR0
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 20:10:37 +0000 (21:10 +0100)]
test top bit 31 in 32-bit mode for CR0 creation
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 19:54:09 +0000 (20:54 +0100)]
ha ha very funny. pipelines being pipelines, you have to wait for them
just as with MUL, it was necessary to set the "valid" signal for
only one cycle otherwise spurious output is created
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 19:44:34 +0000 (20:44 +0100)]
whoops test gets copied 4 times on the If.
create intermediate signal
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 19:37:14 +0000 (20:37 +0100)]
ALU output stage, change logic slightly
test for oe/ok then set xer/ov data/ok if true
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 19:28:54 +0000 (20:28 +0100)]
set xer_ov.ok = 1
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 19:18:04 +0000 (20:18 +0100)]
remove unneeded xer.ca in MulOutputData
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 19:14:29 +0000 (20:14 +0100)]
something weird going on with div. interaction between tests
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 19:00:29 +0000 (20:00 +0100)]
simplify setting of mul overflow into xer_ov
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 19:00:07 +0000 (20:00 +0100)]
clarifying comments on setting xer_ov/so
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 18:59:45 +0000 (19:59 +0100)]
DIV overflow needs to be copied into both bits of XER.ov
(OV, OV32)
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 18:58:13 +0000 (19:58 +0100)]
add debug output of DIV results
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 18:57:34 +0000 (19:57 +0100)]
check result first then CR second
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 17:07:25 +0000 (18:07 +0100)]
munge alu_fsm Shifter into looking like CompALU API compliant
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 12:34:07 +0000 (13:34 +0100)]
resolving issues with div tests (turned out to be nmutil.divmod)
adding more tests to track down a CR0 issue
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 10:49:51 +0000 (11:49 +0100)]
remove xer_ca from DIV pipeline (took a bit of messing about)
Cesar Strauss [Thu, 9 Jul 2020 09:50:47 +0000 (06:50 -0300)]
Define ports for a simple sequential Shifter
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 09:55:52 +0000 (10:55 +0100)]
irony comment on how one line creates a massive array of gates
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 09:52:46 +0000 (10:52 +0100)]
add new stages etc. to get multiply working without xer_ca
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 09:32:57 +0000 (10:32 +0100)]
create new DivMulOutputData which does not have CA/CA32
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 08:32:55 +0000 (09:32 +0100)]
make carry output handling optional in common output stage
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 00:07:24 +0000 (01:07 +0100)]
identifying locations where big/little endian is in place, adding args
Luke Kenneth Casson Leighton [Wed, 8 Jul 2020 19:49:32 +0000 (20:49 +0100)]
resolving bigendian/littleendian modes in qemu sim
Luke Kenneth Casson Leighton [Wed, 8 Jul 2020 19:24:45 +0000 (20:24 +0100)]
resolving old and new behaviour for lookup of SPRs
Luke Kenneth Casson Leighton [Wed, 8 Jul 2020 19:23:39 +0000 (20:23 +0100)]
resolving old and new behaviour for lookup of SPRs
Luke Kenneth Casson Leighton [Wed, 8 Jul 2020 19:15:23 +0000 (20:15 +0100)]
adding in ALU test back in, debugging SPR setup
Luke Kenneth Casson Leighton [Wed, 8 Jul 2020 19:09:48 +0000 (20:09 +0100)]
sorting out setting of XER
Luke Kenneth Casson Leighton [Wed, 8 Jul 2020 18:45:27 +0000 (19:45 +0100)]
add spr to fast reg converter
Luke Kenneth Casson Leighton [Wed, 8 Jul 2020 18:37:14 +0000 (19:37 +0100)]
got test_issuer operational on one unit test
however needs further investigation
Luke Kenneth Casson Leighton [Wed, 8 Jul 2020 17:26:16 +0000 (18:26 +0100)]
switch assembler to little-endian
Luke Kenneth Casson Leighton [Wed, 8 Jul 2020 16:41:48 +0000 (17:41 +0100)]
stashing current state of investigation whilst looking for regression bug
Luke Kenneth Casson Leighton [Wed, 8 Jul 2020 16:22:52 +0000 (17:22 +0100)]
add test trap simulator unit test
Luke Kenneth Casson Leighton [Wed, 8 Jul 2020 16:22:35 +0000 (17:22 +0100)]
allow qemu to stop at specified end point
Luke Kenneth Casson Leighton [Wed, 8 Jul 2020 16:18:51 +0000 (17:18 +0100)]
add mtspr and bcctrl instructions to helloworld test
Luke Kenneth Casson Leighton [Wed, 8 Jul 2020 16:18:29 +0000 (17:18 +0100)]
add option to qemu to break at known alternate address
Luke Kenneth Casson Leighton [Wed, 8 Jul 2020 16:05:16 +0000 (17:05 +0100)]
add to/from spr test (mtspr, mfspr)
Luke Kenneth Casson Leighton [Wed, 8 Jul 2020 15:09:18 +0000 (16:09 +0100)]
add code-fragment from microwatt helloworld
Luke Kenneth Casson Leighton [Wed, 8 Jul 2020 15:05:18 +0000 (16:05 +0100)]
add a simple addis test (regression)
Luke Kenneth Casson Leighton [Wed, 8 Jul 2020 15:05:04 +0000 (16:05 +0100)]
copy binary loaded from disk into data memory as well
Cesar Strauss [Wed, 8 Jul 2020 09:42:07 +0000 (06:42 -0300)]
Start the FSM-based ALU example.
Jacob Lifshay [Wed, 8 Jul 2020 02:39:36 +0000 (19:39 -0700)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc
Jacob Lifshay [Wed, 8 Jul 2020 02:39:13 +0000 (19:39 -0700)]
add WIP pipeline loop demo
Luke Kenneth Casson Leighton [Tue, 7 Jul 2020 23:41:12 +0000 (00:41 +0100)]
add hello world binary test
Luke Kenneth Casson Leighton [Tue, 7 Jul 2020 23:23:56 +0000 (00:23 +0100)]
whoops error in test of dynamic parameter
Luke Kenneth Casson Leighton [Tue, 7 Jul 2020 23:21:48 +0000 (00:21 +0100)]
sort-of got binary execution test working