Luke Kenneth Casson Leighton [Wed, 1 Aug 2018 07:38:53 +0000 (08:38 +0100)]
add sdram interface, remove unneeded import
Luke Kenneth Casson Leighton [Wed, 1 Aug 2018 07:30:53 +0000 (08:30 +0100)]
remove unneeded imports
Luke Kenneth Casson Leighton [Wed, 1 Aug 2018 07:30:19 +0000 (08:30 +0100)]
AddingPeripherals.mdwn
Luke Kenneth Casson Leighton [Wed, 1 Aug 2018 07:30:04 +0000 (08:30 +0100)]
AddingPeripherals.mdwn
Luke Kenneth Casson Leighton [Wed, 1 Aug 2018 07:29:56 +0000 (08:29 +0100)]
add sdr as fast-bus peripheral
Luke Kenneth Casson Leighton [Wed, 1 Aug 2018 07:09:31 +0000 (08:09 +0100)]
rename sd to mmc to avoid name clash with sdram
Luke Kenneth Casson Leighton [Wed, 1 Aug 2018 07:05:10 +0000 (08:05 +0100)]
AddingPeripherals.mdwn
Luke Kenneth Casson Leighton [Wed, 1 Aug 2018 06:57:27 +0000 (07:57 +0100)]
change spec for SDR DQM to +
Luke Kenneth Casson Leighton [Wed, 1 Aug 2018 06:52:37 +0000 (07:52 +0100)]
whoops name wrong
Luke Kenneth Casson Leighton [Wed, 1 Aug 2018 06:11:44 +0000 (07:11 +0100)]
add sdram peripheral to i_class
Luke Kenneth Casson Leighton [Wed, 1 Aug 2018 05:50:12 +0000 (06:50 +0100)]
AddingPeripherals.mdwn
Luke Kenneth Casson Leighton [Wed, 1 Aug 2018 05:46:47 +0000 (06:46 +0100)]
AddingPeripherals.mdwn
Luke Kenneth Casson Leighton [Wed, 1 Aug 2018 05:46:33 +0000 (06:46 +0100)]
add sdram3 function
Luke Kenneth Casson Leighton [Tue, 31 Jul 2018 07:59:44 +0000 (08:59 +0100)]
when muxwidth == 1 output pin directly
Luke Kenneth Casson Leighton [Tue, 31 Jul 2018 07:51:15 +0000 (08:51 +0100)]
use dedicated cell output for muxwidth = 1
Luke Kenneth Casson Leighton [Tue, 31 Jul 2018 07:42:04 +0000 (08:42 +0100)]
update i_class pinspec
Luke Kenneth Casson Leighton [Tue, 31 Jul 2018 07:20:30 +0000 (08:20 +0100)]
fix cell bit widths if muxwidth = 1
Luke Kenneth Casson Leighton [Tue, 31 Jul 2018 07:05:27 +0000 (08:05 +0100)]
output cell mux peripheral side
Luke Kenneth Casson Leighton [Tue, 31 Jul 2018 07:02:20 +0000 (08:02 +0100)]
start code-gen for mux cells
Luke Kenneth Casson Leighton [Tue, 31 Jul 2018 06:57:41 +0000 (07:57 +0100)]
read cell width and bank from pinmap.txt
Luke Kenneth Casson Leighton [Tue, 31 Jul 2018 06:52:12 +0000 (07:52 +0100)]
put pinbank and mux widths into pinmap.txt
Luke Kenneth Casson Leighton [Tue, 31 Jul 2018 06:39:08 +0000 (07:39 +0100)]
remove muxwidths
Luke Kenneth Casson Leighton [Tue, 31 Jul 2018 06:37:47 +0000 (07:37 +0100)]
write mux width and read back in
Luke Kenneth Casson Leighton [Tue, 31 Jul 2018 06:28:23 +0000 (07:28 +0100)]
remove write_ptp, add bitwidths.txt file
Luke Kenneth Casson Leighton [Tue, 31 Jul 2018 06:08:24 +0000 (07:08 +0100)]
make mux cells possible to be 1 wide
Luke Kenneth Casson Leighton [Tue, 31 Jul 2018 06:03:14 +0000 (07:03 +0100)]
pass in muxwidth as argument
Luke Kenneth Casson Leighton [Tue, 31 Jul 2018 06:00:21 +0000 (07:00 +0100)]
specify mux width by argument
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 10:41:43 +0000 (11:41 +0100)]
comment out fb master ifc
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 10:23:48 +0000 (11:23 +0100)]
add master connection
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 10:00:55 +0000 (11:00 +0100)]
sort out jtag clock/reset interchange
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 09:39:39 +0000 (10:39 +0100)]
hmm something suspicious with jtag tck/reset
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 09:22:19 +0000 (10:22 +0100)]
whoops iocell_side interface in wrong template
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 09:19:22 +0000 (10:19 +0100)]
comment out jtag clock sync for now
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 09:18:46 +0000 (10:18 +0100)]
TMS JTAG is an input
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 09:10:47 +0000 (10:10 +0100)]
add iocell peripheral and jtag pins
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 09:06:20 +0000 (10:06 +0100)]
add iocell peripheral and jtag pins
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 08:31:46 +0000 (09:31 +0100)]
invert clock/spc link for input pintypes
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 07:53:27 +0000 (08:53 +0100)]
correct flexbus connections
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 07:47:11 +0000 (08:47 +0100)]
sort out flexbus vector pincon
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 07:31:50 +0000 (08:31 +0100)]
sort out flexbus vector pincon
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 07:20:28 +0000 (08:20 +0100)]
add pin renaming for vector connections
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 06:31:45 +0000 (07:31 +0100)]
flexbus clock-synced
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 06:19:26 +0000 (07:19 +0100)]
vectorise pincon sync
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 05:53:09 +0000 (06:53 +0100)]
clock resolution
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 05:40:10 +0000 (06:40 +0100)]
add lcd clock sync
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 05:04:16 +0000 (06:04 +0100)]
format rgbttl connections
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 04:52:33 +0000 (05:52 +0100)]
missed mk_pincon rename for sdcard
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 04:51:28 +0000 (05:51 +0100)]
missed mk_pincon rename for sdcard
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 04:50:32 +0000 (05:50 +0100)]
missed mk_pincon rename for eint
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 04:48:58 +0000 (05:48 +0100)]
whoops _mk_pincon bypass
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 04:48:35 +0000 (05:48 +0100)]
whoops _mk_pincon bypass
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 04:47:28 +0000 (05:47 +0100)]
uart clock and reset
Luke Kenneth Casson Leighton [Mon, 30 Jul 2018 04:42:45 +0000 (05:42 +0100)]
one too many _interrupt strings
Luke Kenneth Casson Leighton [Sun, 29 Jul 2018 09:54:01 +0000 (10:54 +0100)]
horrible clock-sync hack
Luke Kenneth Casson Leighton [Sun, 29 Jul 2018 09:52:24 +0000 (10:52 +0100)]
horrible clock-sync hack
Luke Kenneth Casson Leighton [Sun, 29 Jul 2018 09:48:05 +0000 (10:48 +0100)]
add tx clockhack
Luke Kenneth Casson Leighton [Sun, 29 Jul 2018 09:45:06 +0000 (10:45 +0100)]
add tx clockhack
Luke Kenneth Casson Leighton [Sun, 29 Jul 2018 09:36:49 +0000 (10:36 +0100)]
horrible clock-sync hack
Luke Kenneth Casson Leighton [Sun, 29 Jul 2018 09:35:26 +0000 (10:35 +0100)]
horrible clock-sync hack
Luke Kenneth Casson Leighton [Sun, 29 Jul 2018 06:25:53 +0000 (07:25 +0100)]
fix gpio mk_pincon function rename
Luke Kenneth Casson Leighton [Sun, 29 Jul 2018 06:24:52 +0000 (07:24 +0100)]
fix gpio mk_pincon function rename
Luke Kenneth Casson Leighton [Sat, 28 Jul 2018 10:01:14 +0000 (11:01 +0100)]
whoops num axi regs 16 too many
Luke Kenneth Casson Leighton [Sat, 28 Jul 2018 09:58:15 +0000 (10:58 +0100)]
correct address out_en name
Luke Kenneth Casson Leighton [Sat, 28 Jul 2018 09:57:16 +0000 (10:57 +0100)]
whoops reverse flexbus in/out AD
Luke Kenneth Casson Leighton [Sat, 28 Jul 2018 09:53:25 +0000 (10:53 +0100)]
rename fb pin
Luke Kenneth Casson Leighton [Sat, 28 Jul 2018 09:52:08 +0000 (10:52 +0100)]
redo mkpincon for fast names
Luke Kenneth Casson Leighton [Sat, 28 Jul 2018 09:36:18 +0000 (10:36 +0100)]
fix includes
Luke Kenneth Casson Leighton [Sat, 28 Jul 2018 09:22:04 +0000 (10:22 +0100)]
put address width to 64
Luke Kenneth Casson Leighton [Sat, 28 Jul 2018 09:18:10 +0000 (10:18 +0100)]
put PADDR_WIDTH separate from ADDR_WIDTH
Luke Kenneth Casson Leighton [Sat, 28 Jul 2018 09:16:14 +0000 (10:16 +0100)]
fix PADDR to 32
Luke Kenneth Casson Leighton [Sat, 28 Jul 2018 09:06:30 +0000 (10:06 +0100)]
put back to RV64
Luke Kenneth Casson Leighton [Sat, 28 Jul 2018 09:02:40 +0000 (10:02 +0100)]
sigh go to 32-bit for now
Luke Kenneth Casson Leighton [Sat, 28 Jul 2018 05:27:52 +0000 (06:27 +0100)]
cleanup soc template
Luke Kenneth Casson Leighton [Sat, 28 Jul 2018 05:20:57 +0000 (06:20 +0100)]
confuse Tuple2 name
Luke Kenneth Casson Leighton [Sat, 28 Jul 2018 05:18:41 +0000 (06:18 +0100)]
fix fast/slow Tuple2 fn names
Luke Kenneth Casson Leighton [Sat, 28 Jul 2018 05:10:12 +0000 (06:10 +0100)]
cleanup soc template
Luke Kenneth Casson Leighton [Sat, 28 Jul 2018 05:08:26 +0000 (06:08 +0100)]
cleanup soc template
Luke Kenneth Casson Leighton [Sat, 28 Jul 2018 05:05:26 +0000 (06:05 +0100)]
fix fast slave bus index names
Luke Kenneth Casson Leighton [Sat, 28 Jul 2018 04:55:14 +0000 (05:55 +0100)]
whoops typo in slave indices
Luke Kenneth Casson Leighton [Sat, 28 Jul 2018 04:50:49 +0000 (05:50 +0100)]
add tuple2 templates
Luke Kenneth Casson Leighton [Sat, 28 Jul 2018 04:50:14 +0000 (05:50 +0100)]
generate separate file for fast memory map
Luke Kenneth Casson Leighton [Sat, 28 Jul 2018 04:43:26 +0000 (05:43 +0100)]
split out slow memory map to separate file
Luke Kenneth Casson Leighton [Sat, 28 Jul 2018 04:43:17 +0000 (05:43 +0100)]
split out slow memory map to separate file
Luke Kenneth Casson Leighton [Sat, 28 Jul 2018 04:43:10 +0000 (05:43 +0100)]
split out slow memory map to separate file
Luke Kenneth Casson Leighton [Fri, 27 Jul 2018 11:25:45 +0000 (12:25 +0100)]
resolve nameclash
Luke Kenneth Casson Leighton [Fri, 27 Jul 2018 11:24:08 +0000 (12:24 +0100)]
package name soc not Soc
Luke Kenneth Casson Leighton [Fri, 27 Jul 2018 11:22:46 +0000 (12:22 +0100)]
change to use core_parameters
Luke Kenneth Casson Leighton [Fri, 27 Jul 2018 10:32:56 +0000 (11:32 +0100)]
pep8 cleanup
Luke Kenneth Casson Leighton [Fri, 27 Jul 2018 10:30:30 +0000 (11:30 +0100)]
add core_parameters include
Luke Kenneth Casson Leighton [Fri, 27 Jul 2018 10:29:04 +0000 (11:29 +0100)]
add core_parameters include
Luke Kenneth Casson Leighton [Fri, 27 Jul 2018 10:24:14 +0000 (11:24 +0100)]
create FastTuple2 function
Luke Kenneth Casson Leighton [Fri, 27 Jul 2018 09:56:52 +0000 (10:56 +0100)]
add includes
Luke Kenneth Casson Leighton [Fri, 27 Jul 2018 09:53:35 +0000 (10:53 +0100)]
add extra -D options to makefile template
Luke Kenneth Casson Leighton [Fri, 27 Jul 2018 09:49:59 +0000 (10:49 +0100)]
add extra -D options to makefile template
Luke Kenneth Casson Leighton [Fri, 27 Jul 2018 09:30:35 +0000 (10:30 +0100)]
add RV64 define to instance_defines
Luke Kenneth Casson Leighton [Fri, 27 Jul 2018 09:18:36 +0000 (10:18 +0100)]
macro Reg_width -> DATA
Luke Kenneth Casson Leighton [Fri, 27 Jul 2018 09:18:00 +0000 (10:18 +0100)]
typo
Luke Kenneth Casson Leighton [Fri, 27 Jul 2018 09:17:16 +0000 (10:17 +0100)]
add uncore debug path
Luke Kenneth Casson Leighton [Fri, 27 Jul 2018 09:14:23 +0000 (10:14 +0100)]
change to compile soc
Luke Kenneth Casson Leighton [Fri, 27 Jul 2018 09:10:15 +0000 (10:10 +0100)]
use quart wrapper for quart
projects / pinmux.git / log