anv: Properly call gen75_emit_state_base_address on Haswell.

This should fix MOCS values.  Caught by Coverity.

CID: 1364155

Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

genxml: Rename "API Rendering Disable" to "Rendering Disable".

Gen7/7.5 call it "Rendering Disable" while Gen8/9 prefix it with "API".

Pick one for consistency, and so we can share code between generations.

Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

anv: Unify 3DSTATE_CLIP code across generations.

The bulk of this is the same.  There are just a couple fields that only
exist on one generation or another, and we can easily handle those with
an #ifdef.

Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

anv: Enable early culling on Gen7.

We set the cull mode, but forgot the enable bit.  Gen8 uses this.

Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

anv: Fix near plane clipping on Gen7/7.5.

The Gen7/7.5 clip code used APIMODE_OGL, while the Gen8+ clip code used
APIMODE_D3D.  The meaning hasn't changed, so one of these must be wrong.

It appears that the hardware documentation is completely wrong.  It
claims that the "API Mode" bit means:

   0h    APIMODE_OGL    NEAR_VP boundary == 0.0 (NDC)
   1h    APIMODE_D3D    NEAR_VP boundary == -1.0 (NDC)

However, DirectX typically uses 0.0 for the near plane, while unextended
OpenGL uses -1.0.  i965's gen6_clip_state.c uses APIMODE_D3D for the
GL_ZERO_TO_ONE case, so I believe the meanings are backwards from what
the documentation says.

Section 23.2 ("Primitive Clipping") of the Vulkan 1.0.21 specification
contains the following equations:

   -w_c <= x_c <= w_c
   -w_c <= y_c <= w_c
      0 <= z_c <= w_c

This means that Vulkan follows D3D semantics.

Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

genxml: Add APIMODE_D3D missing enum values and improve consistency.

Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

genxml: Add CLIPMODE_* prefix to 3DSTATE_CLIP's "Clip Mode" enum values.

Gen6-7.5 use CLIPMODE_REJECT_ALL, while Gen8+ just used REJECT_ALL.
Being consistent will let me unify code, and I prefer having the prefix.

Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

swr: [rasterizer core] introduce simd16intrin.h

Refactoring to leave existing simd_* intrinsics in "simdintrin.h" unchanged,
adding corresponding simd16_* intrinsics in "simd16intrin.h" on the side,
with emulation, that we can use piecemeal, rather than the all-or-nothing
approach to bring up avx512.

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>

swr: [rasterizer core] fix for possible int32 overflow condition

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>

swr: [rasterizer core] rename *_MAX enum values to *_COUNT

Makes these names semantically correct.

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>

swr: [rasterizer core] centroid correction

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>

swr: [rasterizer core] support range of values in TemplateArgUnroller

Fixes Linux warnings.

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>

swr: [rasterizer core] ensure adjacent topologies use the cut-aware PA

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>

swr: [rasterizer] attribute swizzling and linkage

Add support for enhanced attribute swizzling. Currently supports constant
source overrides to handle PrimitiveID support. No support yet for input
select swizzling or wrap shortest. Removes obsoleted linkageMask and
associated code.

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>

swr: [rasterizer common] icc declspec definitions

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>

swr: [rasterizer jitter] rework vertex/instance ID storage in fetch

Moved the setting into the existing component control code. Fixes bad
interaction between attribute/component setting for vertex/instance ID
and component packing.

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>

swr: [rasterizer core] avx512 simd utility work

Enabling KNOB_SIMD_WIDTH = 16 for AVX512 pre-work and low level simd utils

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>

swr: [rasterizer core] viewport rounding for disabled scissor

Adjust viewport rounding when scissor rect is disabled during macro
tile scissor setup.

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>

i965: Stop muging cube array lengths by 6

From the Sky Lake PRM:

   "For SURFTYPE_CUBE: For Sampling Engine Surfaces and Typed Data Port
   Surfaces, the range of this field is [0,340], indicating the number of
   cube array elements (equal to the number of underlying 2D array elements
   divided by 6). For other surfaces, this field must be zero."

In other words, the depth field for cube maps is in number of cubes not
number of 2-D slices so we need to divide by 6.  ISL will do this correctly
for us assuming that we provide it with the correct array bounds which it
expects to be in 2-D slices.  It appears as if we've been doing this wrong
ever since we first added cube map arrays for Sandy Bridge and the change
to ISL made things slightly worse.  While we're at it, we now need to remoe
the shader hacks we've always done since they were only needed because we
were setting the depth field six times too large.

v2: Fix the vec4 backend as well (not sure how I missed this).

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Chris Forbes <chrisforbes@google.com>

i965/miptree: Set logical_depth0 == 6 for cube maps

This matches what we do for cube maps where logical_depth0 is in number of
face-layers rather than number of cubes.  This does mean that we will
temporarily be setting the surface bounds too loose for cube map textures
but we are already setting them too loose for cube arrays and we will be
fixing that in the next commit anyway.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Chris Forbes <chrisforbes@google.com>
Cc: "12.0 11.2 11.1" <mesa-stable@lists.freedesktop.org>

i965/miptree: Enforce that height == 1 for 1-D array textures

The GL API and mesa internals do this differently than we do.  In GL, there
is no depth parameter for 1-D arrays and height is used.  In the i965
miptree code we do the sane thing and make height == 1 and use depth for
number of slices.  This makes for a mismatch every time we create a 1-D
array texture from GL.  Instead of actually solving this problem, we just
said "1-D is hard, let's make sure it works no matter which way we pass the
parameters" and called it a day.

This commit fixes the one GL -> i965 transition point where we weren't
already handling 1-D array textures to do the right thing and then replaces
the magic fixup code with an assert that you're doing the right thing.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Chris Forbes <chrisforbes@google.com>
Cc: "12.0 11.2 11.1" <mesa-stable@lists.freedesktop.org>

Avoid overflow in 'last' variable of FindGLXFunction(...)

This 'last' variable used in FindGLXFunction(...) may become negative,
but has been defined as unsigned int resulting in an overflow,
finally resulting in a segfault when accessing _glXDispatchTableStrings[...].
Fixed this by definining it as signed int. 'first' variable also needs to be
defined as signed int. Otherwise condition for while loop fails due to C
implicitly converting signed to unsigned values before comparison.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Stefan Dirsch <sndirsch@suse.de>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

egl/android: Stop leaking DRI images

Current implementation of the DRI image loader does not free the images
created in get_back_bo() and so leaks memory. Moreover, it creates a new
image every time the DRI driver queries for buffers, even if the backing
native buffer has not changed. leaking memory again.

This patch adds missing call to destroyImage() in droid_enqueue_buffer()
and a check if image is already created to get_back_bo() to fix the
above.

Cc: "11.2 12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

egl/android: Add some useful error messages

It is much easier to debug issues when the application gives some
meaningful error messages. This patch adds few to the EGL Android
platform backend.

Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

egl/android: Check return value of dri2_get_dri_config()

It might return NULL if specific config variant is unsupported.

Cc: "11.2 12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

i965: store reference to the context within struct brw_fence (v2)

As the spec allows for {server,client}_wait_sync to be called without
currently bound context, while our implementation requires context
pointer.

v2: Add a mutex and acquire it for the duration of
    brw_fence_client_wait() and brw_fence_is_completed() as suggested
    by Chad.

Cc: "11.2 12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Tomasz Figa <tfiga@chromium.org>

egl/dri2: dri2_make_current: Set EGL error if bindContext fails

Without this, if a configuration is, say, available only on GLES2/3, but
not on GLES1, and is rejected by the dri module's bindContext call,
eglMakeCurrent fails with error "EGL_SUCCESS".

In this patch, we set error to EGL_BAD_MATCH, which is what CTS/dEQP
dEQP-EGL.functional.surfaceless_context expect.

Cc: "11.2 12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

egl/android: Remove unused variables

There are some unused variables left after previous clean-ups triggering
compiler warnings. Let's remove them.

Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

gallium/dri: Add shared glapi to LIBADD on Android

An earlier patch fixed the problem for classic drivers, however Gallium
was still left broken. This patch applies the same workaround to
Gallium, when compiled for Android. Following is a quote from the
original patch:

0cbc90c57cfc mesa: dri: Add shared glapi to LIBADD on Android

/system/vendor/lib/dri/*_dri.so actually depend on libglapi: without
this, loading the so file fails with:
cannot locate symbol "__emutls_v._glapi_tls_Context"

On non-Android (non-bionic) platform, EGL uses the following
workflow, which works fine:
  dlopen("libglapi.so", RTLD_LAZY | RTLD_GLOBAL);
  dlopen("dri/<driver>_dri.so", RTLD_NOW | RTLD_GLOBAL);

However, bionic does not respect the RTLD_GLOBAL flag, and the dri
library cannot find symbols in libglapi.so, so we need to link
to libglapi.so explicitly. Android.mk already does this.

Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

mesa: scons: remove left over src/glsl include

The path no longer exists.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

mesa: scons: list builddir before srcdir

Analogous to previous commit.

Note: scons always uses OOT builds, while the in-tree generated files
could be created either manually or by the autoconf build.

Cc: "11.2 12.0" <mesa-stable@lists.freedesktop.org>
Cc: Alexander von Gluck IV <kallisti5@unixzen.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

mesa: automake: list builddir before srcdir

In the case of building in out-of-tree fashion, while having generated
in-tree sources, the latter [likely stale] files will be used.

Flip the order to prevent that.

Cc: "11.2 12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

radeonsi: advertise 8 bits subpixel precision for viewport bounds

Signed-off-by: Józef Kucia <joseph.kucia@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>

r600: advertise 8 bits subpixel precision for viewport bounds

Signed-off-by: Józef Kucia <joseph.kucia@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>

gallium: add a cap for VIEWPORT_SUBPIXEL_BITS (v2)

This allows Gallium drivers to advertise the subpixel precision
for floating point viewports bounds.

v2:
  - Set ViewportSubpixelBits in st_init_limits.

Signed-off-by: Józef Kucia <joseph.kucia@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0: disable MS images on GM107+

MS images have to be handled explicitly and I don't plan to implement
them for now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50/ir: print OP_SUREDB subops in debug mode

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

gm107/ir: add emission for SUREDx

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

gm107/ir: add emission for SUSTx and SULDx

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

gm107/ra: fix constraints for surface operations

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

gm107/ir: lower surface operations

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0: bind images for 3d/cp shaders on GM107+

On Maxwell, images binding is slightly different (and much better)
regarding Fermi and Kepler because a texture view needs to be uploaded
for each image and this is going to simplify the thing a lot.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0: increase the tex handles area size in the driver cb

Currently, we can store 32 tex handles of 32-bits integer each and
that fits perfectly with the underlying hardware except on GM107+
which requires to upload a texture view for each images.

This patch increases the number of storable texture handles in the
driver constant buffer from 32 to 40 because we expose 8 images.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

nir: Fix uninitialized use of 'replacement'.

For intrinsics we don't care about, just skip to the next loop iteration
and process the next instruction.  We don't want to execute the rest of
the code.

This was a bug in commit cdfc05ea6e8c87876cdbf588aa8e03d70f3da4bb.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>

i965: Use tex_mocs instead of rb_mocs for GL images.

Fixes a 10-20% performance regression in OglCSDof caused by commit
5a8c89038abab0184ea72664ab390ec6ca58b4d6, which made images (in the
image load/store sense) use BDW_MOCS_PTE instead of BDW_MOCS_WB.

This seems sketchy, as the default PTE value is supposed to be
WB LLC eLLC, which is the same as our MOCS WB setting.  It's only
supposed to change when using a surface for display, which won't
ever happen for images.  Something may be wrong in the kernel...

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

winsys/amdgpu: use pb_cache buckets for fewer pb_cache misses

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

winsys/radeon: use pb_cache buckets for fewer pb_cache misses

This makes Bioshock Infinite with deferred flushing 2.2% faster.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/pb_cache: reduce the number of pointer dereferences

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/pb_cache: divide the cache into buckets for reducing cache misses

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/pb_cache: check parameters that are more likely to fail first

This makes Bioshock Infinite with deferred flushing 2% faster.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: emit PS exports last

This effectively removes s_waitcnt instructions after FP16 exports.

Before:

    v_cvt_pkrtz_f16_f32_e32 v0, v0, v1   ; 5E000300
    v_cvt_pkrtz_f16_f32_e32 v1, v2, v3   ; 5E020702
    exp 15, 0, 1, 0, 0, v0, v1, v0, v0   ; F800040F 00000100
    s_waitcnt expcnt(0)                  ; BF8C0F0F
    v_cvt_pkrtz_f16_f32_e32 v0, v4, v5   ; 5E000B04
    v_cvt_pkrtz_f16_f32_e32 v1, v6, v7   ; 5E020F06
    exp 15, 1, 1, 0, 0, v0, v1, v0, v0   ; F800041F 00000100
    s_waitcnt expcnt(0)                  ; BF8C0F0F
    v_cvt_pkrtz_f16_f32_e32 v0, v8, v9   ; 5E001308
    v_cvt_pkrtz_f16_f32_e32 v1, v10, v11 ; 5E02170A
    exp 15, 2, 1, 0, 0, v0, v1, v0, v0   ; F800042F 00000100
    s_waitcnt expcnt(0)                  ; BF8C0F0F
    v_cvt_pkrtz_f16_f32_e32 v0, v12, v13 ; 5E001B0C
    v_cvt_pkrtz_f16_f32_e32 v1, v14, v15 ; 5E021F0E
    exp 15, 3, 1, 1, 1, v0, v1, v0, v0   ; F8001C3F 00000100
    s_endpgm                             ; BF810000

After:

    v_cvt_pkrtz_f16_f32_e32 v0, v0, v1   ; 5E000300
    v_cvt_pkrtz_f16_f32_e32 v1, v2, v3   ; 5E020702
    v_cvt_pkrtz_f16_f32_e32 v2, v4, v5   ; 5E040B04
    v_cvt_pkrtz_f16_f32_e32 v3, v6, v7   ; 5E060F06
    exp 15, 0, 1, 0, 0, v0, v1, v0, v0   ; F800040F 00000100
    v_cvt_pkrtz_f16_f32_e32 v4, v8, v9   ; 5E081308
    v_cvt_pkrtz_f16_f32_e32 v5, v10, v11 ; 5E0A170A
    exp 15, 1, 1, 0, 0, v2, v3, v0, v0   ; F800041F 00000302
    v_cvt_pkrtz_f16_f32_e32 v6, v12, v13 ; 5E0C1B0C
    v_cvt_pkrtz_f16_f32_e32 v7, v14, v15 ; 5E0E1F0E
    exp 15, 2, 1, 0, 0, v4, v5, v0, v0   ; F800042F 00000504
    exp 15, 3, 1, 1, 1, v6, v7, v0, v0   ; F8001C3F 00000706
    s_endpgm                             ; BF810000

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: set optimal settings in COMPUTE_RESOURCE_LIMITS

ported from Vulkan

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: really wait for the second EOP event and not the first one

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: remove RADEON_FLUSH_KEEP_TILING_FLAGS flag

always set

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

nir/algebraic: Optimize fabs(u2f(x))

I noticed this when I tried to do frexp(float(some_unsigned)) in the
ir_unop_find_lsb lowering pass.  The code generated for frexp() uses
fabs, and this resulted in an extra instruction.  Ultimately I ended up
not using frexp.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

st/mesa: Enable MESA_shader_integer_functions on all GLSL 1.30 platforms

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Enable MESA_shader_integer_functions on all GLSL 1.30 platforms

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Don't lower uaddCarry and usubBorrow in both GLSL IR and NIR

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Update assertion to account for Gen < 7

Previously SHADER_OPCODE_MULH could only exist on Gen7+, so the
assertion assumed the Gen7+ accumulator rules.  A future patch will
allow this instruction on at least Gen6, so update the assertion.

v2: Use get_lowered_simd_width instead of open coding it.  Suggested by
Curro.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com> [v1]

i965: Use LZD to implement nir_op_find_lsb on Gen < 7

v2: Rebase on changes to previous two patches.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Use LZD to implement nir_op_ifind_msb on Gen < 7

v2: Retype LZD source as UD to avoid potential problems with 0x80000000.
Suggested by Matt.  Also update comment about problem values with
LZD(abs(x)).  Suggested by Curro.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Use LZD to implement nir_op_ufind_msb

This uses one less instruction.

v2: Move emit_find_msb_using_lzd out of the visitor classes.  Suggested
by Curro.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Always enable GL_ARB_shading_language_packing

With the existing lowering passes, the functions from this extension
become a bunch of bit twiddling operations that have always been
supported.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Move enable of EXT_shader_integer_mix

This extension does not depend on the Gen.  It only depends on the
availability of GLSL 1.30.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

glsl: Add lowering pass for ir_bin_imul_high

This isn't the lowering pass you want.  Most GPUs that can support GLSL
1.30 have a multiply unit that can do something more interesting than
32x32->32.  Many have 32x16->48.  Any GPU that does, should do the
lowering in the backend.  This is just the thing that will always work.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

glsl: Add lowering pass for ir_unop_find_msb

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

glsl: Add lowering pass for ir_unop_find_lsb

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

glsl: Add lowering pass for ir_unop_bitfield_reverse

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

glsl: Add lowering pass for ir_quadop_bitfield_insert

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

glsl: Add lowering pass for ir_triop_bitfield_extract

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

glsl: Add lowering pass for ir_unop_bit_count

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

MESA_shader_integer_functions: Allow new function overload matching rules

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

MESA_shader_integer_functions: Allow implicit int->uint conversions

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

MESA_shader_integer_functions: Expose new built-in functions

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

MESA_shader_integer_functions: Boiler plate extension tracking

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

MESA_shader_integer_functions: Add extension specification

v2: Fix typo in #extension line noticed by Ken.

v3: Update spec status.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

gm107/ir: make use of ADD32I for all immediates

ADD only allows to emit 19-bits immediates.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: <mesa-stable@lists.freedesktop.org>

gm107/ir: add missing NEG modifier for IADD32I

Like FADD32I, the NEG modifier of src0 is at position 56.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org

ddebug: Fix trivial typo in stderr message

Signed-off-by: Andreas Boll <andreas.boll.dev@gmail.com>

configure.ac: Use ${datarootdir} for --with-vulkan-icddir help string too

The help string wasn't updated in cbc37f7.

Fixes: cbc37f7 ("anv: install the intel_icd.json to ${datarootdir} by
default")

Signed-off-by: Andreas Boll <andreas.boll.dev@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Cc: mesa-stable@lists.freedesktop.org

vl: fix memory leak

CovID: 1363008
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

vl: add entry point

Add entrypoint to distinguish H.264 decode and encode. For example, in patch
5/11 when is calling "VaCreateContext", "pps" and "sps" shouldn't be allocated
for H.264 encoding. So we need to use the entry_point to determine this is
H.264 decode or H.264 encode. We can use config to determine the entrypoint
since config_id is passed to us for VaCreateContext call. However, for
VaDestoyContext call, only context_id is passed to us. So we need to know the
entrypoint in order to not free the pps/sps for encoding case.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

nv50,nvc0: srgb rendering is only available for rgba/bgra

Mark both L8_SRGB and L8A8_SRGB as non-renderable (the latter already
didn't have the bind flags). This makes the state tracker pick a
different format when rendering is required, or mark the fb as
incomplete. This fixes:

  bin/getteximage-formats init-by-clear-and-render -auto -fbo
  bin/getteximage-formats init-by-rendering -auto -fbo

which previously ran into srgb-encoding differences.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable@lists.freedesktop.org

nvc0: add support for BGRA8 images

This is useful for pbo downloads, which are now accelerated with images.
BGRA8 is a moderately common format to do that in.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

i965: Skip update_texture_surface when the plane doesn't exist

Thanks to rebase fail, recent surface state changes (commits 7e951cd56,
8521ce1a7, and 69c0dc5c53) effectively reverted 727a9b24933 and 367cf3a2e3e
which was unintentional.  This should bring it back.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

glsl: use linked shaders rather than compiled shaders

At this point there is no reason not to be using the linked shaders,
using the linked shaders should be faster and will make things simpler
for upcoming shader cache work.

The previous variable name suggests the linked shaders were intended
to be used here anyway.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

The extension is already exposed, this simply marks it as done.

Signed-off-by: Lars Hamre <chemecse@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

docs: Fix typo in extension name

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>

docs: Add support for GL_KHR_texture_compression_astc_sliced_3d

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reported-by: Ilia Mirkin <imirkin@alum.mit.edu>

Revert "docs: Mark KHR_texture_compression_astc_sliced_3d done on i965"

This reverts commit 82f8c239506ef126dcad266156f8945c62dc6bc9.

KHR_texture_compression_astc_sliced_3d is not a requirement for
GLES 3.2.

Reported-by: Ilia Mirkin <imirkin@alum.mit.edu>\
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>

docs: Mark KHR_texture_compression_astc_sliced_3d done on i965

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

i965/gen9: Enable KHR_texture_compression_astc_sliced_3d

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

mesa: Add the infrastructure for KHR_texture_compression_astc_sliced_3d

V2: Drop the changes to gl.xml.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

radeon/uvd: add session context buffer for polaris 10/11 v2

This way we have unlimited UVD sessions.

v2: only enable it when kernel supports it as well.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>

vl/dri3: fix a memory leak from front buffer

Inspired by fix for mem leak of vdpau interop, resource_from_handle
set texture reference count, that need to be decreased and released,
recall there is a similar case for DRI3, that is with VA-API glx
extension, there is temporary TFP(texture from pixmap), we target it
through dma-buf. leak happens when without count down the reference.

Checked and found with mpv vo=opengl case, there only one static TFP,
the leak happens once, but for totem player using gstreamer VA-API glx,
the dynamic TFP for each frame, so leak quite a bit.

This fixes mem leak for mpv and totem.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>

i965/tes/scalar: fix 64-bit indirect input loads

We totally ignored this before because there were no piglit tests for
indirect loads in tessellation stages with doubles.

Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

i965/tcs/scalar: only update imm_offset for second message in 64bit input loads

Our indirect URB read messages take both a direct and an indirect offset
so when we emit the second message for a 64-bit input load we can just
always incremement the immediate offset, even for the indirect case.

Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

i965: Move pulls_bary setting to emit_pixel_interpolator_send().

pulls_bary should be set when the shader uses a pixel interpolator
message.  So, setting it from the function that emits pixel interpolator
messages makes a lot of sense.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

i965: Write gl_FragCoord directly to the destination.

This patch makes emit_general_interpolation take a destination register
as an argument, and write directly to that.  This is simpler than the
old approach of ralloc'ing a register, writing to that temporary, and
then making the caller emit per-component MOVs to copy it to the actual
destination.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

i965: Drop has_pln checks in unlit centroid workaround.

The unlit centroid workaround starts being necessary on Gen6, which
is the first platform with multisampling.  PLN exists on G45+, so all
platforms which need this workaround have PLN.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>