Marek Olšák [Thu, 6 Jul 2017 00:14:53 +0000 (02:14 +0200)]
radeonsi: don't call gallivm_init_llvm_targets
It's for initializing the native (x86) target.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 4 Jul 2017 15:29:46 +0000 (17:29 +0200)]
gallium/radeon: reallocate suballocated buffers when exported
This should fix exports of suballocated buffers.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 4 Jul 2017 15:26:31 +0000 (17:26 +0200)]
gallium/radeon: flush the context after in-place texture realloc before export
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Mark Thompson [Sat, 15 Jul 2017 18:51:56 +0000 (19:51 +0100)]
st/va: Fix scaling list ordering for H.265
Mesa here requires the scaling lists in diagonal scan order, but
VAAPI passes them in raster scan order. Therefore, rearrange the
elements when copying.
v2: Move scan tables to vl_zscan.c.
Fix type in size assertion.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Mark Thompson <sw@jkqxz.net>
Reviewed-by: Christian König <christian.koenig@amd.com>
Emil Velikov [Fri, 14 Jul 2017 15:18:59 +0000 (16:18 +0100)]
radv: advertise v6 of the wayland surface extension
Jason updated the Khronos spec to explicitly state that Wayland surfaces
must support VK_PRESENT_MODE_MAILBOX_KHR.
ANV did so since day one (back in 2015)
Cc: mesa-stable@lists.freedesktop.org
Cc: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: Dave Airlie <airlied@redhat.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Emil Velikov [Fri, 14 Jul 2017 15:14:14 +0000 (16:14 +0100)]
anv: advertise v6 of the wayland surface extension
Jason updated the Khronos spec to explicitly state that Wayland surfaces
must support VK_PRESENT_MODE_MAILBOX_KHR.
ANV did so since day one (back in 2015)
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Emil Velikov [Thu, 13 Jul 2017 16:43:10 +0000 (17:43 +0100)]
i965: use strtol to convert the integer deviceID override
One can override the deviceID, by setting the INTEL_DEVID_OVERRIDE
variable. A few symbolic names or a numerical value for the actual
device ID is accepted.
At the same time we're using strtod (string to double) to convert the
string to a decimal numeral. A seeming thinko, made by the original
commit that introduces the code in libdrm_intel and got here with the
import.
Fixes: 514db96c117a ("i965: Import libdrm_intel.")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Marek Olšák [Wed, 12 Jul 2017 19:21:38 +0000 (21:21 +0200)]
gallium/u_blitter: don't use TXF for scaled blits
There seems to be a rounding difference with F2I vs nearest filtering.
The precise problem in the rounding is unknown.
This fixes an incorrect output with OpenMAX encoding.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Lionel Landwerlin [Sun, 16 Jul 2017 14:28:09 +0000 (15:28 +0100)]
anv: ensure device name contains terminating character
v2: Use sizeof() (Chris)
CID:
1415113
Reported-by: Grazvydas Ignotas <notasas@gmail.com>
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Lionel Landwerlin [Sun, 16 Jul 2017 14:17:25 +0000 (15:17 +0100)]
i965: miptree: silence coverity warning
This probably can't happen, but we're better off with initialized
variables.
CID:
1415114
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Marek Olšák [Tue, 4 Jul 2017 21:34:09 +0000 (23:34 +0200)]
mesa: flag _NEW_TEXTURE_OBJECT for GL_TEXTURE_LOD_BIAS_EXT
Only the compatibility profile can set it.
It was done incorrectly when we split _NEW_TEXTURE.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Kenneth Graunke [Fri, 14 Jul 2017 03:43:57 +0000 (20:43 -0700)]
meta: Actually initialize ImmutableLevels to 1.
Otherwise, ImmutableLevels is 0, which is an illegal value. Later,
_mesa_meta_setup_sampler will use _mesa_texture_parameteriv to set
texObj->MaxLevel = CLAMP(params[0], texObj->BaseLevel,
texObj->ImmutableLevels - 1);
which turns into a completely bogus CLAMP(value, 0, -1)...where the
upper bound is smaller than the lower bound. This ends up being -1
today due to the way CLAMP is implemented, which is a bogus MaxLevel.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Fri, 14 Jul 2017 21:46:09 +0000 (14:46 -0700)]
dri: Make classic drivers allow __DRI_CTX_FLAG_NO_ERROR.
Grigori recently added EGL_KHR_create_context_no_error support,
which causes EGL to pass a new __DRI_CTX_FLAG_NO_ERROR flag to
drivers when requesting an appropriate context mode.
driContextSetFlags() will already handle it properly for us, but the
classic drivers all have code to explicitly balk at unknown flags. We
need to let it through or they'll fail to create a no_error context.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Grigori Goronzy <greg@chown.ath.cx>
Samuel Pitoiset [Fri, 7 Jul 2017 07:52:05 +0000 (09:52 +0200)]
ddebug: fix parsing of the pipelined mode
Trivial.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Dave Airlie [Thu, 2 Mar 2017 21:39:10 +0000 (21:39 +0000)]
radv: predicate cmask eliminate when using DCC.
When using DCC some clear values don't require a cmask eliminate
step. This patch adds support for black and black with alpha 1,
there are other values, but I don't have access to a comprehensive list.
This works by setting the cmask eliminate predicate when doing the
fast clear, and later when doing the cmask elimination making sure
the draws are predicated.
This increases the fps on Sascha Willems deferred.
Tonga: 580fps->670fps on a Tonga PRO card.
Polaris 730->850fps
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Sun, 25 Jun 2017 23:52:07 +0000 (00:52 +0100)]
radv/clear: add r32g32b32a32 fast clear support (v2)
We can only fast clear 128-bit images if the r/g/b channels
are the same, and we are using DCC.
For DCC we'll bail out on translate if this isn't true,
and we catch cmask clears explicitly.
v2: remove 64-bit block (Bas), add uint32 as well.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Sun, 9 Jul 2017 19:27:48 +0000 (20:27 +0100)]
amd/addrlib: fix typo in api name.
This fixes the misspelling of ALIGNMENTS in addrlib.
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 7 Jul 2017 05:56:57 +0000 (06:56 +0100)]
radv: set cb base tile swizzles for MRT speedups (v4)
This patch uses addrlib to workout the tile swizzles according
to the surface index. It seems to produce the same values as
amdgpu-pro for the deferred test.
v2: don't apply swizzle to CMASK. the eg docs don't mention
it, and we clearly don't align cmask for that.
v3: disable surf index for dedicated images, as these will
most likely be shared, and I don't think the metadata has
space for this info in it yet.
v4: update for shareable images, rename combined_swizzle
to tile_swizzle
This gets the deferred demo from 730->950fps on my rx480.
(dcc cmask elim predication patches get it further)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 11 Jul 2017 02:02:09 +0000 (03:02 +0100)]
radv: allow clear merging for depth/stencil with no care stencil
Some of the Sascha Willems demos pick a D32/S8 format for the depth
buffer, then do a LOAD_OP_CLEAR/LOAD_OP_DONT_CARE on it, which means
we don't get to merge the undefined->depth and clear htile transitions.
This add the stencil aspect to the pending clears if there is a depth
clear pending and the stencil aspect is don't care.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Sat, 15 Jul 2017 17:55:47 +0000 (19:55 +0200)]
radv: Remove NV dedicated alloc extension.
To not confuse apps in thinking it might be faster.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Andres Rodriguez <andresx7@gmail.com>
Bas Nieuwenhuizen [Sat, 15 Jul 2017 17:54:13 +0000 (19:54 +0200)]
radv: Use the KHR dedicated alloc for the WSI.
NV isn't valid for external images anymore.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Fixes: 6ddc64b93ea "radv: Add support for VK_KHR_dedicated_allocation."
Reviewed-by: Andres Rodriguez <andresx7@gmail.com>
Jason Ekstrand [Sat, 15 Jul 2017 00:08:01 +0000 (02:08 +0200)]
radv: Implement VK_KHR_external_memory
This effectively reverts commit
43a171878bb4b5aedb36a. Technically,
VK_KHR_get_memory_requirements2 and VK_KHR_dedicated_allocation are
required for the KHR version but this at least restores the removed
functionality. This patch builds but has received zero testing.
Acked-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Sat, 15 Jul 2017 00:08:00 +0000 (02:08 +0200)]
radv: Add support for VK_KHR_dedicated_allocation.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Sat, 15 Jul 2017 00:07:59 +0000 (02:07 +0200)]
radv: Add support for VK_KHR_get_memory_requirements2.
Fished the SparseImage call out of the headers as the spec missed
the definition.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Dave Airlie <airlied@redhat.com>
Jason Ekstrand [Thu, 13 Jul 2017 19:18:15 +0000 (12:18 -0700)]
anv: Implement VK_KHR_external_memory_*
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Fri, 28 Apr 2017 12:17:38 +0000 (05:17 -0700)]
anv: Implement VK_KHR_dedicated_allocation
We always recommend sub-allocation and don't do anything special for
dedicated allocations.
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Fri, 28 Apr 2017 12:13:08 +0000 (05:13 -0700)]
anv: Implement VK_KHR_get_memory_requirements2
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Thu, 13 Jul 2017 19:28:46 +0000 (12:28 -0700)]
anv: Advertise version 1.0.54
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Thu, 13 Jul 2017 18:57:07 +0000 (11:57 -0700)]
vulkan: Update to the new 1.0.54 spec XML and headers
There is one small ANV change here because we used the
VK_ERROR_INVALID_EXTERNAL_HANDLE_KHX enum in the BO cache and that had
to be updated to have the _KHR suffix.
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Sat, 15 Jul 2017 15:58:55 +0000 (08:58 -0700)]
radv: Drop support for VK_KHX_external_semaphore_*
These have been formally deprecated by Khronos never to be shipped
again. The KHR versions should be implemented/used instead.
Acked-by: Dave Airlie <airlied@redhat.com>
Jason Ekstrand [Thu, 13 Jul 2017 18:40:46 +0000 (11:40 -0700)]
anv: Drop support for VK_KHX_external_semaphore_*
These have been formally deprecated by Khronos never to be shipped
again. The KHR versions should be implemented/used instead.
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Thu, 13 Jul 2017 18:18:39 +0000 (11:18 -0700)]
anv: Drop support for VK_KHX_external_memory_*
These have been formally deprecated by Khronos never to be shipped
again. The KHR versions should be implemented/used instead.
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Matt Turner [Sat, 15 Jul 2017 05:01:11 +0000 (22:01 -0700)]
i965: Compile with -msse2 (instead of -msse2)
Ian noted that were were two Pentium 4 Extreme Edition LGA 775 CPUs, and
they only have SSE2.
Matt Turner [Fri, 7 Jul 2017 04:31:05 +0000 (21:31 -0700)]
i965: Compile with -msse3
All CPUs that can be paired with a GPU supported by i965_dri.so supports
SSE3. This allows us to ensure that some vectorized version of the tiled
memcpy path is enabled on 32-bit systems.
This also ensures that __builtin_ia32_clflush is always usable.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101774
Tested-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Kenneth Graunke [Fri, 14 Jul 2017 21:26:42 +0000 (14:26 -0700)]
egl: Fix predecence problem when setting __DRI_CTX_FLAG_NO_ERROR
This accidentally set __DRI_CTX_FLAG_NO_ERROR whenever any flags were
present. Just needs extra parenthesis.
Fixes: 4909519a6655 (egl: Add EGL_KHR_create_context_no_error support)
Reviewed-by: Grigori Goronzy <greg@chown.ath.cx>
Tested-by: Mark Janes <mark.a.janes@intel.com>
Petr Sebor [Tue, 11 Jul 2017 10:08:47 +0000 (12:08 +0200)]
drirc: whitelist glthread for Euro Truck Simulator 2
Petr Sebor [Tue, 11 Jul 2017 10:08:46 +0000 (12:08 +0200)]
drirc: whitelist glthread for American Truck Simulator
Grigori Goronzy [Fri, 14 Jul 2017 21:12:17 +0000 (23:12 +0200)]
mesa/marshal: fix Windows build
This was broken by commit
1ad24faa.
Reported by AppVeyor:
https://ci.appveyor.com/project/mesa3d/mesa/build/4918
Edmondo Tommasina [Mon, 10 Jul 2017 19:12:11 +0000 (21:12 +0200)]
drirc: whitelist glthread for The Witcher 2
Performance delta on AMD Phenom II X3 720 / RX 470
The Witcher 2: +18%
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Edmondo Tommasina [Sun, 9 Jul 2017 19:43:09 +0000 (21:43 +0200)]
drirc: whitelist glthread for Civilization 5
Performance delta on AMD Phenom II X3 720
Civilization 5: +28%
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Tim Rowley [Fri, 14 Jul 2017 20:01:35 +0000 (15:01 -0500)]
swr: JitManager runtime determination of architecture
Fixes performance regression from
f50aa21456d - was forcing internal
code generation to target AVX (no gather, etc).
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Andres Gomez [Fri, 14 Jul 2017 19:27:26 +0000 (22:27 +0300)]
docs: update calendar, add news item and link release notes for 17.1.5
Signed-off-by: Andres Gomez <agomez@igalia.com>
Andres Gomez [Fri, 14 Jul 2017 19:22:50 +0000 (22:22 +0300)]
docs: add sha256 checksums for 17.1.5
Signed-off-by: Andres Gomez <agomez@igalia.com>
Andres Gomez [Fri, 14 Jul 2017 18:58:05 +0000 (21:58 +0300)]
docs: add release notes for 17.1.5
Signed-off-by: Andres Gomez <agomez@igalia.com>
Grigori Goronzy [Thu, 29 Jun 2017 05:39:55 +0000 (07:39 +0200)]
st/mesa: Add KHR_no_error toggle to driconf
Allows applications to be whitelisted.
v2: Remove misguided DRI common part.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Grigori Goronzy [Thu, 29 Jun 2017 00:44:03 +0000 (02:44 +0200)]
egl: Add EGL_KHR_create_context_no_error support
This only adds the EGL side, needs to be plumbed into Mesa frontend.
v2: Add check for extension availability.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Grigori Goronzy [Thu, 29 Jun 2017 02:39:22 +0000 (04:39 +0200)]
st/mesa: Add support for KHR_no_error flag
Add a new context flag and plumb it through the various layers of the
context creation code to set up dispatch tables for the no-error mode.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Grigori Goronzy [Thu, 29 Jun 2017 01:24:15 +0000 (03:24 +0200)]
dri: Add KHR_no_error DRI extension
This basic extension allows usage of the __DRI_CTX_FLAG_NO_ERROR flag.
This includes support code for classic Mesa drivers to switch on the
no-error mode if the flag is set.
v2: Move to common DRI code.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Grigori Goronzy [Sun, 9 Jul 2017 23:55:52 +0000 (01:55 +0200)]
mesa/marshal: fix glNamedBufferData with NULL data
The semantics are similar to glBufferData.
Tested-by: Marc Dietrich <marvin24@gmx.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Grigori Goronzy [Sun, 9 Jul 2017 01:27:12 +0000 (03:27 +0200)]
mesa/marshal: add marshalling for glClearBuffer*
Add async marshalling/unmarshalling for all glClearBuffer variants.
These entry points are commonly used in general and Alien Isolation
specifically uses glClearBufferiv. Slightly reduces the number of
thread synchronizations with glthread in that game.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Grigori Goronzy [Sun, 9 Jul 2017 00:30:46 +0000 (02:30 +0200)]
mesa/marshal: extract ClearBuffer helpers
Extract clear buffer helper functions in preparation for adding
marshal/unmarshal functions for the various glClearBuffer variants.
v2: Fix command size.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Christoph Haag [Fri, 14 Jul 2017 07:59:38 +0000 (09:59 +0200)]
gallium/hud: use double values for all graphs
The fps graph for example calculates the fps as double with small
variations based on when query_new_value() is called, which causes
many values to be truncated on the cast to uint64_t.
The HUD internally stores the values as double, so just use double
everywhere instead of fixing this with rounding. Using doubles also
allows the hud to show small variations instead of being clamped to
discrete values.
v2: Don't print decimals in the dump file when not necessary
Signed-off-by: Christoph Haag <haagch+mesadev@frickel.club>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Lucas Stach [Fri, 14 Jul 2017 15:21:42 +0000 (17:21 +0200)]
Revert "etnaviv: add support for snorm textures"
This reverts commit
d8b2ccdb880f, which causes priglit regressions on GPUs
with SNORM support. We'll have another try at enabling this feature after
the 17.2 branchpoint.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Wladimir J. van der Laan [Fri, 14 Jul 2017 11:26:24 +0000 (13:26 +0200)]
etnaviv: reset indexed rendering information when not rendering indexed
A dangling bo object would result in memory corruption while loading a
level in ioquake3_opengl2.
Fixes: 330d0607ed60 (gallium: remove pipe_index_buffer and set_index_buffer)
Suggested-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Wladimir J. van der Laan [Tue, 11 Jul 2017 13:07:09 +0000 (15:07 +0200)]
etnaviv: Use the correct LOG instruction on GC3000
GC3000 has a new LOG instruction, similar to the new SIN and COS instructions.
Generate the new instruction sequence when appropriate; there are
two occasions, as part of LIT and the generator for the LG2
instruction itself.
Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Lucas Stach [Mon, 26 Jun 2017 15:26:20 +0000 (17:26 +0200)]
etnaviv: flush source TS before resolve
If we blit from a rendertarget or a depthstencil buffer there might still
be dirty data in the TS buffer which needs to be flushed out.
Fixes missing shadow tiles in glmark2 shadow.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Philipp Zabel [Tue, 9 May 2017 16:26:57 +0000 (18:26 +0200)]
etnaviv: flush color cache and depth cache together before resolves
Before resolving a rendertarget or a depth/stencil resource into a
texture, flush both the color cache and the depth cache together.
It is unclear whether this is necessary for the following stall to
work properly, or whether the depth flush just adds enough time
for the color cache flush to finish before the resolver is started,
but this change removes artifacts that otherwise appear if a texture
is sampled directly after rendering into it.
The test case is a simple QML scene graph with a QtWebEngine based
WebView rendered on top of a blue background:
import QtQuick 2.0
import QtQuick.Window 2.2
import QtWebView 1.1
Window {
Rectangle {
id: background
anchors.fill: parent
color: "blue"
}
WebView {
id: webView
anchors.fill: parent
}
Component.onCompleted: {
webView.url = "<some animated website>"
}
}
If the website is animated, the WebView renders the site contents into
texture tiles and immediately afterwards samples from them to draw the
tiles into the Qt renderbuffer. Without this patch, a small irregular
triangle in the lower right of each browser tile appears solid blue, as
if the texture sampler samples zeroes instead of the website contents,
and the previously rendered blue Rectangle shows through.
Other attempts such as adding a pipeline stall before the color flush or
a TS cache flush afterwards or flushing multiple times, with stalls
before and after each flush, have shown no effect.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Lucas Stach [Thu, 13 Jul 2017 16:58:04 +0000 (18:58 +0200)]
st/mesa: handle stfbi being NULL on entry of st_framebuffer_reuse_or_create
Apparently this can happen. Just bail out early in that case, as all the called
functions return NULL in that case.
Fixes weston-terminal for me.
Fixes: 147d7fb772a7 ("st/mesa: add a winsys buffers list in st_context")
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Daniel Stone [Sat, 10 Jun 2017 13:54:44 +0000 (14:54 +0100)]
egl/wayland: Use MIN2 for wl_drm version
Use a slightly more explicit version cap for binding wl_drm, so we can
add other interfaces with different versioning schemes later.
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Daniel Stone [Sat, 10 Jun 2017 13:54:05 +0000 (14:54 +0100)]
egl/wayland: Fix whitespace damage
Convert tabs to spaces, fix misalignments.
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Daniel Stone [Fri, 9 Jun 2017 13:57:20 +0000 (14:57 +0100)]
util: Remove u_math from u_vector
u_vector.h doesn't actually use anything from u_math, but it does mean
everyone has to pull in src/gallium/auxiliary/util includes.
Just remove it, adding a <string.h> include to u_vector.c to cover
memcpy.
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Eric Engestrom [Fri, 14 Jul 2017 10:14:28 +0000 (11:14 +0100)]
configure: only install khrplatform.h if needed
khrplatform.h is only used by EGL and GLES; let's only install it when
one of those is enabled.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Jussi Kukkonen <jussi.kukkonen@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Eric Engestrom [Mon, 10 Jul 2017 12:27:25 +0000 (13:27 +0100)]
scons: split out check_header() helper
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Juan A. Suarez Romero [Fri, 14 Jul 2017 10:31:38 +0000 (10:31 +0000)]
anv/pipeline: do not use BITFIELD64_BIT()
In the previous commit, forgot to apply v2 suggestions.
Fixes: 28d0c38 (anv/pipeline: use unsigned long long constant to check
enable vertex inputs)
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Juan A. Suarez Romero [Thu, 13 Jul 2017 14:33:57 +0000 (14:33 +0000)]
anv/pipeline: use unsigned long long constant to check enable vertex inputs
When initializing the ANV pipeline, one of the tasks is checking which
vertex inputs are enabled. This is done by checking if the enabled bits
in inputs_read.
But the mask to use is computed doing `(1 << (VERT_ATTRIB_GENERIC0 +
desc->location))`. The problem here is that if location is 15 or
greater, the sum is 32 or greater. But C is handling 1 as a 32-bit
integer, which means the displaced bit is out of range and thus the full
value is 0.
Thus, use 1ull, which is an unsigned long long value.
This fixes:
dEQP-VK.pipeline.vertex_input.max_attributes.16_attributes.binding_one_to_one.interleaved
v2: use 1ull instead of BITFIELD64_BIT() (Matt Turner)
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Cc: mesa-stable@lists.freedesktop.org
Kenneth Graunke [Tue, 29 Nov 2016 13:20:20 +0000 (05:20 -0800)]
i965: Use pushed UBO data in the scalar backend.
This actually takes advantage of the newly pushed UBO data, avoiding
pull loads.
Improves performance in GLBenchmark Manhattan 3.1 by:
HSW: ~1%, BDW/SKL/KBL GT2: 3-4%, SKL GT4: 7-8%, APL: 4-5%.
(thanks to Eero Tamminen for these numbers)
shader-db results on Skylake, ignoring programs with spill/fill changes:
total instructions in shared programs:
13963994 ->
13651893 (-2.24%)
instructions in affected programs:
4250328 ->
3938227 (-7.34%)
helped: 28527
HURT: 0
total cycles in shared programs:
179808608 ->
172535170 (-4.05%)
cycles in affected programs:
79720410 ->
72446972 (-9.12%)
helped: 26951
HURT: 1248
LOST: 46
GAINED: 21
Many "Deus Ex: Mankind Divided" shaders which already spilled end up
spill a lot more (about 240 programs hurt, 9 helped). The cycle
estimator suggests this is still overall a win (-0.23% in cycle counts)
presumably because we trade pull loads for fills.
v2: Drop "PULL" environment variable left in for initial debugging
(caught by Matt).
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Fri, 2 Jun 2017 16:54:31 +0000 (09:54 -0700)]
i965: Factor out push locations.
With UBOs, the answer of "have we decided to push this uniform" gets
a bit more complicated - for one, we have multiple surfaces. This
patch refactors things so we can add the new code in a single place.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Tue, 29 Nov 2016 10:47:15 +0000 (02:47 -0800)]
i965: Push UBO data, but don't use it just yet.
This patch starts uploading UBO data via 3DSTATE_CONSTANT_* packets,
and updates the compiler to know that there's extra payload data, so
things continue working. However, it still issues pull loads for all
data. I wanted to separate the two aspects for greater bisectability.
v2: Update for new intel_bufferobj_buffer parameter.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Sat, 3 Jun 2017 18:46:15 +0000 (11:46 -0700)]
i965: Pad buffer objects by 2kB in robust contexts to avoid OOB access.
This is an annoyingly big hammer, but it seems less mean than disabling
UBO pushing, and I'm not sure what else to do.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Tue, 29 Nov 2016 09:37:49 +0000 (01:37 -0800)]
i965: Stop re-uploading push constants after URB reconfiguration.
Previously we would re-upload the constant data to the batchbuffer,
then re-emit the packets. We only need to do the last step (causing
the existing data in the batchbuffer to be re-uploaded to the push
constant staging area in the L3).
Now that we've separated the two, it's pretty easy to accomplish.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Tue, 29 Nov 2016 09:06:50 +0000 (01:06 -0800)]
i965: Separate uploading push constant data from the pointer packets.
I hope to upload UBO via 3DSTATE_CONSTANT_XS packets, in addition to
normal uniforms. In order to do that, I'll need to re-emit the packets
when UBOs change. But I don't want to re-copy the regular uniform data
to the batchbuffer every time.
This patch separates out the data uploading from the packet submission.
We're running low on dirty bits, so I made the new atom happen on every
draw call, and added a flag to stage_state indicating that we want the
packet for that stage emitted.
I would have preferred to do this outside the atom system, but it has
to happen between the uploading of push constant data and the binding
table upload.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Tue, 29 Nov 2016 11:34:01 +0000 (03:34 -0800)]
i965: Introduce a BRW_NEW_DRAW_CALL dirty bit.
This allows us to have atoms which are signalled on every draw call.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Tue, 27 Jun 2017 21:38:13 +0000 (14:38 -0700)]
i965: Store per-stage push constant BO pointers.
Right now, we always upload new push constant data, and immediately
emit 3DSTATE_CONSTANT_* packets. We call intel_upload_space and store
the resulting BO pointer in brw->curbe.curbe_bo. We read that when
emitting the packets. This works today, but is fragile - it depends on
upload and packet emission being interleaved.
If we instead were to upload all the data, then emit all the packets,
then upload BO wrapping will get us into trouble. For example, the VS
constants may land in one upload BO, but the FS constants may not fit
and land in a second upload BO. Uploading FS constants would overwrite
the brw->curbe.curbe_bo pointer, so when we emitted 3DSTATE_CONSTANT_VS,
we'd get the wrong BO.
I intend to separate out this code in a future commit, so I need to fix
this. To fix it, we simply store a per-stage BO pointer.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Sat, 2 Jan 2016 11:21:28 +0000 (03:21 -0800)]
i965: Select ranges of UBO data to be uploaded as push constants.
This adds a NIR pass that decides which portions of UBOS we should
upload as push constants, rather than pull constants.
v2: Switch to uint16_t for the UBO block number, because we may
have a lot of them in Vulkan (suggested by Jason). Add more
comments about bitfield trickery (requested by Matt).
v3: Skip vec4 stages for now...I haven't finished wiring up support
in the vec4 backend, and so pushing the data but not using it
will just be wasteful.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Mon, 25 Jan 2016 23:23:24 +0000 (15:23 -0800)]
i965: Require a UBO offset alignment of 32 bytes.
Soon, we're going to start providing UBO data to shaders as push
constants, rather than requiring them to issue pull loads. The
3DSTATE_CONSTANT_* commands require 32 byte aligned pointers.
So, we need to increase this from 16 to 32.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Fri, 15 Aug 2014 05:36:45 +0000 (22:36 -0700)]
i965: Switch to absolute addressing for constant buffer 0.
By default, 3DSTATE_CONSTANT_* Constant Buffer 0 is relative to dynamic
state base address. This makes it unusable for pushing UBOs. I'd like
to be able to use all four push buffers.
There is a bit in the INSTPM register (or CS_DEBUG_MODE2 on Skylake)
which controls whether buffer 0 is relative to dynamic state base
address, or simply a normal pointer. Setting that gives us full
flexibility.
We can't currently write this on Haswell and earlier, and will need
to update the kernel command parser, and then do the whole version
checking song and dance.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Wed, 18 Jan 2017 01:18:01 +0000 (17:18 -0800)]
i965: Use async maps for BufferSubData to regions with no valid data.
When writing a region of a buffer via glBufferSubData(), we can write
the data asynchronously if the destination doesn't contain any data.
Even if it's busy, the data was undefined, so the new data is fine too.
Removes all stall avoidance blits on BufferSubData calls in
"Total War: WARHAMMER" on my Skylake GT4.
Decreases the number of stall avoidance blits in Manhattan 3.1:
- Skylake GT4: -18.3544% +/- 6.76483% (n=13)
- Apollolake: -12.1095% +/- 5.24458% (n=13)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Wed, 18 Jan 2017 01:18:01 +0000 (17:18 -0800)]
i965: Track a range of the buffer which contains valid data.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Wed, 7 Jun 2017 20:26:58 +0000 (13:26 -0700)]
i965: Add a "write" parameter to intel_bufferobj_buffer.
This doesn't do anything yet, but soon we'll want to know whether an
access to a buffer section may write that data, or simply reads it.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Rafael Antognolli [Wed, 7 Jun 2017 20:03:43 +0000 (13:03 -0700)]
i965: Convert GS_STATE to genxml.
Merge the code with gen6+ 3DSTATE_GS, and delete brw_gs_state.c,
together with brw_gs_unit_state.
Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Rafael Antognolli [Tue, 6 Jun 2017 16:38:46 +0000 (09:38 -0700)]
i965: Prepare gs_state emitting code to include gen4-5.
Since we always call brw_batch_emit anyways, we can hopefully make things
simpler by calling it only once, and then branching inside its body. This
can be helpful when bringing the gen4-5 code into this function.
Additionally, check for GEN_GEN == 6 instead of < 7 in cases that won't apply
to lower gens.
Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Rafael Antognolli [Tue, 6 Jun 2017 16:49:11 +0000 (09:49 -0700)]
i965: Remove upload_gs_state_for_tf.
This function only emits a particular case of 3DSTATE_GS. Instead, we can do
that inside genX(upload_gs_state), and later reuse part of that code for
emitting gen4-5 state.
There's the additional benefit of allowing us to remove gen6_gs_state.c, which
was only left because of this function.
Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Rafael Antognolli [Mon, 5 Jun 2017 21:44:44 +0000 (14:44 -0700)]
i965: Convert BLEND_CONSTANT_COLOR state to genxml.
It's a very simple conversion, and it allows us to delete brw_cc.c.
Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Rafael Antognolli [Thu, 1 Jun 2017 19:28:41 +0000 (12:28 -0700)]
i965: Convert CC state on gen4-5 to genxml.
Use set_blend_entry_bits and set_depth_stencil_bits to fill most of the
color calc struct, and then manually update the rest.
v2:
- Always check for depth_irb (Ken)
- Always set Backface Stencil Ref (Ken)
- Always set alpha reference value (Ken)
Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Rafael Antognolli [Tue, 20 Jun 2017 00:15:55 +0000 (17:15 -0700)]
i965: Move color calc code around a bit.
This makes the code more consistent accross generations.
Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Rafael Antognolli [Fri, 2 Jun 2017 21:41:19 +0000 (14:41 -0700)]
i965: Check for alpha channel just like in gen6+.
gen6+ uses _mesa_base_format_has_channel() to check for the alpha
channel, while gen4-5 use ctx->DrawBuffer->Visual.alphaBits. By using
_mesa_base_format_has_channel() here we keep the same behavior accross
all gen.
While initially both ways of checking the alpha channel seemed correct
to me, this change also seems to fix fbo-blending-formats piglit test on
gen4.
Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Rafael Antognolli [Thu, 1 Jun 2017 18:41:16 +0000 (11:41 -0700)]
i965: Make a helper function for blend entry related state.
Add a helper function to reuse code that fills blend entry related
state, and make genX(upload_blend_state) use it. This function can later
be used by gen4-5 color calc state to set the blend related bits.
Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Kenneth Graunke [Mon, 8 May 2017 23:30:58 +0000 (16:30 -0700)]
i965: Make a helper function for depth/stencil related state.
Gen4-5 basically glue DEPTH_STENCIL_STATE, COLOR_CALC_STATE, and
BLEND_STATE together into a single COLOR_CALC_STATE structure.
By making a helper function, we'll be able to reuse it when filling
out Gen4-5 COLOR_CALC_STATE without replicating any actual logic.
We use generation-defined typedef to handle the polymorphism.
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Lionel Landwerlin [Thu, 13 Jul 2017 15:39:42 +0000 (16:39 +0100)]
aubinator: don't leak fd of opened aubfile
CID:
1373563
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Lionel Landwerlin [Thu, 13 Jul 2017 15:35:01 +0000 (16:35 +0100)]
anv: don't use strcpy for copying strings
CID:
1358935
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Lionel Landwerlin [Thu, 13 Jul 2017 15:32:54 +0000 (16:32 +0100)]
intel/compiler: no need to check unsigned is >= 0
CID:
1338342
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Lionel Landwerlin [Thu, 13 Jul 2017 15:29:25 +0000 (16:29 +0100)]
i965: fix missing NULL return if allocation fails
CID:
1250585
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Lionel Landwerlin [Thu, 13 Jul 2017 15:23:48 +0000 (16:23 +0100)]
intel/compiler: don't check unsigned is >= 0
CID:
1224468
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Lionel Landwerlin [Thu, 13 Jul 2017 15:11:40 +0000 (16:11 +0100)]
i965: check pointer before dereferencing it
Check that irb isn't NULL before accessing irb->Base.Base.NumSamples.
CID:
1026046
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Lionel Landwerlin [Thu, 13 Jul 2017 15:08:34 +0000 (16:08 +0100)]
i965: map_gtt: check mapping address before adding offset
The NULL check might fail if offset isn't 0.
CID: 971379
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Lionel Landwerlin [Thu, 13 Jul 2017 15:04:28 +0000 (16:04 +0100)]
intel/compiler: remove check unsigned is >= 0
By definition unsigned are always >= 0.
CID: 742212
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Lionel Landwerlin [Thu, 13 Jul 2017 14:37:43 +0000 (15:37 +0100)]
isl: use 64bit arithmetic to compute size
If we allow the size to be more than 2^32, then we should compute it
in 64bit arithmetic otherwise we might run into overflow issues.
CID:
1412892,
1412891
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Connor Abbott [Thu, 6 Jul 2017 19:23:33 +0000 (12:23 -0700)]
nir/lower_io_to_temporaries: don't set compact on shadow vars
The compact flag doesn't make sense on local variables, since the
packing on them is up to the driver. This fixes nir_validate assertions
in some cases, particularly when lower_io_to_temporaries is used on
per-vertex inputs/outputs.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Connor Abbott [Tue, 27 Jun 2017 00:07:21 +0000 (17:07 -0700)]
nir: don't segfault when printing variables with no name
While normally we give variables whose name field is NULL a temporary
name when called from nir_print_shader(), when we were calling from
nir_print_instr() we never bothered, meaning that we just segfaulted
when trying to print out instructions with such a variable. Since
nir_print_instr() is meant to be called while debugging, we don't need
to bother too much about giving a consistent name, but we don't want to
crash in the middle of debugging.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Jason Ekstrand [Tue, 11 Oct 2016 23:39:25 +0000 (16:39 -0700)]
i965/urb: Trigger upload_urb on NEW_BLORP
It's a bit rare, but blorp can trigger a urb reconfiguration. When
that happens, we need to re-upload the URB config. Previoulsy blorp
would set BRW_NEW_URB_SIZE, but this is a pretty big hammer as it
would cause back-to-black blorp operations to reconfigure both times.
Using BRW_NEW_BLORP is a small, more accurate hammer.
v2 (idr): Sort BRW_NEW_ tokens to match brw_recalculate_urb_fence and
gen6_urb.
v3 (idr): Don't whack BRW_NEW_URB_SIZE in blorp. Suggested by Jason.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>