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Reroute clk so PLL output clock is used as sys_clk.
2021-06-03 Staf VerhaegenReroute clk so PLL output clock is used as sys_clk.
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2021-06-03 Staf VerhaegenDuplicate file before patching for clock rerouting.
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2021-04-19 Staf Verhaegenexperiments10_verilog/freepdk_c4m45: Add link for add.py.
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2021-04-19 Staf VerhaegenTop layer -> metal6
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2021-04-19 Staf Verhaegenexperiments9/freepdk_c4m45: Reduce core size.
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2021-04-12 Staf VerhaegendoDesign.py: Disable SRAM placement
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2021-04-12 Staf VerhaegenReduce core size.
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2021-04-12 Staf VerhaegenRight branch of c4m-pdk-freedpk45.
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2021-04-11 Staf VerhaegenUpdate c4m-pdk-freepdk45 submodule.
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2021-04-11 Staf VerhaegenWip of P&R of ls180 with C4M FreePDK45.
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2021-04-11 Staf Verhaegenexperiments9: Ignore pinmux generated files.
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2021-04-11 Staf Verhaegenmksym.sh: Check exitence of alliance-check-toolkit
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2021-04-11 Staf VerhaegenSubmodule for C4M FreePDK45 PDK release files.
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